Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate, the substrate has a first well region and a second well region adjacent to each other, the first well region has first ions, the second well region has second ions, the first ions and the second ions are different in electrical type; a plurality of first fins located on the first well region; a plurality of second fins located on the second well region; an isolation opening located in the substrate, the isolation opening is located between the first well region and the second well region; an isolation layer located on the substrate and in the isolation opening, the isolation layer covers part of the sidewalls of the first fins and the second fins, and the top surface of the isolation layer is lower than the top surfaces of the first fins and the second fins. Through the isolation layer located in the isolation opening, the first well region and the second well region can be effectively isolated, thereby reducing the problem of short circuit between the transistors formed subsequently, so as to improve the performance of the semiconductor structure finally formed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the feature size of devices in integrated circuits is getting smaller and smaller. However, when the feature size of devices is getting smaller and smaller, the length of the channel region between the source and the drain is also getting shorter and shorter. When the length of the channel region is reduced to a certain value, the short channel effect will occur. The short channel effect will affect the performance of the device, thus hindering the further reduction of the feature size of devices in integrated circuits.

[0003] In the prior art, in order to overcome the short channel effect and promote the development of semiconductor technology, the channel material is replaced by germanium-silicon (SiGe) material. Since the germanium-silicon material has a high hole mobility, which is usually 6-25 times the hole mobility of silicon (Si) material, the performance of the device can be greatly improved by using germanium-silicon material as the material of the channel region.

[0004] However, the silicon germanium material channel transistor in the prior art still has many problems. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate has adjacent first and second well regions therein, the first well region has first ions therein, the second well region has second ions therein, the first ions and the second ions are different in electrical type; a plurality of first fins on the first well region; a plurality of second fins on the second well region; an isolation opening in the substrate, the isolation opening is between the first well region and the second well region; an isolation layer on the substrate and in the isolation opening, the isolation layer covers part of the sidewalls of the first fins and the second fins, and the top surface of the isolation layer is lower than the top surfaces of the first fins and the second fins.

[0007] Optionally, the second fin comprises a first region and a second region on the first region, and the materials of the first region and the second region are different.

[0008] Optionally, the material of the first region comprises silicon, and the material of the second region comprises silicon germanium.

[0009] Optionally, the material of the first fin comprises silicon.

[0010] Optionally, the material of the isolation layer comprises silicon oxide, silicon oxycarbide or silicon oxynitride.

[0011] Optionally, the first ion comprises a P-type ion; and the second ion comprises an N-type ion.

[0012] Correspondingly, the technical scheme of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate having a first well region and a second well region adjacent to each other, the first well region having a first ion therein, the second well region having a second ion therein, the first ion and the second ion being of different electrical types; forming an isolation opening, a plurality of first fins and a plurality of second fins, the first fins being located on the first well region, the second fins being located on the second well region, the isolation opening being located between the first well region and the second well region; forming an isolation layer on the substrate and in the isolation opening, the isolation layer covering part of the sidewalls of the first fins and the second fins, and the top surface of the isolation layer being lower than the top surfaces of the first fins and the second fins.

[0013] Optionally, the second fin comprises a first region and a second region located on the first region, and the materials of the first region and the second region are different.

[0014] Optionally, the material of the first region comprises silicon; and the material of the second region comprises silicon germanium.

[0015] Optionally, the material of the first fin comprises silicon.

[0016] Optionally, the forming method of the isolation opening, the first fin and the second fin comprises: forming a first semiconductor material layer and a second semiconductor material layer on the substrate; forming a first patterning layer on the first semiconductor material layer and the second semiconductor material layer, the first patterning layer exposing the top surfaces of part of the first semiconductor material layer and part of the second semiconductor material layer; forming a patterning opening between the first semiconductor material layer and the second semiconductor material layer; and etching the first semiconductor material layer, the second semiconductor material layer, the first well region and the second well region with the first patterning layer and the patterning opening as masks, to form the first fin, the second fin and the isolation opening.

[0017] Optionally, the method for forming the first semiconductor material layer, the second semiconductor material layer and the patterned opening comprises: forming an initial first semiconductor material layer on the substrate; removing part of the initial first semiconductor material layer to form the first semiconductor material layer and an initial first opening, the initial first opening being located on the second well region; forming a side wall on the sidewall of the initial first opening to form a first opening; forming the second semiconductor material layer in the first opening, the second semiconductor material layer being different from the material of the first semiconductor material layer; removing the side wall to form the patterned opening between the first semiconductor material layer and the second semiconductor material layer.

[0018] Optionally, the process for forming the second semiconductor material layer in the first opening comprises an epitaxial growth process.

[0019] Optionally, the method for forming the side wall on the sidewall of the initial first opening comprises: forming an initial side wall on the sidewall and top surface of the initial first opening and the top surface of the first semiconductor material layer; etching back the initial side wall until the top surface of the first semiconductor material layer and the bottom surface of the initial first opening are exposed to form the side wall.

[0020] Optionally, the material of the side wall is different from the material of the first semiconductor material; the material of the side wall is different from the material of the second semiconductor material.

[0021] Optionally, the material of the side wall comprises silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

[0022] Optionally, the method for forming the isolation layer comprises: forming an isolation material layer in the isolation opening and on the substrate, the isolation material layer covering the first fin and the second fin; performing a planarization process on the isolation material layer until the top surfaces of the first fin and the second fin are exposed to form an initial isolation layer; etching back the initial isolation layer to form the isolation layer.

[0023] Optionally, the material of the isolation layer comprises silicon oxide, silicon oxycarbide or silicon oxynitride.

[0024] Optionally, the first ion comprises a P-type ion; the second ion comprises an N-type ion.

[0025] Optionally, the forming method of the substrate comprises: providing an initial substrate; forming a second patterning layer on the initial substrate, the second patterning layer exposes part of the top surface of the initial substrate; taking the second patterning layer as a mask, implanting the first ions into the initial substrate to form the first well region; after forming the first well region, removing the second patterning layer; after removing the second patterning layer, forming a third patterning layer on the initial substrate, the third patterning layer exposes part of the top surface of the initial substrate; taking the third patterning layer as a mask, implanting the second ions into the initial substrate to form the second well region and the substrate.

[0026] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0027] In the structure of the technical scheme of the present application, the isolation port is located in the substrate, the isolation port is located between the first well region and the second well region; the isolation layer is located on the substrate and in the isolation port, the isolation layer covers part of the sidewall of the first fin and the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin. By the isolation layer located in the isolation port, the first well region and the second well region can be effectively isolated, thereby reducing the problem of short circuit between the subsequently formed transistors, so as to improve the performance of the finally formed semiconductor structure.

[0028] In the forming method of the technical scheme of the present application, the isolation port is formed between the first well region and the second well region, and the isolation layer is formed on the substrate and in the isolation port. By the isolation layer located in the isolation port, the first well region and the second well region can be effectively isolated, thereby reducing the problem of short circuit between the subsequently formed transistors, so as to improve the performance of the finally formed semiconductor structure.

[0029] Further, the forming method of the first semiconductor material layer, the second semiconductor material layer and the patterned opening comprises: forming an initial first semiconductor material layer on the substrate; removing part of the initial first semiconductor material layer to form the first semiconductor material layer and an initial first opening, the initial first opening being located on the second well region; forming a side wall on the sidewall of the initial first opening to form a first opening; forming the second semiconductor material layer in the first opening, the material of the second semiconductor material layer being different from that of the first semiconductor material layer; forming a first patterning layer on the first semiconductor material layer and the second semiconductor material layer, the first patterning layer exposing part of the top surface of the first semiconductor material layer and part of the top surface of the second semiconductor material layer; removing the side wall to form the patterned opening between the first semiconductor material layer and the second semiconductor material layer. Since the sidewall of the first opening is a side wall, when the second semiconductor material layer is formed by using an epitaxial growth process, the second semiconductor material layer can only grow from the bottom surface of the first opening, avoiding the formation of a void in the second semiconductor material layer, and further ensuring that the second fin portion formed also does not have the void, thereby improving the performance of the semiconductor structure finally formed.

[0030] Further, the forming method of the substrate comprises: providing an initial substrate; forming a second patterning layer on the initial substrate, the second patterning layer exposing part of the top surface of the initial substrate; implanting the first ions into the initial substrate to form the first well region by using the second patterning layer as a mask; removing the second patterning layer after forming the first well region; forming a third patterning layer on the initial substrate after removing the second patterning layer, the third patterning layer exposing part of the top surface of the initial substrate; implanting the second ions into the initial substrate to form the second well region and the substrate by using the third patterning layer as a mask. The first well region and the second well region are formed before the first fin portion and the second fin portion are formed, which can effectively avoid affecting the first fin portion and the second fin portion during implantation of the first ions and the second ions. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure;

[0032] Figures 4 to 13 is a structural schematic diagram of each step of an embodiment of the forming method of the semiconductor structure. DETAILED DESCRIPTION

[0033] As described in the background, the transistor of the silicon germanium material channel in the prior art still has many problems. The following will be specifically described with reference to the drawings.

[0034] Figures 1 to 3 is a schematic diagram of a semiconductor structure.

[0035] Referring to Figure 1 , a substrate 100 is provided, the substrate 100 comprises a first region I and a second region II which are adjacent to each other, and the substrate 100 has a first opening (not shown) therein, the first opening is located in the second region II; a semiconductor material layer 102 is formed in the first opening, the material of the semiconductor material layer 102 is different from the material of the substrate 100.

[0036] Referring to Figure 2 , the substrate 100 and the semiconductor material layer 102 are subjected to a patterning process to form a plurality of first fins 103 and a plurality of second fins 104, the first fins 103 are formed by patterning the substrate 100, and the second fins 104 are formed by patterning the semiconductor material layer 102.

[0037] Referring to Figure 3 , an initial isolation layer (not shown) is formed on the substrate 100, the initial isolation layer covers the sidewalls of the first fins 103 and the second fins 104; a first well region 105 is formed in the first region I, the first well region 105 has first ions therein; a second well region 106 is formed in the second region II, the second well region 106 has second ions therein, the first ions and the second ions are of different electrical types; after the first well region 105 and the second well region 106 are formed, the initial isolation layer is etched back to form an isolation layer 101, the isolation layer 101 covers part of the sidewalls of the first fins 103 and the second fins 104, and the top surface of the isolation layer 101 is lower than the top surfaces of the first fins 103 and the second fins 104.

[0038] In this embodiment, the material of the substrate 100 is silicon, and the material of the semiconductor material layer 102 is silicon germanium, the second fins 104 formed by patterning the semiconductor material layer 102 are used as the channel layers of subsequent PMOS transistors, which can effectively improve the mobility of holes and thus improve the device performance of the PMOS transistors.

[0039] However, in this embodiment, the gap between the first well region 105 and the second well region 106 formed after the patterning process is small, which makes it easy for the subsequently formed transistors to be short-circuited, thereby affecting the performance of the subsequent semiconductor structure.

[0040] On this basis, the application provides a semiconductor structure and a forming method thereof, a separation opening is formed between the first well region and the second well region, and an isolation layer is formed on the substrate and in the separation opening. Through the isolation layer in the separation opening, the first well region and the second well region can be effectively isolated, thereby reducing the short circuit problem between the subsequently formed transistors, so as to improve the performance of the finally formed semiconductor structure.

[0041] In order to make the above objectives, characteristics and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0042] Figures 4 to 13 is a structure schematic diagram of each step of an embodiment of the forming method of the semiconductor structure of the application.

[0043] Please refer to Figure 4 and Figure 5 , Figure 4 is a structure schematic diagram of each step of an embodiment of the forming method of the semiconductor structure of the application. Figure 5 , Figure 5 is a sectional view along line A-A in Figure 4 , a substrate 200 is provided, the substrate 200 has a first well region 201 and a second well region 202 adjacent to each other in the substrate 200, the first well region 201 has first ions, the second well region 202 has second ions, and the first ions and the second ions are of different electrical types.

[0044] In this embodiment, the forming method of the substrate 200 comprises the following steps: providing an initial substrate (not shown); forming a second patterned layer (not shown) on the initial substrate, the second patterned layer exposes part of the top surface of the initial substrate; taking the second patterned layer as a mask, injecting the first ions into the initial substrate to form the first well region 201; after forming the first well region 201, removing the second patterned layer; after removing the second patterned layer, forming a third patterned layer (not shown) on the initial substrate, the third patterned layer exposes part of the top surface of the initial substrate; taking the third patterned layer as a mask, injecting the second ions into the initial substrate to form the second well region 202 and the substrate 200.

[0045] In this embodiment, the material of the initial substrate is silicon; in other embodiments, the material of the initial substrate can also be silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0046] In this embodiment, the first ions are P-type ions, the first well region 201 is a P-well, the second ions are N-type ions, and the second well region 202 is an N-well.

[0047] In this embodiment, an NMOS transistor is formed on the P-well, and a PMOS transistor is formed on the N-well.

[0048] In this embodiment, the first well region 201 and the second well region 202 are formed before the first fin and the second fin are formed, which can effectively avoid affecting the first fin and the second fin during the process of implanting the first ions and the second ions.

[0049] In this embodiment, after the substrate 200 is provided, the method further includes forming an isolation opening, a plurality of first fins and a plurality of second fins, the first fins are located on the first well region 201, the second fins are located on the second well region 202, and the isolation opening is located between the first well region 201 and the second well region 202. For details, please refer to Figures 6 to 12 .

[0050] Please refer to the same view direction of Figure 6 , Figure 6 and Figure 5 , an initial first semiconductor material layer 203 is formed on the substrate 200.

[0051] In this embodiment, the initial first semiconductor material layer 203 is located on the first well region 201 and the second well region 202, respectively.

[0052] In this embodiment, the material of the initial first semiconductor material layer 203 is silicon.

[0053] Please refer to Figure 7 , part of the initial first semiconductor material layer 203 is removed to form the first semiconductor material layer 204 and an initial first opening 205, and the initial first opening 205 is located on the second well region 202.

[0054] In this embodiment, the initial first opening 205 provides space for the subsequent formation of a second semiconductor material layer.

[0055] In this embodiment, the forming method of the initial first opening 205 includes: forming a fourth patterned layer (not shown) on the initial first semiconductor material layer 203, the fourth patterned layer exposes part of the top surface of the initial first semiconductor material layer 203; and etching the initial first semiconductor material layer 203 with the fourth patterned layer as a mask to form the initial first opening 205.

[0056] Please refer to Figure 8 , a side wall 206 is formed on the side wall of the initial first opening 205, and a first opening 207 is formed.

[0057] In the embodiment, the first opening 207 is located on the second well region 202.

[0058] In the embodiment, the side wall 206 is used to form a patterned opening, and the isolation opening is formed by taking the patterned opening as a mask.

[0059] In the embodiment, the method for forming the side wall 206 on the sidewall of the initial first opening 205 includes: forming an initial side wall (not shown) on the sidewall and top surface of the initial first opening 205, and the top surface of the first semiconductor material layer 204; etching back the initial side wall until the top surface of the first semiconductor material layer 204 and the bottom surface of the initial first opening 205 are exposed, thereby forming the side wall 206.

[0060] In the embodiment, the material of the side wall 206 is different from the first semiconductor material 204; the material of the side wall 206 is different from the second semiconductor material formed subsequently. When the side wall 206 is removed subsequently, the etching damage to the first semiconductor material layer 204 and the second semiconductor material layer is reduced.

[0061] In the embodiment, the material of the side wall 206 includes silicon oxide; in other embodiments, the material of the side wall can also be silicon nitride, silicon carbide or silicon oxynitride.

[0062] Please refer to Figure 9 In the first opening 207, a second semiconductor material layer 208 is formed, and the material of the second semiconductor material layer 208 is different from that of the first semiconductor material layer 204.

[0063] In the embodiment, the material of the second semiconductor material layer 208 is silicon germanium, and the second semiconductor material layer 208 is used to form the second fin, which is used to form the channel layer of the PMOS transistor, thereby effectively improving the mobility of holes and improving the device performance of the PMOS transistor.

[0064] In the embodiment, the process for forming the second semiconductor material layer 208 in the first opening 207 adopts an epitaxial growth process. Since the sidewall of the first opening 207 is the side wall 206, when the epitaxial growth process is used to form the second semiconductor material layer 208, the second semiconductor material layer 208 can only grow from the bottom surface of the first opening 207, thereby avoiding the formation of voids in the second semiconductor material layer 208, and further ensuring that the second fin formed also does not have the voids, so as to improve the performance of the semiconductor structure finally formed.

[0065] Please refer to Figure 10A first patterning layer 209 is formed on the first semiconductor material layer 204 and the second semiconductor material layer 208, and exposes part of the top surface of the first semiconductor material layer 204 and part of the top surface of the second semiconductor material layer 208.

[0066] In this embodiment, the first semiconductor material layer 204 and the second semiconductor material layer 208 are etched by using the first patterning layer 209 as a mask, to form a plurality of first fins and a plurality of second fins.

[0067] Please refer to Figure 11 The side wall 206 is removed, and the patterning opening 210 is formed between the first semiconductor material layer 204 and the second semiconductor material layer 208.

[0068] In this embodiment, the side wall 206 is removed by using a wet etching process. The material of the side wall 206 is different from the material of the first semiconductor material layer 204 and the material of the second semiconductor material layer 208. Therefore, the self-aligned wet etching process can effectively reduce the process difficulty.

[0069] Please refer to Figure 12 The first semiconductor material layer 204, the second semiconductor material layer 208, the first well region 201 and the second well region 202 are etched by using the first patterning layer 209 and the patterning opening 210 as masks, to form the first fin 211, the second fin 212 and the isolation opening 213.

[0070] In this embodiment, the second fin 212 includes a first region I and a second region II on the first region I, and the material of the first region I is different from the material of the second region II.

[0071] In this embodiment, the material of the first region I is silicon, and the material of the second region II is silicon germanium.

[0072] In this embodiment, the material of the first fin 211 is silicon.

[0073] Please refer to Figure 13 An isolation layer 214 is formed on the substrate 200 and in the isolation opening 213, and covers part of the side wall of the first fin 211 and part of the side wall of the second fin 212. The top surface of the isolation layer 214 is lower than the top surface of the first fin 211 and the top surface of the second fin 212.

[0074] In the embodiment, the forming method of the isolation layer 214 includes: forming an isolation material layer (not shown) on the substrate 200 and in the isolation opening 213, the isolation material layer covering the first fin 211 and the second fin 212; performing a planarization process on the isolation material layer until the top surfaces of the first fin 211 and the second fin 212 are exposed, forming an initial isolation layer (not shown); and etching back the initial isolation layer to form the isolation layer 214.

[0075] In the embodiment, the material of the isolation layer 214 is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon oxide carbon or silicon oxide nitrogen.

[0076] In the embodiment, the isolation opening 213 is formed between the first well region 201 and the second well region 202, and the isolation layer 214 is formed on the substrate 200 and in the isolation opening 213. The isolation layer 214 in the isolation opening 213 can effectively isolate the first well region 201 and the second well region 202, thereby reducing the problem of short circuit between the subsequently formed transistors, so as to improve the performance of the finally formed semiconductor structure.

[0077] Correspondingly, the embodiment of the present application also provides a semiconductor structure, please continue to refer to Figure 13 , comprising: a substrate 200, the substrate 200 having a first well region 201 and a second well region 202 adjacent in the substrate 200, the first well region 201 having a first ion, the second well region 202 having a second ion, the first ion and the second ion being different in electrical type; a plurality of first fins 211 on the first well region 201; a plurality of second fins 212 on the second well region 202; an isolation opening 213 in the substrate 200, the isolation opening 213 being between the first well region 201 and the second well region 202; an isolation layer 214 on the substrate 200 and in the isolation opening 213, the isolation layer 214 covering part of the sidewalls of the first fin 211 and the second fin 212, and the top surface of the isolation layer 214 being lower than the top surfaces of the first fin 211 and the second fin 212.

[0078] The isolation layer 214 in the isolation opening 213 can effectively isolate the first well region 201 and the second well region 202, thereby reducing the problem of short circuit between the subsequently formed transistors, so as to improve the performance of the finally formed semiconductor structure.

[0079] In the embodiment, the second fin 212 comprises a first region I and a second region II on the first region I, and the materials of the first region I and the second region II are different.

[0080] In the embodiment, the material of the first region I is silicon, and the material of the second region II is silicon germanium.

[0081] In the embodiment, the material of the first fin 211 is silicon.

[0082] In the embodiment, the material of the isolation layer 214 is silicon oxide, and in other embodiments, the material of the isolation layer can also be silicon oxycarbide or silicon oxynitride.

[0083] In the embodiment, the first ion is a P-type ion, and the second ion is an N-type ion.

[0084] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application provides a substrate, which comprises a first well region and a second well region adjacent to each other, the first well region containing first ions, and the second well region containing second ions, the first ions and the second ions being different in electrical type. A first fin and a second fin are formed on the first well region and the second well region respectively, and an isolation opening is formed between the first well region and the second well region. An isolation layer is formed on the substrate and in the isolation opening, covering part of the sidewalls of the first fin and the second fin, and the top surface of the isolation layer is lower than the top surfaces of the first fin and the second fin. The method for forming the isolation opening, the first fin and the second fin comprises the following steps: forming a first semiconductor material layer and a second semiconductor material layer on the substrate; forming a first patterned layer on the first semiconductor material layer and the second semiconductor material layer, the first patterned layer exposing the top surfaces of part of the first semiconductor material layer and part of the second semiconductor material layer; forming a patterned opening between the first semiconductor material layer and the second semiconductor material layer; and etching the first semiconductor material layer, the second semiconductor material layer, the first well region and the second well region with the first patterned layer and the patterned opening as masks, to form the first fin, the second fin and the isolation opening. The method for forming the first semiconductor material layer, the second semiconductor material layer and the patterned opening comprises the following steps: forming an initial first semiconductor material layer on the substrate; removing part of the initial first semiconductor material layer to form the first semiconductor material layer and an initial first opening, the initial first opening being located on the second well region; forming a sidewall on the sidewall of the initial first opening to form a first opening; forming the second semiconductor material layer in the first opening, the second semiconductor material layer being different in material from the first semiconductor material layer; and removing the sidewall to form the patterned opening between the first semiconductor material layer and the second semiconductor material layer. The second fin comprises a first region and a second region located on the first region, and the materials of the first region and the second region are different.

2. The method of forming a semiconductor structure of claim 1, wherein The material of the first region comprises silicon, and the material of the second region comprises silicon germanium.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the first fin comprises silicon.

4. The method of forming a semiconductor structure of claim 1, wherein The process for forming the second semiconductor material layer in the first opening comprises an epitaxial growth process.

5. The method of forming a semiconductor structure of claim 1, wherein The method for forming the sidewall on the sidewall of the initial first opening comprises the following steps: forming an initial sidewall on the sidewall and the top surface of the initial first opening and the top surface of the first semiconductor material layer; and etching back the initial sidewall until the top surface of the first semiconductor material layer and the bottom surface of the initial first opening are exposed, to form the sidewall.

6. The method of forming a semiconductor structure of claim 1, wherein, The material of the sidewall is different from the material of the first semiconductor material, and the material of the sidewall is different from the material of the second semiconductor material.

7. The method of forming a semiconductor structure of claim 1, wherein The material of the sidewall comprises silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

8. The method of forming a semiconductor structure of claim 1, wherein, ​ 9. The method of forming a semiconductor structure of claim 1, wherein The forming method of the isolation layer comprises: forming an isolation material layer in the isolation opening and on the substrate, the isolation material layer covering the first fin and the second fin; performing a planarization treatment on the isolation material layer until the top surfaces of the first fin and the second fin are exposed, forming an initial isolation layer; etching back the initial isolation layer to form the isolation layer.

10. The method of forming a semiconductor structure of claim 1, wherein, The material of the isolation layer comprises silicon oxide, silicon oxide carbon or silicon oxide nitrogen.

11. The method of forming a semiconductor structure of claim 1, wherein The first ion comprises a P-type ion; and the second ion comprises an N-type ion.

12. The method of forming a semiconductor structure of claim 1, wherein, The forming method of the substrate comprises: providing an initial substrate; forming a second patterning layer on the initial substrate, the second patterning layer exposing part of the top surface of the initial substrate; taking the second patterning layer as a mask, implanting the first ion into the initial substrate to form the first well region; after forming the first well region, removing the second patterning layer; after removing the second patterning layer, forming a third patterning layer on the initial substrate, the third patterning layer exposing part of the top surface of the initial substrate; taking the third patterning layer as a mask, implanting the second ion into the initial substrate to form the second well region and the substrate.

13. A semiconductor structure formed by the method of any one of claims 1 to 12, wherein: The forming method of the substrate comprises: The substrate has adjacent first and second well regions, the first well region has a first ion, the second well region has a second ion, and the first and second ions have different electrical types; a plurality of first fins on the first well region; a plurality of second fins on the second well region; an isolation opening in the substrate, the isolation opening being between the first and second well regions; an isolation layer on the substrate and in the isolation opening, the isolation layer covering part of the sidewalls of the first and second fins, and the top surface of the isolation layer being lower than the top surfaces of the first and second fins.

14. The semiconductor structure of claim 13, wherein, The second fin comprises a first region and a second region on the first region, and the materials of the first and second regions are different.

15. The semiconductor structure of claim 14, wherein, The material of the first region comprises silicon; and the material of the second region comprises silicon germanium.

16. The semiconductor structure of claim 13, wherein, The material of the first fin comprises silicon.

17. The semiconductor structure of claim 13, wherein, The material of the isolation layer comprises silicon oxide, silicon oxide carbon or silicon oxide nitrogen.

18. The semiconductor structure of claim 13, wherein, The first ion comprises a P-type ion; and the second ion comprises an N-type ion.

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