Bidirectional vertical cavity surface emitting laser

Abstract

In some embodiments, a vertical cavity surface emitting laser device includes a substrate layer and a first set of epitaxial layers for a bottom-emitting VCSEL disposed on the substrate layer. The first set of epitaxial layers may include a first set of reflectors and at least one first active layer. The VCSEL device may include a second set of epitaxial layers for a top-emitting VCSEL, which is disposed on the first set of epitaxial layers for the bottom-emitting VCSEL. The second set of epitaxial layers may include a second set of reflectors and at least one second active layer. The top-emitting VCSEL and the bottom-emitting VCSEL may be configured to emit light in opposite light emission directions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 261,697, filed on September 27, 2021, entitled “Vertically Offset Single-Substrate Single-Chip Vertical Cavity Surface Emitting Laser.” This patent application also claims priority to U.S. Provisional Patent Application No. 63 / 261,699, filed on September 27, 2021, entitled “Bidirectional Vertical Cavity Surface Emitting Laser Chip.” Technical Field

[0003] The present disclosure relates generally to lasers and bidirectional vertical cavity surface emitting lasers (VCSELs). Background Art

[0004] Vertical emitting devices (such as vertical cavity surface emitting lasers) can include lasers, light emitters, etc., in which a light beam is emitted in a direction perpendicular to the substrate surface (e.g., perpendicularly from the surface of a semiconductor wafer). Multiple vertical emitting devices can be arranged in one or more emitter arrays (e.g., VCSEL arrays) on a common substrate. Summary of the Invention

[0005] In some embodiments, a vertical cavity surface emitting laser device includes a substrate layer and a first set of epitaxial layers for a bottom-emitting VCSEL disposed on the substrate layer, the first set of epitaxial layers including a first set of reflectors and at least one first active layer. The VCSEL device includes a second set of epitaxial layers for a top-emitting VCSEL disposed on the first set of epitaxial layers for a bottom-emitting VCSEL, the second set of epitaxial layers including a second set of reflectors and at least one second active layer. The top-emitting VCSEL and the bottom-emitting VCSEL are configured to emit light in opposite light emission directions.

[0006] In some embodiments, a module includes a housing including an aperture and a VCSEL device attached to the housing. The VCSEL device includes a substrate layer and a first set of epitaxial layers for a bottom-emitting VCSEL disposed on the substrate layer, the first set of epitaxial layers including a first set of reflectors and at least one first active layer. The VCSEL device includes a second set of epitaxial layers for a top-emitting VCSEL disposed on the first set of epitaxial layers for a bottom-emitting VCSEL, the second set of epitaxial layers including a second set of reflectors and at least one second active layer. The top-emitting VCSEL and the bottom-emitting VCSEL are configured to emit light in opposite light emission directions, and the first emission region of the bottom-emitting VCSEL or the second emission region of the top-emitting VCSEL is aligned with the aperture of the housing.

[0007] In some embodiments, a method includes growing a first set of epitaxial layers for a bottom-emitting VCSEL on a substrate, the first set of epitaxial layers including a first set of reflectors and at least one first active layer. The method also includes growing a second set of epitaxial layers for a top-emitting VCSEL on the first set of epitaxial layers, the second set of epitaxial layers including a second set of reflectors and at least one second active layer. The method also includes etching a portion of the second set of epitaxial layers until a surface of the first set of epitaxial layers is exposed. The top-emitting VCSEL and the bottom-emitting VCSEL are configured to emit light in opposite light emission directions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and 1B are diagrams depicting a top view of an example emitter and a cross-sectional view of the example emitter along line XX, respectively.

[0009] Figure 2 is a diagram of an example vertical cavity surface emitting laser device.

[0010] Figure 3 is a diagram of an example VCSEL device.

[0011] Figure 4 is a diagram of an example VCSEL array.

[0012] Figure 5 is a diagram of an example VCSEL device.

[0013] Figure 6 is a flow chart of an exemplary process for forming a bidirectional VCSEL as described herein. DETAILED DESCRIPTION

[0014] The following detailed embodiments of the exemplary embodiments refer to the accompanying drawings, in which the same reference numerals in different drawings may identify the same or similar elements.

[0015] Vertical cavity surface emitting lasers (VCSELs) and edge emitting lasers (EELs) emit light in different directions, which can be particularly relevant in applications requiring a small form factor. VCSELs emit vertically, in a direction perpendicular to the wafer surface. Therefore, the thickness of the VCSEL can be determined by the number of VCSEL layers grown and the amount of thinning of the VCSEL substrate during manufacturing. EELs emit from the edge of the device, parallel to the wafer surface. In addition, VCSELs can be interfaced with external optics placed directly above the VCSEL surface. If the emission is in the same direction as the wafer surface, the EEL requires additional optics to change the direction of the emitted light by 90 degrees.

[0016] In addition, VCSELs can emit light from the top of the chip in the growth direction of the VCSEL (e.g., top-emitting VCSELs) or emit light downward through the substrate through the back of the VCSEL (e.g., bottom-emitting VCSELs). Each type of VCSEL can utilize a different epitaxial design and a different manufacturing process. Top-emitting VCSELs can be easier to manufacture than bottom-emitting VCSELs, but top-emitting VCSELs may need to be used in combination with external optical components. Bottom-emitting VCSELs can integrate optical components onto the back of the substrate of the bottom-emitting VCSEL to reduce complexity, but the manufacturing process of bottom-emitting VCSELs may be more complex than that of top-emitting VCSELs. Top-emitting VCSELs and / or bottom-emitting VCSELs can be used in applications related to dot projectors, indirect time-of-flight (ITOF), direct time-of-flight (DTOF), and / or light detection and ranging (LDR).

[0017] In some cases, multiple VCSEL chips can be integrated into a device such as a smartphone. For example, a first VCSEL chip integrated into the device can be configured to face the user (e.g., emitting light in the emission direction of the device's display), which can be referred to as "front-facing." Continuing with this example, a second VCSEL chip integrated into the device can be configured to face the world (e.g., emitting light opposite to the emission direction of the device's display), which can be referred to as "world-facing." Typically, both VCSEL chips used in this configuration can be top-emitting. Furthermore, each VCSEL chip can be integrated into a separate module, thereby increasing the overall device size and thickness.

[0018] Some embodiments described herein provide VCSEL devices that emit light in opposite directions (e.g., bidirectionally). In some embodiments, different types of VCSELs (e.g., top-emitting and bottom-emitting) can be integrated on a single chip. For example, a top-emitting VCSEL and a bottom-emitting VCSEL (e.g., separate VCSELs with different active layers and reflectors) can be integrated into the same chip in a configuration that provides emission in opposite directions. In some embodiments, a first set of epitaxial layers for one or more bottom-emitting VCSELs can be disposed on a substrate layer (e.g., a wafer), and a second set of epitaxial layers for one or more top-emitting VCSELs can be disposed on the first set of epitaxial layers. For example, multiple complete VCSEL epitaxial stacks can be grown on the same substrate layer, and the lower VCSEL stacks can be exposed during manufacturing to produce multiple VCSELs that emit light in opposite light emission directions.

[0019] In this way, a single VCSEL module can include both top-emitting and bottom-emitting VCSELs with a reduced form factor. Furthermore, the VCSELs (e.g., which can be independently controlled) enable bidirectional emission of light to facilitate both forward-facing and world-facing operation. Thus, forward-facing and world-facing operation can be achieved without the need for separate VCSEL chips and modules, thereby reducing complexity, thickness, and overall form factor.

[0020] Figure 1A and Figure 1B 1 and 2 are diagrams respectively depicting a top view of an example transmitter 100 and a cross-sectional view 150 of the example transmitter 100 along line XX. Figure 1A As shown, the transmitter 100 may include a set of transmitter layers constructed in a transmitter architecture. In some embodiments, the transmitter 100 may correspond to one or more vertical transmitters described herein.

[0021] like Figure 1A As shown, the emitter 100 can include an implant protection layer 102 that is circular in shape in this example. In some implementations, the implant protection layer 102 can have another shape, such as an elliptical shape, a polygonal shape, etc. The implant protection layer 102 is defined based on the spaces between portions of the implant material (not shown) included in the emitter 100.

[0022] like Figure 1A As shown in the medium gray and dark gray areas in the figure, the emitter 100 includes an ohmic metal layer 104 (e.g., a p-ohmic metal layer or an n-ohmic metal layer) that is configured as a partial ring (e.g., having an inner radius and an outer radius). The medium gray area shows the area of ​​the ohmic metal layer 104 that is covered by a protective layer (e.g., a dielectric layer or a passivation layer) of the emitter 100, and the dark gray area shows the area of ​​the ohmic metal layer 104 that is exposed via a through hole 106, as described below. As shown, the ohmic metal layer 104 overlaps the implant protection layer 102. For example, in the case of a p-top / top-emitting emitter 100, this configuration can be used. In the case of a bottom-emitting emitter 100, the configuration can be adjusted as needed.

[0023] exist Figure 1A106 ). The emitter 100 includes a protective layer in which a via 106 is formed (e.g., etched). The dark gray area shows the area of ​​the ohmic metal layer 104 that is exposed by the via 106 (e.g., the shape of the dark gray area can be a result of the shape of the via 106), while the medium gray area shows the area of ​​the ohmic metal layer 104 that is covered by some of the protective layer. The protective layer can cover all of the emitter except for the via. As shown, the via 106 is formed as a partial ring (e.g., similar to the ohmic metal layer 104) and is formed above the ohmic metal layer 104 so that the metallization on the protective layer contacts the ohmic metal layer 104. In some embodiments, the via 106 and / or the ohmic metal layer 104 can be formed in another shape, such as a full ring or an open ring.

[0024] As further shown, the emitter 100 includes an optical aperture 108 in a portion of the emitter 100 within the inner radius of the partial annular shape of the ohmic metal layer 104. The emitter 100 emits the laser beam via the optical aperture 108. As further shown, the emitter 100 also includes a current limiting aperture 110 (e.g., an oxide aperture (not shown) formed by an oxide layer of the emitter 100). The current limiting aperture 110 is formed below the optical aperture 108.

[0025] like Figure 1A As further shown in FIG, emitter 100 includes a set of trenches 112 (e.g., oxide trenches) spaced (e.g., equally, unequally) around the circumference of implant protection layer 102. How closely the trenches 112 can be positioned relative to optical aperture 108 depends on the application and is generally limited by the implant protection layer 102, ohmic metal layer 104, via 106, and manufacturing tolerances.

[0026] Figure 1A The number and arrangement of layers shown in FIG are provided as examples. In practice, the transmitter 100 may include Figure 1A 112 , different layers, or differently arranged layers than the layers shown in . For example, while emitter 100 includes a set of six grooves 112 , in practice, other configurations are possible, such as a compact emitter including five grooves 112 , seven grooves 112 , or another number of grooves. In some embodiments, the grooves 112 can surround emitter 100 to form a mesa structure associated with the distance dt . As another example, while emitter 100 is a circular emitter design, in practice, other designs can be used, such as rectangular emitters, hexagonal emitters, elliptical emitters, etc. Additionally or alternatively, a set of layers (e.g., one or more layers) of emitter 100 can each perform one or more functions described as being performed by another set of layers of emitter 100 .

[0027] It is worth noting that while the design of emitter 100 is described as including a VCSEL, other implementations are possible. For example, the design of emitter 100 can be applied in the context of another type of optical device (such as a light emitting diode) or another type of vertical emitting (e.g., top-emitting or bottom-emitting) optical device. In addition, the design of emitter 100 can be applied to emitters of any wavelength, power level, and / or emission profile. In other words, emitter 100 is not specific to an emitter having given performance characteristics.

[0028] like Figure 1B As shown, the example cross-sectional view may represent a cross-section of the emitter 100 passing through or between a pair of grooves 112 (e.g., as shown in FIG. Figure 1A ). As shown, emitter 100 may include a backside cathode layer 128, a substrate layer 126, a bottom reflector 124, an active region 122, an oxide layer 120, a top reflector 118, an implanted isolation material 116, a protective layer 114 (e.g., a dielectric passivation / mirror layer), and an ohmic metal layer 104. As shown, emitter 100 may have an overall height of, for example, approximately 10 micrometers (μm).

[0029] The backside cathode layer 128 may include a layer in electrical contact with the substrate layer 126. For example, the backside cathode layer 128 may include an annealed metallization layer, such as an AuGeNi layer, a PdGeAu layer, or the like.

[0030] The substrate layer 126 may include a base substrate layer on which an epitaxial layer is grown. For example, the substrate layer 126 may include a semiconductor layer such as a GaAs layer, an InP layer, and / or another type of semiconductor layer.

[0031] The bottom reflector 124 may include a bottom reflector layer of the emitter 100. For example, the bottom reflector 124 may include a distributed Bragg reflector (DBR).

[0032] Active region 122 may include a layer that confines electrons and defines the emission wavelength of emitter 100. For example, active region 122 may be a quantum well.

[0033] Oxide layer 120 may include an oxide layer that provides optical and electrical confinement for emitter 100. In some embodiments, oxide layer 120 may be formed by wet oxidation of an epitaxial layer. For example, oxide layer 120 may be an Al2O3 layer formed by oxidation of an AlAs or AlGaAs layer. Trench 112 may include an opening that allows oxygen (e.g., dry oxygen, wet oxygen) to enter the epitaxial layer forming oxide layer 120.

[0034] The current limiting aperture 110 may include an optically active aperture defined by an oxide layer 120. The size of the current limiting aperture 110 may be, for example, in the range of about 4 μm to about 20 μm. In some embodiments, the size of the current limiting aperture 110 may depend on the distance between the trenches 112 surrounding the emitter 100. For example, the trenches 112 may be etched to expose the epitaxial layer forming the oxide layer 120. Here, oxidation of the epitaxial layer may occur a certain distance (e.g., within 100°) toward the center of the emitter 100 before forming (e.g., depositing) the protective layer 114. Figure 1B 1 ), thereby forming an oxide layer 120 and a current confining aperture 110. In some embodiments, the current confining aperture 110 may include an oxide aperture. Additionally or alternatively, the current confining aperture 110 may include an aperture associated with another type of current confinement technology, such as an etched mesa, an area without ion implantation, a lithographically defined intracavity mesa, and regrowth.

[0035] The top reflector 118 may comprise a top reflector layer of the emitter 100. For example, the top reflector 118 may comprise a DBR.

[0036] The implant isolation material 116 may include a material that provides electrical isolation. For example, the implant isolation material 116 may include an ion implant material, such as a hydrogen / proton implant material or similar implant elements, to reduce electrical conductivity. In some implementations, the implant isolation material 116 may define the implant protection layer 102.

[0037] The protective layer 114 may include a layer that acts as a protective passivation layer and may act as an additional DBR. For example, the protective layer 114 may include one or more sublayers (e.g., a dielectric passivation layer and / or a reflector layer, a SiO2 layer, a Si3N4 layer, an Al2O3 layer, or other layers) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of the emitter 100.

[0038] As shown, the protective layer 114 may include one or more vias 106 that provide electrical access to the ohmic metal layer 104. For example, the vias 106 may be formed as an etched portion of the protective layer 114 or a stripped portion of the protective layer 114. The optical aperture 108 may include a portion of the protective layer 114 above the current confining aperture 110 through which light may be emitted.

[0039] The ohmic metal layer 104 may include a layer that makes electrical contact through which current can flow. For example, the ohmic metal layer 104 may include a Ti and Au layer, a Ti and Pt layer, and / or an Au layer, etc., through which current can flow (e.g., through a pad (not shown) that contacts the ohmic metal layer 104 through the via 106). The ohmic metal layer 104 may be P-ohm, N-ohm, or other forms known in the art. The selection of the specific type of ohmic metal layer 104 may depend on the architecture of the emitter and is within the knowledge of those skilled in the art. The ohmic metal layer 104 may provide an ohmic contact between the metal and the semiconductor and / or may provide a non-rectifying electrical junction and / or may provide a low resistance contact. In some embodiments, the emitter 100 may be manufactured using a series of steps. For example, the bottom reflector 124, the active area 122, the oxide layer 120, and the top reflector 118 may be epitaxially grown on the substrate layer 126, after which the ohmic metal layer 104 may be deposited on the top reflector 118. Next, trenches 112 may be etched to expose oxide layer 120 for oxidation. Implant isolation material 116 may be created via ion implantation, after which protective layer 114 may be deposited. Vias 106 may be etched into protective layer 114 (e.g., to expose ohmic metal layer 104 for contact). Electroplating, seeding, and etching may be performed, after which substrate layer 126 may be thinned and / or ground to a target thickness. Finally, a backside cathode layer 128 may be deposited on the bottom side of substrate layer 126.

[0040] Figure 1B The number, arrangement, thickness, order, symmetry, etc. of layers shown in FIG are provided as examples. In practice, the transmitter 100 may include Figure 1B 100 may include additional layers, fewer layers, different layers, differently constructed layers, or differently arranged layers than those shown in FIG. Additionally or alternatively, a set of layers (e.g., one or more layers) of transmitter 100 may perform one or more functions described as being performed by another set of layers of transmitter 100, and any layer may include more than one layer.

[0041] Figure 2 is a diagram of an example VCSEL device 200. Figure 2As shown, the VCSEL device 200 may include a substrate layer 202, similar to that described above. Additionally, the VCSEL device 200 may include a first set of epitaxial layers 204 for a bottom-emitting VCSEL 206 (e.g., one or more bottom-emitting VCSELs 206, such as a plurality of bottom-emitting VCSELs 206) disposed on the substrate layer 202, and the VCSEL device 200 may include a second set of epitaxial layers 208 for a top-emitting VCSEL 210 (e.g., one or more top-emitting VCSELs 210, such as a plurality of top-emitting VCSELs 210) disposed on the first set of epitaxial layers 204. The first set of epitaxial layers 204 and the second set of epitaxial layers may be independent, so that the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 may be (e.g., electrically and optically) independent. The first set of epitaxial layers 204 and / or the second set of epitaxial layers 208 may correspond to a combination of Figures 1A-1B Describes the emitter layer.

[0042] The VCSEL device 200 may include a bulk material layer 212 between the first set of epitaxial layers 204 and the second set of epitaxial layers 208. For example, the bulk material layer 212 may include a bulk semiconductor layer (e.g., GaAs) that may be lattice-matched to the substrate layer 202 (e.g., the GaAs bulk semiconductor layer may be lattice-matched to the GaAs substrate layer 202). In some embodiments, the VCSEL device 200 may include an electrical isolation layer 214 (e.g., a semiconductor layer) between the first set of epitaxial layers 204 and the second set of epitaxial layers 208 (e.g., between the bulk material layer 212 and the first set of epitaxial layers 204). The electrical isolation layer 214 may include a material that provides electrical isolation. In some embodiments, the VCSEL device 200 may include a contact layer 216 (e.g., a semiconductor layer) between the first set of epitaxial layers 204 and the second set of epitaxial layers 208 (e.g., between the bulk material layer 212 and the first set of epitaxial layers 204). The contact layer 216 may include a highly doped semiconductor material (e.g., an n++ material or a p++ material). A contact layer 216 can be disposed on the electrically isolating layer 214. In some embodiments, the VCSEL device 200 can include a tunnel junction 218 between one or more active layers of the first set of epitaxial layers 204 and the second set of epitaxial layers 208, as described below (e.g., within the body material layer 212, within the bottom reflector of the second set of epitaxial layers 208, etc., outside the active regions of the top-emitting VCSEL 210 and the bottom-emitting VCSEL 206).

[0043] The tunnel junction 218 can flip the carrier type (e.g., from electrons (n-type) to holes (p-type)) between the first set of epitaxial layers 204 and the second set of epitaxial layers 208. In this way, both the first set of epitaxial layers 204 and the second set of epitaxial layers 208 can utilize a pin structure and electrical drive scheme (i.e., simplifying the fabrication of the VCSEL device 200). However, the first set of epitaxial layers 204 and the second set of epitaxial layers 208 are not limited to any particular structure. For example, the first set of epitaxial layers 204 and the second set of epitaxial layers 208 can include the same structure or different structures, which can be any combination of pin, nip, npin, etc.

[0044] The first set of epitaxial layers 204 may include a first set of reflectors, shown as first reflector 220a and second reflector 220b. The first set of epitaxial layers 204 may include at least one first active layer 222 (e.g., a gain region) between the first reflector 220a and second reflector 220b. The second set of epitaxial layers 208 may include a second set of reflectors, shown as third reflector 224a and fourth reflector 224b. The second set of epitaxial layers 208 may include at least one second active layer 226 (e.g., a gain region) between the third reflector 224a and fourth reflector 224b. The active layer may include an active region where electrons and holes recombine to emit light. For example, the active region may include one or more quantum wells. The active layer may be located at a semiconductor junction of the set of epitaxial layers. A semiconductor junction may be a region where oppositely doped semiconductor materials meet. For example, the first active layer and the second active layer of the set of epitaxial layers may be located at a first pn junction and a second pn junction, respectively. The bottom-emitting VCSEL 206 and / or the top-emitting VCSEL 210 may include two or more semiconductor junctions / active layers (e.g., the bottom-emitting VCSEL 206 and / or the top-emitting VCSEL 210 may be a multi-junction VCSEL). Here, a tunnel junction may be between consecutive active layers. In some embodiments, the first set of reflectors and the second set of reflectors may be configured to prevent optical crosstalk between the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210.

[0045] In some embodiments, the first group of mirrors may include a first mirror 220A (e.g., a bottom mirror) and a second mirror 220B (e.g., a top mirror), and the second group of mirrors may include a third mirror 224A (e.g., a bottom mirror) and a fourth mirror 224B (e.g., a top mirror). In some embodiments, the first group of mirrors may include a first mirror (e.g., first mirror 220a) and a second mirror (e.g., a combination of second mirror 220b and third mirror 224a), and the second group of mirrors may include a second mirror and a third mirror (e.g., fourth mirror 224b). For example, the bulk material layer 212 may be omitted, and the top mirror (or one or more layers thereof) of the first group of epitaxial layers 204 may be combined with the bottom mirror (or one or more layers thereof) of the second group of epitaxial layers 208 to form a shared mirror for the first group of epitaxial layers 204 and the second group of epitaxial layers 208. The shared mirror can have increased reflectivity, thereby reducing optical leakage between the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210. Furthermore, the use of a shared mirror can reduce the time and complexity of manufacturing the VCSEL device 200. As described herein, the first mirror 220A, the second mirror 220B, the third mirror 224A, or the fourth mirror 224B can be a DBR.

[0046] In some embodiments, the first bottom reflector in the first group of reflectors (e.g., first reflector 220a) and the second bottom reflector in the second group of reflectors (e.g., third reflector 224a) can be one of n-type or p-type, and the first top reflector in the first group of reflectors (e.g., second reflector 220b) and the second top reflector in the second group of reflectors (e.g., fourth reflector 224b) can be the other of n-type or p-type. For example, the first and second bottom reflectors can be n-type, and the first and second top reflectors can be p-type. As described above, the VCSEL device 200 can include a tunnel junction 218 between the first and second epitaxial layers 204 and 208. Thus, the first and second epitaxial layers 204 and 208 can both utilize the same pin structure, the same nip structure, etc. In some embodiments, the first and second epitaxial layers 204 and 208 can utilize different structures, and the tunnel junction 218 can be omitted.

[0047] The at least one first active layer 222 may include one or more active layers, and the at least one second active layer 226 may include one or more active layers. In some embodiments, the first number of active layers of the first active layer 222 is the same as the second number of active layers of the second active layer 226, as shown. In some implementations, the first number of active layers of the first active layer 222 is different from the second number of active layers of the second active layer 226. In this manner, the optical power of the bottom-emitting VCSEL 206 can be the same as or different from the optical power of the top-emitting VCSEL 210. In implementations where the first active layer 222 or the second active layer 226 includes multiple active layers (e.g., two active layers), the first set of epitaxial layers 204 or the second set of epitaxial layers 208, respectively, can include tunnel junctions (not shown) between the multiple active layers.

[0048] In an example, the bottom-emitting VCSEL 206 (or the top-emitting VCSEL 210) can have two active layers 222 (e.g., for higher slope efficiency) and can be suitable for applications using higher power or longer distance light emission, while the top-emitting VCSEL 210 (or the bottom-emitting VCSEL) can have a single active layer 226 (e.g., for lower slope efficiency and / or for lower driver voltage and / or current operation) and can be suitable for applications using lower power or shorter distance light emission. Thus, the VCSEL device 200 can be used for multi-power applications, such as indoor / outdoor applications, short-range / long-range applications, etc. For example, if the world-facing application uses higher optical power, the world-facing VCSEL can include three active layers or five active layers, while the front-facing VCSEL can include a single active layer (e.g., because front-facing applications generally use lower optical power).

[0049] In some embodiments, the bottom-emitting VCSEL 206 (e.g., the lower VCSEL) can have a greater number of active layers than the top-emitting VCSEL 210 (e.g., the upper VCSEL). Alternatively, the top-emitting VCSEL 210 can have a greater number of active layers than the bottom-emitting VCSEL 206. The VCSEL with the greatest number of active layers (e.g., and therefore the greatest heat load) can be positioned closest to the substrate layer 202, and therefore closest to the heat sink (not shown). The number of active layers that can be utilized in the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 is not limited to one or two active layers. For example, the bottom-emitting VCSEL 206 and / or the top-emitting VCSEL 210 can include three active layers, four active layers, five active layers, and / or six active layers, etc. Furthermore, any combination of numbers of active layers may be used for the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 (eg, because the first set of epitaxial layers 204 is independent of the second set of epitaxial layers 208).

[0050] The bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 can be configured with an emission wavelength of 850 nanometers (nm), 905 nm, 940 nm, or greater than 1300 nm. In some embodiments, the emission wavelength of the bottom-emitting VCSEL 206 can be the same as the emission wavelength of the top-emitting VCSEL 210. In some embodiments, the emission wavelength of the bottom-emitting VCSEL 206 can be different from the emission wavelength of the top-emitting VCSEL 210. Here, the VCSEL device 200 can be used for multi-wavelength applications. For example, the VCSEL device 200 can provide shorter wavelength emission (e.g., 940 nm) and longer wavelength emission (e.g., greater than 1300 nm). In this way, the VCSEL device 200 can be used (e.g., simultaneously) for completely different applications.

[0051] The VCSEL device 200 can include a first set of electrical contacts electrically connected to the first set of epitaxial layers 204. The first set of electrical contacts can include a bottom contact 228a (e.g., a cathode contact) and a top contact 228b (e.g., an anode contact). The bottom contact 228a can be disposed on a surface of the substrate layer 202 opposite the first set of epitaxial layers 204. The top contact 228b can be formed in one or more trenches extending from the surface of the first set of epitaxial layers 204 to the first mirror 220a. Figure 2 The configuration of the first set of electrical contacts shown and described herein is provided as an example, and other configurations are possible.

[0052] The VCSEL device 200 may include a second set of electrical contacts electrically connected to the second set of epitaxial layers 208. The second set of electrical contacts may include a bottom contact 230a (e.g., a cathode contact) and a top contact 230b (e.g., an anode contact). The bottom contact 230a may be disposed on the first set of epitaxial layers 204. For example, the bottom contact 230a may be disposed on the contact layer 216 or the electrical isolation layer 214. The top contact 230b may be disposed on the surface of the second set of epitaxial layers 208 (e.g., on the fourth mirror 224b), or may be formed in one or more trenches extending from the surface of the second set of epitaxial layers 208 to the third mirror 224a. Figure 2 The configuration of the second set of electrical contacts shown and described herein is provided as an example, and other configurations are possible.

[0053] The first set of electrical contacts and the second set of electrical contacts can be independent or connected together (e.g., depending on the drive scheme employed for VCSEL device 200). That is, bottom-emitting VCSEL 206 and top-emitting VCSEL 210 can be operated simultaneously or independently (e.g., based on the drive scheme employed and / or based on the manner in which the VCSELs are manufactured). For example, each VCSEL can be independently controlled by a separate set of contact layers deposited during the manufacture of VCSEL device 200.

[0054] In some embodiments, the first set of epitaxial layers 204 may include an oxide layer 232 (e.g., between the first active layer 222 and the second reflector 220 b), the oxide layer 232 including oxide holes, and the second set of epitaxial layers 208 may include an oxide layer 234 (e.g., between the second active layer 226 and the fourth reflector 224 b), the oxide layer 234 including oxide holes, similar to those described above. In some embodiments, an electrical isolation layer 236 may be disposed along a surface of the first set of epitaxial layers 204 (e.g., lining one or more trenches for the top contact 230 b), and an electrical isolation layer 238 may be disposed along a surface of the second set of epitaxial layers 208 (e.g., lining one or more trenches for the top contact 232 b, if present). The electrical isolation layers 236, 238 may include electrically isolated removed portions (illustrated by dashed ellipses) to facilitate electrical connection of the top contacts 228 b, 230 b to the first and second sets of epitaxial layers 204, 208, respectively.

[0055] In some embodiments, the surface of substrate layer 202 opposite first set of epitaxial layers 204 may include an optical element 240 (e.g., a lens). That is, optical element 240 may be integrated into substrate layer 202. Here, substrate layer 202 may have a thickness greater than or equal to 50 μm (e.g., based on the configuration of optical element 240). As shown, optical element 240 may be used for bottom-emitting VCSEL 206 (e.g., light emission from bottom-emitting VCSEL 206 may be directed to optical element 240).

[0056] The bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 can be configured to emit light in opposite light emission directions 242a, 242b (e.g., with the light emission direction 242a rotated 180 degrees relative to the light emission direction 242b). For example, as described herein, the bottom-emitting VCSEL 206 can be configured for bottom emission (e.g., through the substrate layer 202), and the top-emitting VCSEL 210 can be configured for top emission (e.g., away from the substrate layer 202). Furthermore, the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 can be offset (e.g., vertically offset) in opposite light emission directions 242a, 242b. For example, the second set of epitaxial layers 208 for the top-emitting VCSEL 210 can be stacked on the first set of epitaxial layers 204 for the bottom-emitting VCSEL 206.

[0057] In some embodiments, the emission area of ​​the bottom emitting VCSEL 206 and the emission area of ​​the top emitting VCSEL 210 are aligned in a direction orthogonal to the opposite light emission directions 242a, 242b, such as Figure 2 In some embodiments, the emission area of ​​the bottom-emitting VCSEL 206 and the emission area of ​​the top-emitting VCSEL 210 are offset in a direction orthogonal to the opposite light emission directions 242a, 242b, as described below. That is, the emission area of ​​the bottom-emitting VCSEL 206 and the emission area of ​​the top-emitting VCSEL 210 can be horizontally offset.

[0058] In the VCSEL device 200, the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 are optically independent. In other words, there can be complete optical separation between the optical cavity of the bottom-emitting VCSEL 206 and the optical cavity of the top-emitting VCSEL 210, because optical leakage between the bottom-emitting VCSEL 206 and the top-emitting VCSEL 210 can affect the performance of the top-emitting VCSEL 210 (e.g., a VCSEL stacked on top of another VCSEL).

[0059] The VCSEL device 200 can be implemented as a single chip including bidirectional VCSELs 206 and 210. That is, the bidirectional VCSELs 206 and 210 can share a single common substrate layer 202 (e.g., a single common wafer). Thus, the VCSEL device 200 provides integration of a front-facing VCSEL and a world-facing VCSEL in a single chip, wherein the front-facing VCSEL and the world-facing VCSEL can have different optical powers (e.g., different numbers of active layers) and / or different emission wavelengths.

[0060] As mentioned above, Figure 2 are provided as examples. Other examples can be found in the Figure 2 The examples described are different.

[0061] Figure 3 is a diagram of an example VCSEL device 300. The VCSEL device 300 may include a substrate layer 302, similar to that described above. Additionally, the VCSEL device 300 may include a first set of epitaxial layers 304 for a bottom-emitting VCSEL 306 (e.g., one or more bottom-emitting VCSELs 306, such as a plurality of bottom-emitting VCSELs 306) disposed on the substrate layer 302, and the VCSEL device 300 may include a second set of epitaxial layers 308 for a top-emitting VCSEL 310 (e.g., one or more top-emitting VCSELs 310, such as a plurality of top-emitting VCSELs 310) disposed on the first set of epitaxial layers 304. The VCSEL device 300, including the first set of epitaxial layers 304 and the second set of epitaxial layers 308, may be configured in a manner similar to that described in conjunction with the VCSEL device 200. The bottom-emitting VCSEL 306 and the top-emitting VCSEL 310 may be configured to emit light in opposite light emission directions 342a, 342b, similar to that described above.

[0062] like Figure 3 As shown, the emission areas of the bottom emitting VCSEL 306 and the emission areas of the top emitting VCSEL 310 can be offset in a direction orthogonal to the opposite light emission directions 342a, 342b (e.g., the emission areas of the bottom emitting VCSEL 306 and the emission areas of the top emitting VCSEL 310 can be offset horizontally), as described herein. The horizontal offset can be used to meet module constraints or to produce a specific VCSEL array pattern (e.g., in combination with Figure 4For example, a VCSEL for a forward-facing application may require a dot projector with a random emitter layout, while a VCSEL for a world-facing application (i.e., based on ITOF) may require a uniform emitter array. The horizontal offset of the bottom-emitting VCSEL 306 and the top-emitting VCSEL 310 may also simplify the manufacturing of the VCSEL device 300.

[0063] As mentioned above, Figure 3 are provided as examples. Other examples can be found in the Figure 3 The examples described are different.

[0064] Figure 4 is a diagram of example VCSEL arrays 400, 410, and 420. VCSEL arrays 400, 410, and 420 may include VCSEL device 300 or another VCSEL device described herein. For example, VCSEL arrays 400, 410, and 420 may include a first set of epitaxial layers 304 for a plurality of bottom-emitting VCSELs 306 and a second set of epitaxial layers 308 for a plurality of top-emitting VCSELs 310. As shown, VCSEL arrays 400, 410, and 420 may be arranged into various patterns for a plurality of bottom-emitting VCSELs 306 and a plurality of top-emitting VCSELs 310 (some of which cannot be implemented using a single VCSEL chip). Figure 4 The patterns shown in are provided as examples, and in some embodiments, the VCSEL array may utilize Figure 4 The patterns shown in the different patterns.

[0065] In VCSEL array 400, multiple bottom-emitting VCSELs 306 and multiple top-emitting VCSELs 310 can be separated into different parts of the chip (e.g., left and right parts, top and bottom parts, etc.). For example, multiple bottom-emitting VCSELs 306 can be positioned on a first side of a line that divides VCSEL array 400 (e.g., into equal parts or into unequal parts), and multiple top-emitting VCSELs 310 can be positioned on a second side of the line in a direction orthogonal to opposite light emission directions 342a, 342b. The line can indicate the starting location of etching of the second set of epitaxial layers 308 that exposes the surface of the first set of epitaxial layers 304.

[0066] In VCSEL arrays 410 and 420, a plurality of bottom-emitting VCSELs 306 and a plurality of top-emitting VCSELs 310 are intermixed. For example, the plurality of bottom-emitting VCSELs 306 can be arranged in a first pattern, and the plurality of top-emitting VCSELs 310 can be arranged in a second pattern. In VCSEL array 410, the plurality of bottom-emitting VCSELs 306 can be interleaved with the plurality of top-emitting VCSELs 310 in a uniform pattern (e.g., each row and column of VCSEL array 410 alternates between a plurality of bottom-emitting VCSELs 306 and a plurality of top-emitting VCSELs 310). However, in some embodiments, the plurality of bottom-emitting VCSELs 306 and the plurality of top-emitting VCSELs 310 are interleaved in a random or quasi-random pattern. In other words, the first pattern of the plurality of bottom-emitting VCSELs 306 and the second pattern of the plurality of top-emitting VCSELs 310 are interleaved in a direction orthogonal to the opposing light emission directions 242a, 242b. In VCSEL array 410, etching of second set of epitaxial layers 308 may expose (e.g., surround) individual VCSELs in first set of epitaxial layers 304. In some embodiments, etching of second set of epitaxial layers 308 may expose multiple VCSELs in first set of epitaxial layers 304 (e.g., etching exposes specific portions of the surface of first set of epitaxial layers 304).

[0067] In the VCSEL array 420, a plurality of bottom-emitting VCSELs 306 surround (e.g., centrally, as shown, or offset from the center) a plurality of top-emitting VCSELs 310. In other words, a first pattern of the plurality of bottom-emitting VCSELs 306 surrounds a second pattern of the plurality of top-emitting VCSELs 310 in a direction orthogonal to the opposite light emission directions 342a, 342b. Here, etching of the second set of epitaxial layers 308 can expose the plurality of bottom-emitting VCSELs 306 in the first set of epitaxial layers 304. In some embodiments, the plurality of bottom-emitting VCSELs 306 can surround multiple groups of the plurality of top-emitting VCSELs 310. In some embodiments, the plurality of top-emitting VCSELs 310 can surround the plurality of bottom-emitting VCSELs 306 in a similar manner.

[0068] In this manner, a single optical component (eg, including VCSEL array 400, 410, or 420) can provide both forward-facing and world-facing light emissions with reduced module size and module complexity.

[0069] As mentioned above, Figure 4 are provided as examples. Other examples can be found in the Figure 4 The examples described are different.

[0070] Figure 5 is a diagram of an example module 500. Figure 5 As shown, the module may include a VCSEL device 501. The VCSEL device 501 may include a substrate layer 502, similar to that described above. Additionally, the VCSEL device 501 may include a first set of epitaxial layers 504 for a bottom-emitting VCSEL 506 (e.g., one or more bottom-emitting VCSELs 506, such as a plurality of bottom-emitting VCSELs 506) disposed on the substrate layer 502, and the VCSEL device 501 may include a second set of epitaxial layers 508 for a top-emitting VCSEL 510 (e.g., one or more top-emitting VCSELs 510, such as a plurality of top-emitting VCSELs 510) disposed on the first set of epitaxial layers 504. The VCSEL device 501, including the first set of epitaxial layers 504 and the second set of epitaxial layers 508, may be configured in a manner similar to that described in conjunction with the VCSEL device 200.

[0071] In addition, the module 500 may include a housing 550. The VCSEL device 501 may be attached to the housing 550. For example, the housing 550 may include a substrate, and the VCSEL device 501 may be attached to the substrate (e.g., at an edge of the VCSEL device 501) by bonding or the like. As examples, the housing 550 may include a box (e.g., where the base of the box is the substrate), a tray (e.g., where the base of the tray is the substrate), or a plate (e.g., where the plate is the substrate).

[0072] In some embodiments, the housing 550 can include an aperture 552. That is, the substrate of the housing 550 can include the aperture 552. The emission area of ​​the bottom-emitting VCSEL 506 or the emission area of ​​the top-emitting VCSEL 510 can be aligned with the aperture 552 of the housing 550 (e.g., such that light emitted from the bottom-emitting VCSEL 506 or the top-emitting VCSEL 510 passes through the aperture 552). For example, the emission area of ​​the bottom-emitting VCSEL 506 can be aligned with the aperture 552 of the housing 550 (e.g., such that the aperture surrounds the emission area of ​​the bottom-emitting VCSEL 506 and light emitted from the bottom-emitting VCSEL 506 passes through the aperture 552), as shown.

[0073] In some embodiments, module 500 can include one or more optical elements (not shown) attached to housing 550. For example, an optical element for bottom-emitting VCSEL 506 can be attached to the substrate at a surface of the substrate opposite from VCSEL device 501. Here, the optical element can be attached to or otherwise aligned with aperture 552. As another example, an optical element for top-emitting VCSEL 510 can be attached to the housing above VCSEL device 501.

[0074] As mentioned above, Figure 5 are provided as examples. Other examples can be found in the Figure 5 The examples described are different.

[0075] In some embodiments, VCSEL device 200, VCSEL device 300, and / or VCSEL device 501 can utilize a vertical emission device other than a VCSEL, as described herein. In some embodiments, a module can include VCSEL device 200, VCSEL device 300, and / or VCSEL device 501. For example, VCSEL device 200, VCSEL device 300, and / or VCSEL device 501 can be disposed in a housing having one or more additional electrical components (e.g., circuitry for driving VCSEL device 200, VCSEL device 300, and / or VCSEL device 501) and / or optical components (e.g., optical elements such as lenses, diffusers, diffractive optical elements, etc.). In some embodiments, a light source (e.g., for three-dimensional sensing (3DS) or LIDAR) can include VCSEL device 200, VCSEL device 300, and / or VCSEL device 501. In some embodiments, the optical system can include VCSEL device 200, VCSEL device 300, and / or VCSEL device 501. Additionally, the optical system can include one or more lenses, one or more optical elements (e.g., diffractive optical elements, refractive optical elements, etc.), one or more reflector elements, and / or one or more optical sensors, among other examples.

[0076] In some embodiments, a VCSEL can achieve bidirectional light emission as described herein from the same active region. For example, the reflectivity of the top and bottom mirrors of the VCSEL can be configured such that light is emitted from both sides (e.g., top and bottom) of the VCSEL.

[0077] Figure 6 is a flow chart of an exemplary process 600 for forming a bidirectional VCSEL as described herein.

[0078] like Figure 6 As shown, process 600 may include growing a first set of epitaxial layers for a bottom emitting VCSEL (e.g., a lower VCSEL) on a substrate layer (block 610). The substrate layer may correspond to substrate layer 202, 302, or 502. The first set of epitaxial layers may correspond to the first set of epitaxial layers 204, 304, or 504. Figure 6As further shown in FIG6 , process 600 may include growing a second set of epitaxial layers for a top-emitting VCSEL (e.g., an upper VCSEL) on the first set of epitaxial layers (block 620). The second set of epitaxial layers may correspond to the second set of epitaxial layers 208, 308, or 508. During growth between the sets of mirrors of the first and second sets of epitaxial layers, limiting the epitaxial quality and thickness by introducing epitaxial dislocations or other strain effects should be avoided.

[0079] The first group of epitaxial layers and the second group of epitaxial layers can be grown on the same substrate layer during the same growth process. In addition, the first group of epitaxial layers and the second group of epitaxial layers can be grown with different numbers of active layers and / or emit light at different emission wavelengths. In some embodiments, in order to configure different emission wavelengths for the first group of epitaxial layers and the second group of epitaxial layers, different growth processes can be used for the first group of epitaxial layers and the second group of epitaxial layers. For example, metal organic vapor phase epitaxy (MOVPE) and / or metal organic chemical vapor deposition (MOCVD) can be used to produce shorter wavelengths (e.g., 850nm, 905nm and / or 940nm), and molecular beam epitaxy (MBE) can be used to produce longer wavelengths (e.g., greater than 1300nm).

[0080] like Figure 6 As further shown in FIG, process 600 may include etching a portion of the second set of epitaxial layers until the surface of the first set of epitaxial layers is exposed (block 630). For example, to etch the portion of the second set of epitaxial layers, process 600 may include masking the second set of epitaxial layers in areas where operation (e.g., light emission) of the top-emitting VCSELs is desired, and performing an etching process (e.g., a wet etch, a dry etch, or a combination thereof) to remove the second set of epitaxial layers in areas where operation (e.g., light emission) of the bottom-emitting VCSELs is desired. In some embodiments, the second set of epitaxial layers may be etched to produce a pattern for VCSEL array 400, a pattern for VCSEL array 410, and / or a pattern for VCSEL array 420, among other examples.

[0081] like Figure 6As further shown in FIG6 , process 600 may include forming at least one of a bottom-emitting VCSEL in the first set of epitaxial layers or a top-emitting VCSEL in the second set of epitaxial layers (block 640). Forming the bottom-emitting VCSEL and / or the top-emitting VCSEL may include depositing metal contacts for the bottom-emitting VCSEL and / or the top-emitting VCSEL, exposing oxide layers of the bottom-emitting VCSEL and / or the top-emitting VCSEL, etc. In some embodiments, both the bottom-emitting VCSEL and the top-emitting VCSEL may be formed after the etching described in conjunction with block 630. In some embodiments, the top-emitting VCSEL may be formed before the etching described in conjunction with block 630, and the bottom-emitting VCSEL may be formed after the etching described in conjunction with block 630.

[0082] In some embodiments, bottom-emitting VCSELs and top-emitting VCSELs can be formed independently. For example, a bottom-emitting VCSEL can be formed by masking regions of the VCSEL device except for the regions of the bottom-emitting VCSELs, and a top-emitting VCSEL can be formed by masking regions of the VCSEL device except for the regions of the top-emitting VCSELs. In some embodiments, the bottom-emitting VCSELs and top-emitting VCSELs can be formed simultaneously, for example, by simultaneously depositing corresponding metal contacts for each VCSEL and / or by simultaneously exposing corresponding oxide layers for each VCSEL.

[0083] In this manner, process 600 improves tolerances of VCSEL devices and eliminates the need for multiple wafers and / or multiple growth runs to produce VCSEL devices suitable for bidirectional light emission.

[0084] Process 600 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0085] although Figure 6 Example blocks of process 600 are shown, but in some implementations, process 600 includes Figure 6 The process 600 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. Additionally or alternatively, two or more blocks of the blocks of process 600 may be executed in parallel.

[0086] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be acquired from practice of the embodiments. Furthermore, any embodiment described herein may be combined unless the foregoing disclosure explicitly provides reasons why one or more embodiments may not be combined.

[0087] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may be directly dependent on only one claim, the disclosure of the various embodiments includes the combination of each dependent claim with every other claim in the claim set. As used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including single members. As an example, "at least one of A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as any combination with multiples of the same item.

[0088] Unless clearly described as such, the element, action or instruction used herein should not be interpreted as key or necessary. In addition, as used herein, the article "one" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more projects quoted in conjunction with the article "the", and can be used interchangeably with "one or more". In addition, as used herein, the term "set" is intended to include one or more projects (for example, related projects, unrelated projects or the combination of related and unrelated projects). In the case of only intending a project, phrase "only one" or similar language is used. In addition, as used herein, the term "has", "have", "having" etc. are intended to be open terms. In addition, unless otherwise clearly stated, phrase "based on" is intended to represent "at least partially based on". In addition, as used herein, the term "or" is intended to be inclusive when used in series, and can be used interchangeably with "and / or", unless otherwise clearly stated (for example, if used in combination with "either" or "only one in". Additionally, for ease of description, spatially relative terms, such as "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device, apparatus, and / or element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

Claims

1. A vertical cavity surface emitting laser device comprising: substrate layer; A first group of epitaxial layers for a bottom-emitting vertical cavity surface emitting laser is provided on the substrate layer, the first group of epitaxial layers comprising: a first set of mirrors; and at least one first active layer; and a second set of epitaxial layers for a top-emitting vertical cavity surface emitting laser, disposed on the first set of epitaxial layers for the bottom-emitting vertical cavity surface emitting laser, the second set of epitaxial layers comprising: a second set of mirrors; and at least one second active layer, wherein the top-emitting vertical cavity surface emitting laser and the bottom-emitting vertical cavity surface emitting laser are configured to emit light in opposite light emission directions.

2. The VCSEL device according to claim 1 , further comprising at least one of the following: an electrically isolating layer between the first set of epitaxial layers and the second set of epitaxial layers; a contact layer between the first set of epitaxial layers and the second set of epitaxial layers; or A tunnel junction is formed between the first set of epitaxial layers and the at least one second active layer.

3. The vertical cavity surface emitting laser device according to claim 1 , further comprising: A layer of bulk material is between the first set of epitaxial layers and the second set of epitaxial layers.

4. The vertical cavity surface emitting laser device according to claim 1 , wherein the first group of reflecting mirrors comprises a first reflecting mirror and a second reflecting mirror, and The second group of reflectors includes the second reflector and a third reflector. 5 . The VCSEL device of claim 1 , wherein a surface of the substrate layer opposite to the first set of epitaxial layers includes an optical element for the bottom-emitting VCSEL.

6. The VCSEL device of claim 1, wherein the first emission region of the bottom-emitting VCSEL and the second emission region of the top-emitting VCSEL are offset in a direction orthogonal to the opposite light emission directions.

7. The VCSEL device of claim 1, wherein the first emission region of the bottom-emitting VCSEL and the second emission region of the top-emitting VCSEL are aligned in a direction orthogonal to the opposite light emission directions. 8 . The VCSEL device of claim 1 , wherein a first number of active layers of the at least one first active layer is different from a second number of active layers of the at least one second active layer.

9. The VCSEL device of claim 1, wherein a first emission wavelength of the bottom-emitting VCSEL is different from a second emission wavelength of the top-emitting VCSEL.

10. A device for emitting light in opposite directions, comprising: a housing, the housing comprising an aperture; as well as a vertical cavity surface emitting laser device attached to the housing, the vertical cavity surface emitting laser device comprising: substrate layer; A first group of epitaxial layers for a bottom-emitting vertical cavity surface emitting laser is provided on the substrate layer, the first group of epitaxial layers comprising: a first set of mirrors; and at least one first active layer; and a second set of epitaxial layers for a top-emitting vertical cavity surface emitting laser, disposed on the first set of epitaxial layers for the bottom-emitting vertical cavity surface emitting laser, the second set of epitaxial layers comprising: a second set of mirrors; and at least one second active layer; wherein the top-emitting vertical cavity surface emitting laser and the bottom-emitting vertical cavity surface emitting laser are configured to emit light in opposite light emission directions, and wherein the first emission region of the bottom-emitting vertical cavity surface emitting laser or the second emission region of the top-emitting vertical cavity surface emitting laser is aligned with the hole of the housing.

11. The apparatus of claim 10, wherein the first emission region of the bottom-emitting vertical cavity surface emitting laser is aligned with the aperture of the housing.

12. The apparatus of claim 10, wherein a surface of the substrate layer opposite the first set of epitaxial layers comprises optical elements for the bottom-emitting vertical cavity surface emitting laser.

13. The apparatus according to claim 10, further comprising: At least one optical element for said top-emitting vertical cavity surface emitting laser.

14. The apparatus of claim 10, wherein the first bottom reflector in the first set of reflectors and the second bottom reflector in the second set of reflectors are one of n-type or p-type, wherein the first top reflector in the first group of reflectors and the second top reflector in the second group of reflectors are the other of n-type or p-type, and A tunnel junction is formed between the first set of epitaxial layers and the at least one second active layer.

15. The device of claim 10, wherein the first emission region of the bottom-emitting vertical cavity surface emitting laser and the second emission region of the top-emitting vertical cavity surface emitting laser are aligned in a direction orthogonal to the opposite light emission directions. 16 . The device of claim 10 , wherein a first number of active layers of the at least one first active layer is different from a second number of active layers of the at least one second active layer.

17. The apparatus of claim 10, wherein a first emission wavelength of the bottom-emitting VCSEL is different from a second emission wavelength of the top-emitting VCSEL.

18. The device of claim 10, wherein the vertical cavity surface emitting laser device further comprises at least one of the following: an electrically isolating layer between the first set of epitaxial layers and the second set of epitaxial layers; a contact layer between the first set of epitaxial layers and the second set of epitaxial layers; or A tunnel junction is formed between the first set of epitaxial layers and the at least one second active layer.

19. The device of claim 10, wherein the vertical cavity surface emitting laser device further comprises: A layer of bulk material is between the first set of epitaxial layers and the second set of epitaxial layers.

20. The apparatus of claim 10, wherein the first set of reflectors comprises a first reflector and a second reflector, and The second group of reflectors includes the second reflector and a third reflector.

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