Boot strap switch

Abstract

The present invention discloses a bootstrap switch, comprising: a first transistor, a second transistor, a first capacitor, three switches, and a switching circuit. The switching circuit comprises the first switch, the second switch, the second capacitor, and an inverter circuit. The first transistor receives an input voltage and outputs an output voltage. The first end of the second transistor receives an input voltage, and the second end is coupled to the first end of the first capacitor. The control end of the first switch receives a clock. The first switch is coupled between a node and a reference voltage. The second switch is coupled between the control end of the first transistor and the node. The input end of the inverter circuit is coupled to the control end of the first switch. The second capacitor is coupled between the node and the output end of the inverter circuit.

Description

Technical Field

[0001] The present application relates to a bootstrapped switch, and more particularly to a bootstrapped switch capable of rapid turn-on and turn-off. Background Art

[0002] Figure 1 The following is a circuit diagram of a conventional bootstrap switch. Bootstrap switch 10 includes switch 101, switch 102, switch 103, switch 104, switch 105, an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (hereinafter referred to as NMOS transistor) 106, and a bootstrap capacitor 107. The input terminal VI and output terminal VO of bootstrap switch 10 are coupled to the source and drain of NMOS transistor 106, respectively. The gate of NMOS transistor 106 is coupled to voltage source V3 via switch 105 and to one end of bootstrap capacitor 107 and one end of switch 101 via switch 104. The other end of switch 101 is coupled to voltage source V1. The other end of the pull-up capacitor 107 is coupled to a voltage source V2 via a switch 102, and to the source of the NMOS transistor 106 and the input terminal V1 of the bootstrap switch 10 via a switch 103. The voltage source V1 is at a high voltage potential VDD, while the voltage sources V2 and V3 are at ground potential. The operation of the bootstrap switch 10 is well known to those skilled in the art and will not be described in detail.

[0003] The state of switch 105 (conductive or non-conductive) determines the state of NMOS transistor 106 (conductive or non-conductive). In other words, the shorter the response time of switch 105 (i.e., the faster the gate of NMOS transistor 106 reaches the target voltage), the more closely the state of NMOS transistor 106 is aligned with the system clock, resulting in better performance of bootstrap switch 10 (e.g., faster speed and more accurate sampling results). In other words, the design of switch 105 plays a crucial role in bootstrap switch 10. Summary of the Invention

[0004] In view of the deficiencies of the prior art, one object of the present invention is to provide a boot strap switch to improve the deficiencies of the prior art.

[0005] One embodiment of the present invention provides a bootstrap switch for receiving an input voltage and outputting an output voltage, comprising: a first transistor, a first capacitor, a second transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an inverter circuit, and a second capacitor. The first transistor has a first terminal, a second terminal, and a first control terminal, wherein the first transistor receives the input voltage at the first terminal and outputs the output voltage at the second terminal. The first capacitor has a third terminal and a fourth terminal; the second transistor has a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage at the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. The first switch is coupled between the third terminal of the first capacitor and a first reference voltage. The second switch is coupled between the fourth terminal of the first capacitor and a second reference voltage. The third switch is coupled between the fourth terminal of the first capacitor and the first control terminal of the first transistor. The fourth switch is coupled between the first control terminal of the first transistor and a node. The fifth switch has a third control terminal and is coupled between the node and the first reference voltage. The inverter circuit has an input terminal and an output terminal, wherein the input terminal is coupled to the third control terminal of the fifth switch, and the inverter circuit is configured to invert a voltage at the third control terminal. The second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the output terminal of the inverter circuit, and the eighth terminal is coupled to the node.

[0006] The bootstrap switch of the present invention can be turned on and / or turned off quickly. Compared with the conventional technology, the bootstrap switch of the present invention can operate at a higher speed.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A circuit diagram of an existing boot strap switch;

[0009] Figure 2 A circuit diagram of an embodiment of a boot strap switch according to the present invention;

[0010] Figure 3 An example showing clock Φ1 and clock Φ1b;

[0011] Figure 4 is a computer simulated waveform diagram of the voltage at the node Nq and the voltage at the control terminal of the transistor M1; and

[0012] Figure 5 FIG. 4 is a circuit diagram of another embodiment of a boot strap switch according to the present invention. DETAILED DESCRIPTION

[0013] The technical terms used in the following descriptions refer to the customary terms in the technical field. If this specification provides explanations or definitions for some terms, the interpretation of those terms shall be based on the explanations or definitions in this specification.

[0014] The present invention includes a bootstrap switch. Since some components of the bootstrap switch may be known components, details of known components will be omitted below without affecting the full disclosure and feasibility of the present invention.

[0015] Figure 2 The circuit diagram of one embodiment of the bootstrap switch of the present invention is shown. The bootstrap switch 100 receives an input voltage Vin from an input terminal IN and outputs an output voltage Vout from an output terminal OUT. The bootstrap switch 100 includes a switch 110, a switch 120, a switch 130, a switch 140, a switch 150, a switch 160, a switch 170, a lift capacitor Cb, a capacitor Cq, and an inverter circuit 180. The switch circuit SW1 corresponds to Figure 1 Switch 105. Switch 110, switch 120, switch 130, switch 140, switch 150, switch 160, and switch 170 can be implemented by transistor M1, transistor M7, transistor M2, transistor M3, transistor M8, transistor M4, and transistor M11, respectively. Each transistor has a first terminal, a second terminal, and a control terminal, and the first terminal and the second terminal are the two terminals of the switch formed by the transistor. For a metal-oxide-semiconductor field-effect transistor (MOSFET), the first terminal can be one of the source and the drain, the second terminal is the other of the source and the drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be one of the collector and the emitter, the second terminal is the other of the collector and the emitter, and the control terminal is the base.

[0016] like Figure 2 As shown, the control terminal of transistor M1 and the control terminal of transistor M7 are electrically connected to each other. Transistor M1 receives input voltage Vin at a first terminal and outputs output voltage Vout from a second terminal. A first terminal of transistor M7 receives input voltage Vin, and a second terminal of transistor M7 is electrically connected to a first terminal of lift capacitor Cb. A first terminal of transistor M2 is coupled to a first terminal of lift capacitor Cb, and a second terminal of transistor M2 is coupled to a first reference voltage (at Figure 2 The first terminal of the transistor M3 is coupled to the second reference voltage (in the example of Figure 2 In the example, the power supply voltage VDD is higher than the ground level GND), and the second end of the transistor M3 is coupled to the second end of the pull-up capacitor Cb. The first end of the transistor M8 is coupled to the control end of the transistor M1, and the second end of the transistor M8 is coupled to the second end of the pull-up capacitor Cb. The first end of the transistor M4 is coupled to or electrically connected to the control end of the transistor M1 and the control end of the transistor M7, the control end of the transistor M4 is coupled to or electrically connected to the power supply voltage VDD, and the second end of the transistor M4 is coupled to or electrically connected to the node Nq. The first end of the transistor M11 is coupled to or electrically connected to the node Nq, and the second end of the transistor M11 is coupled to or electrically connected to the first reference voltage (ground level GND). The control end of the transistor M11 receives the clock Φ1b. The first end of the capacitor Cq is coupled to or electrically connected to the node Nq. The input end of the inverter circuit 180 receives the clock Φ1b, and the output end of the inverter circuit 180 is coupled to or electrically connected to the second end of the capacitor Cq.

[0017] The switches 130 , 140 , 150 and 170 are conductive (corresponding transistors are turned on) or non-conductive (corresponding transistors are turned off) according to the clocks Φ1 and Φ1 b. Figure 3 An example of clock Φ1 and clock Φ1b is shown. Clock Φ1 and clock Φ1b are inverted signals. Controlled by clock Φ1 and clock Φ1b, bootstrap switch 100 alternates between a first clock phase Ph1 (a period during which clock Φ1 is at a first level (e.g., a low level) and clock Φ1b is at a second level (e.g., a high level)) and a second clock phase Ph2 (a period during which clock Φ1 is at a second level and clock Φ1b is at a first level). The following describes the detailed operation of bootstrap switch 100.

[0018] refer to Figure 2 and Figure 3 During the first clock phase Ph1 (when the clock Φ1 is at a low level and the clock Φ1b is at a high level), the switches 130, 140, 160, and 170 are turned on, and the switch 150 is turned off. When the switches 160 and 170 are turned on, the voltages at the control terminals of the transistors M1 and M7 are substantially equal to the first reference voltage (ground level GND), so that the switches 110 and 120 are turned off. In other words, the switches 110 and 120 are turned off during the first clock phase Ph1. When the switches 130 and 140 are turned on, the voltages across the pull-up capacitor Cb are substantially equal to the first reference voltage (ground level GND) and the second reference voltage (power supply voltage VDD), respectively. In other words, the pull-up capacitor Cb is charged during the first clock phase Ph1, and after the first clock phase Ph1 ends, the voltage Vcb across the pull-up capacitor Cb is substantially equal to the voltage difference between the first reference voltage and the second reference voltage.

[0019] During the second clock phase Ph2 (when clock Φ1 is at a high level and clock Φ1b is at a low level), switches 130, 140, 160, and 170 are non-conductive, and switch 150 is conductive. When switch 150 is conductive, the control terminals of transistors M1 and M7 are substantially equal in potential to the second terminal of pull-up capacitor Cb, causing transistors M1 and M7 to turn on due to the voltage Vcb across pull-up capacitor Cb. When transistor M7 is turned on, the voltage across the second terminal of pull-up capacitor Cb and the control terminal of transistor M1 are substantially equal to the sum of input voltage Vin and voltage Vcb. When transistor M1 is turned on, output voltage Vout is substantially equal to input voltage Vin, indicating that bootstrap switch 100 is conductive.

[0020] The voltage at the control terminal of transistor M1 may be greater than the power supply voltage VDD (even nearly twice the power supply voltage VDD), while transistor M11 may be in a state where both its control terminal (gate) and second terminal (source) are connected to ground level GND. In some related arts, if the first terminal (drain) of transistor M11 is directly electrically connected to transistor M1, the high voltage at the control terminal of transistor M1 (which, as mentioned above, can be as high as nearly twice the power supply voltage VDD) will significantly reduce the lifespan of transistor M11. To improve the above problem, one purpose of transistor M4 of the present invention is to isolate the control terminal of transistor M1 from transistor M11, thereby preventing the first terminal of transistor M11 from being subjected to this high voltage. Because the control terminal of transistor M4 is coupled to or electrically connected to the power supply voltage VDD, the voltages between the first terminal, second terminal, and control terminal of transistor M4 are all lower than the power supply voltage VDD, allowing transistor M4 to withstand this high voltage. However, the transistor M4 slows down the speed at which the control terminal of the transistor M1 switches from the second potential (e.g., a high potential) to the first potential (e.g., a low potential). This causes the bootstrap switch 100 to be unable to immediately switch from the conductive state to the non-conductive state after entering the first clock phase Ph1. In other words, the transistor M4 may slow down the switching speed of the bootstrap switch 100.

[0021] One purpose of the capacitor Cq and the inverter circuit 180 is to quickly pull up or down the voltage of the node Nq, thereby accelerating the switching speed of the transistor M4 (i.e., increasing the voltage conversion speed of the control terminal of the transistor M1, which is equivalent to accelerating the switching speed of the bootstrap switch 100).

[0022] When clock Φ1b transitions from the first level to the second level (transistor M11 begins to conduct but is not yet fully turned on), inverter circuit 180 outputs an output signal that is in phase with clock Φ1b (i.e., a signal at the first level). This output signal is then coupled to node Nq via capacitor Cq, allowing the voltage at node Nq to begin decreasing before transistor M11 is fully turned on. Once the voltage at node Nq begins to decrease, the voltage across the first and second terminals of transistor M4 increases, thereby increasing the conduction capability of transistor M4. In other words, inverter circuit 180 and capacitor Cq significantly help transistor M4 turn on earlier, thereby causing the voltage at the control terminal of transistor M1 to decrease more quickly (i.e., accelerating the turn-off speed of bootstrap switch 100).

[0023] When clock Φ1b transitions from the second level to the first level (transistor M11 begins to turn off but has not yet fully turned off), inverter circuit 180 outputs an output signal that is in phase with clock Φ1b (i.e., a signal at the second level). This output signal is then coupled to node Nq via capacitor Cq, allowing the voltage at node Nq to begin rising before transistor M11 fully turns off. Once the voltage at node Nq begins to rise, it pulls up the voltage at the control terminal of transistor M1 through transistor M4. In other words, inverter circuit 180 and capacitor Cq enable the voltage at the control terminal of transistor M1 to rise more quickly (i.e., speeding up the turn-on speed of bootstrap switch 100).

[0024] Figure 4 The graph is a computer simulation waveform of the voltage at the node Nq and the voltage at the control terminal of the transistor M1. Curves g2 and b2 represent the voltage at the node Nq, and curves g3 and b3 represent the voltage at the control terminal of the transistor M1. Curves g2 and g3 correspond to a bootstrap switch (e.g., a circuit comprising an inverter circuit 180 and a capacitor Cq) Figure 2 The boot strap switch 100), and the curve b2 and the curve b3 correspond to the boot strap switch without the inverter circuit 180 and the capacitor Cq (for example Figure 2 The circuit is the same as above, but with the inverter circuit 180 and capacitor Cq removed. Figure 4 As can be seen, when clock Φ1b transitions from the first level to the second level (e.g., time T1), curve g3 falls faster than curve b3 (the slope of curve g3 is greater than the slope of curve b3). This means that the voltage at the control terminal of transistor M1 reaches the first level approximately T3-T2 earlier. When clock Φ1b transitions from the second level to the first level (e.g., time T4), curve g3 begins to rise earlier than curve b3, indicating that bootstrap switch 100 starts up more quickly. The voltage at node Nq also exhibits a similar trend, so this will not be further described.

[0025] In some embodiments, the inverter circuit 180 includes an odd number of inverters, and the capacitance of the capacitor Cq can be approximately tens to hundreds of femtofarads (fF), preferably between 10 femtofarads and 100 femtofarads. The capacitance of the capacitor Cq is also a trade-off. If the capacitance of the capacitor Cq is too large, the size of the inverter circuit 180 will be increased, causing the added inverter circuit 180 and the capacitor Cq to operate slower than the transistor M11.

[0026] Figure 5 This is a circuit diagram of another embodiment of a bootstrap switch according to the present invention. Bootstrap switch 500 is similar to bootstrap switch 100, except that bootstrap switch 500 further includes switches 185, 190, and 195. Switches 185, 190, and 195 are implemented by transistors M9, M5, and M6, respectively. Switch 185 is coupled between a second reference voltage and the control terminal of transistor M8 and is controlled by clock Φ1. Switch 190 is coupled between the first terminal of pull-up capacitor Cb and the control terminal of transistor M8 and is controlled by clock Φ1. Switch 195 is coupled between the first terminal of pull-up capacitor Cb and the control terminal of transistor M8, and the control terminal of transistor M6 is electrically connected to the control terminals of transistor M1 and transistor M7. Transistors M5, M6, and M9 are used to provide overvoltage protection during operation of bootstrap switch 500, thereby extending the service life of the components. The operating principles of these transistors are well known to those skilled in the art and will not be further described.

[0027] In summary, the inverter circuit 180 and the capacitor Cq help the voltage on the node Nq and the voltage on the control terminal of the transistor M1 to rise or fall earlier and / or rise or fall faster, so that the bootstrap switch has a faster response speed (ie, can operate at a higher speed).

[0028] In other embodiments, the PMOS transistor and the NMOS transistor in the aforementioned embodiments may be replaced by an NMOS transistor and a PMOS transistor, respectively. A person skilled in the art would know how to adaptably adjust the phase or level of the clock Φ1 and the clock Φ1b, and adaptably adjust the first reference voltage and the second reference voltage to implement the aforementioned implementation.

[0029] Please note that the shapes, sizes and proportions of the components in the above-mentioned figures are merely illustrative and are provided to help those skilled in the art understand the present invention, and are not intended to limit the present invention.

[0030] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may modify the technical features of the present invention based on the explicit or implicit contents of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0031]

Explanation of symbols

[0032] 10,100,500: Bootstrap switch

[0033] 101,102,103,104,105,110,120,130,140,150,160,170,185,190,195: switch

[0034] 106: N-type metal oxide semiconductor field effect transistor

[0035] 107, Cb: lifting capacitor

[0036] VI,IN: input terminal

[0037] VO,OUT:output terminal

[0038] V1, V2, V3: voltage source

[0039] Vin: input voltage

[0040] Vout: output voltage

[0041] SW1: switch circuit

[0042] Cq: capacitance

[0043] 180: Inverter circuit

[0044] M1, M7, M2, M3, M8, M4, M11, M9, M5, M6: Transistor GND: Ground level

[0045] VDD: power supply voltage

[0046] Nq: Node

[0047] Φ1, Φ1b: clock

[0048] Ph1: First clock phase

[0049] Ph2: Second clock phase

[0050] Vcb: cross voltage

[0051] g2,b2,g3,b3: curve

[0052] T1, T2, T3, T4: time points.

Claims

1. A bootstrap switch for receiving an input voltage and outputting an output voltage, comprising: A first transistor has a first terminal, a second terminal and a first control terminal, wherein The first transistor receives the input voltage through the first terminal and outputs the output voltage through the second terminal; a first capacitor having a third terminal and a fourth terminal; a second transistor having a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage through the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor; a first switch coupled between the third terminal of the first capacitor and a first reference voltage; a second switch coupled between the fourth terminal of the first capacitor and a second reference voltage; a third switch coupled between the fourth terminal of the first capacitor and the first control terminal of the first transistor; a fourth switch coupled between the first control terminal of the first transistor and a node; a fifth switch having a third control terminal and coupled between the node and the first reference voltage; an inverter circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the third control terminal of the fifth switch, and the inverter circuit is used to invert a voltage at the third control terminal; and A second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the output terminal of the inverter circuit, and the eighth terminal is coupled to the node.

2. The boot strap switch according to claim 1, wherein: During a first clock phase, the first switch, the second switch, the fourth switch, and the fifth switch are turned on and the third switch is turned off to charge the first capacitor. During a second clock phase, the third switch is turned on and the first switch, the second switch, the fourth switch, and the fifth switch are turned off.

3. The boot strap switch according to claim 1, wherein: The fourth switch has a fourth control terminal, and the fourth control terminal is electrically connected to the second reference voltage.

4. The boot strap switch according to claim 1, wherein: The inverter circuit includes an odd number of inverters.

5. The boot strap switch according to claim 1, wherein: The capacitance of the second capacitor is between 10 femtofarads and 100 femtofarads.

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