Clock synchronization method and apparatus in digital subcarrier multiplexing system

Abstract

This invention relates to a clock synchronization method and apparatus in a digital subcarrier multiplexing system. The method includes: interpolating a multiplexed signal sampling sequence comprising multiple subcarriers based on a fractional interval and a basic pointer; demultiplexing the multiplexed signal sampling sequence to obtain multiple subcarrier signal sampling sequences; performing dispersion compensation on each of the multiple subcarrier signal sampling sequences; selecting a target subcarrier signal sampling sequence from the dispersion-compensated multiple subcarrier signal sampling sequences for timing error detection to obtain timing error information; calculating the fractional interval and the basic pointer based on the timing error information; determining the conversion parameter of the fractional interval based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter; and interpolating the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval. This completes one feedback loop, and after several feedback loops, the timing error of the multiplexed signal sampling sequence is eliminated.

Description

Technical Field

[0001] This invention relates to the field of optical fiber communication technology, and in particular to a clock synchronization method and apparatus in a digital subcarrier multiplexing system. Background Technology

[0002] With the near-full utilization of available frequencies in the C+L band of optical fiber, traditional wavelength division multiplexing (WDM) systems, which rely solely on increasing the number of multiplexed wavelengths or reducing channel spacing, face a physical bottleneck that limits further capacity improvements. Optical transmission systems are under immense bandwidth pressure. Against this backdrop, single-wavelength channel 800Gbps and higher coherent optical transmission technologies have become key technologies in the field of high-capacity, long-distance optical fiber transmission. Digital subcarrier multiplexing (DSCM) systems not only possess technical advantages such as enhanced dispersion and nonlinearity tolerance and equalization-enhanced phase noise (EEPN) reduction, but also allow for flexible adjustment of transmission rate and distance through dynamic subcarrier configuration, achieving optimal adaptation to dynamic optical connections. This has made it one of the most powerful system solutions supporting single-wavelength channel 800Gbps and higher transmission rates, and therefore has received continuous attention from researchers in academia and industry both domestically and internationally in recent years.

[0003] In digital subcarrier multiplexing (DSCM) systems, clock synchronization is one of the fundamental functions of the receiver's digital signal processing (DSP) algorithm module. Currently proposed clock synchronization schemes for DSCM systems include synchronizing the clock of each subcarrier signal separately using DSP algorithms. However, these DSCM clocking techniques have some shortcomings, namely, the existing clock synchronization schemes result in complex circuit structures and high algorithm complexity. Summary of the Invention

[0004] This invention provides a clock synchronization method and apparatus in a digital subcarrier multiplexing system to address the shortcomings of existing clock synchronization schemes, which result in complex circuit structures and high algorithm complexity.

[0005] This invention provides a clock synchronization method in a digital subcarrier multiplexing system, comprising:

[0006] Interpolation is performed on the multiplexed signal sampling sequence, which includes multiple subcarriers, based on fractional intervals and basic pointers;

[0007] The multiplexed signal sampling sequence is demultiplexed with subcarriers to obtain a multi-subcarrier signal sampling sequence;

[0008] Dispersion compensation is performed on the sampling sequences of the multi-subcarrier signals respectively;

[0009] Select one target subcarrier signal sampling sequence from the dispersion-compensated multi-subcarrier signal sampling sequence for timing error detection to obtain timing error information;

[0010] Calculate the fractional interval and basic pointer based on the timing error information;

[0011] The conversion parameters of the fractional interval are determined based on the symbol rate of each of the subcarrier signal sampling sequences, and the fractional interval is converted according to the conversion parameters; the conversion parameters are used to shorten the period of the fractional interval while keeping the amplitude unchanged;

[0012] Based on the basic pointer and the converted fractional interval, the multiplexed signal sampling sequence is interpolated, thus completing one feedback loop. After several feedback loops, the timing error of the multiplexed signal sampling sequence is eliminated.

[0013] A clock synchronization method in a digital subcarrier multiplexing system provided by the present invention,

[0014] The step of determining the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and converting the fractional interval according to the conversion parameters, includes:

[0015] The conversion parameters of the fractional interval are determined based on the sum of the symbol rates of the sampling sequences of each subcarrier signal and the symbol rate of the sampling sequence of the target subcarrier signal, and the fractional interval is converted according to the conversion parameters.

[0016] A clock synchronization method in a digital subcarrier multiplexing system provided by the present invention,

[0017] The conversion parameter for determining the fractional interval based on the sum of the symbol rates of each of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence is calculated using the following formula:

[0018]

[0019] Where M represents the transformation parameter, R SCi R represents the symbol rate of the subcarrier signal sampling sequence i. SC_TED R represents the symbol rate of the target subcarrier signal sampling sequence. SC1 +R SC2 +…+R SCi The sum of the symbol rates based on the sampling sequences of each subcarrier signal is used to determine M. After that, the period of the fractional interval is shortened by a factor of M while keeping its amplitude unchanged.

[0020] A clock synchronization method in a digital subcarrier multiplexing system provided by the present invention,

[0021] The calculation of the fractional interval and basic pointer based on the timing error information includes:

[0022] The timing error information is filtered to output a control word;

[0023] The fractional interval and basic pointer are calculated based on the control word.

[0024] A clock synchronization method in a digital subcarrier multiplexing system provided by the present invention,

[0025] The interpolation of the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval includes:

[0026] Based on the basic pointer and the converted fractional interval, polynomial interpolation is performed on the multiplexed signal sampling sequence using Lagrange interpolation or linear interpolation to correct timing errors on the multiplexed signal sampling sequence.

[0027] The present invention also provides a clock synchronization device in a digital subcarrier multiplexing system, comprising:

[0028] An interpolation module is used to interpolate the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval;

[0029] A subcarrier demultiplexing module is used to demultiplex the multiplexed signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence.

[0030] A dispersion compensation module is used to perform dispersion compensation on the multi-subcarrier signal sampling sequence;

[0031] The timing error detection module is used to select one target subcarrier signal sampling sequence from the dispersion-compensated multi-subcarrier signal sampling sequence for timing error detection, and obtain timing error information.

[0032] A fractional interval and basic pointer calculation module is used to calculate the fractional interval and basic pointer based on the timing error information;

[0033] A fractional interval conversion module is used to determine the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and to convert the fractional interval according to the conversion parameters; the conversion parameters are used to shorten the period of the fractional interval while keeping the amplitude unchanged;

[0034] The operation control module is used to control the parameters of the subcarrier demultiplexing module, the dispersion compensation module, the timing error detection module, the fractional interval and basic pointer calculation module, the fractional interval conversion module, and the interpolation module.

[0035] The clock synchronization method and apparatus in a digital subcarrier multiplexing system provided by this invention, based on the characteristic that the clocks of all subcarriers in the digital subcarrier multiplexing system originate from the same source, performs timing error detection only on one target subcarrier signal in the multi-channel subcarrier signal sampling sequence, and then calculates a fractional interval and a basic pointer based on the timing error information obtained from the timing error detection; determines the conversion parameter of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and converts the fractional interval according to the conversion parameter: shortening the period of the fractional interval while keeping its amplitude unchanged; interpolating the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval, and repeating the above steps cyclically, after several feedback loops, the fractional interval changes from an initially irregular change to a stable periodic change, eliminating the timing error on the multiplexed signal sampling sequence. Thus, this embodiment of the invention corrects timing errors on the multiplexed signal sampling sequence and completes the synchronization of all subcarrier signal sampling sequences. Compared to existing solutions that perform clock synchronization for each subcarrier signal sampling sequence separately, the embodiments of the present invention do not require parallel processing of multiple subcarrier signal sampling sequences, thus requiring a smaller circuit area, reducing circuit complexity, and reducing algorithm complexity. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a flowchart illustrating the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention;

[0038] Figure 2 This is a functional block diagram of the DSP used in the DSCM coherent optical receiver according to an embodiment of the present invention;

[0039] Figure 3 This is a spectral diagram of the multiplexed signal of a 4×32GBaud PM-16QAM DSCM system, which consists of four subcarriers, each with a symbol rate of 32GBaud, provided by this invention.

[0040] Figure 4This is a schematic diagram comparing the performance of the clock synchronization method in the digital subcarrier multiplexing system provided by this invention in the 4×32GBaud PM-16QAM DSCM system with the clock synchronization method performed separately for each subcarrier in the existing scheme.

[0041] Figure 5 This is the spectrum of the multiplexed signal of a 128GBaud PM-16QAM DSCM system composed of eight subcarriers with different symbol rates, as provided by this invention.

[0042] Figure 6 This is a schematic diagram comparing the performance of the clock synchronization method provided by this invention in the digital subcarrier multiplexing system of a 128GBaud PM-16QAM DSCM system composed of 8 subcarriers with different symbol rates, with the clock synchronization method for each subcarrier in the existing scheme.

[0043] Figure 7 This is a schematic diagram comparing the algorithm complexity of the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention with the existing method of synchronizing clocks for each subcarrier separately.

[0044] Figure 8 This is a functional structure diagram of the clock synchronization device in the digital subcarrier multiplexing system provided by the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0046] Please refer to Figure 1 A clock synchronization method in a digital subcarrier multiplexing system includes:

[0047] Step 100: Interpolate the multiplexed signal sampling sequence, which includes multiple subcarriers, based on fractional intervals and basic pointers;

[0048] It should be noted that the fractional interval and the basic pointer are determined by the timing error detected from the subcarrier. The initial fractional interval can be a random fractional interval.

[0049] Step 200: Perform subcarrier demultiplexing on the multiplexed signal sampling sequence to obtain a multi-subcarrier signal sampling sequence.

[0050] Specifically, the electronic equipment performs polynomial interpolation on the multiplexed signal sampling sequence, which includes multiple subcarriers, using a basic pointer and an initial fractional interval. The polynomial interpolation can be determined using methods such as Lagrange interpolation or linear interpolation. The electronic equipment then performs subcarrier demultiplexing on the multiplexed signal sampling sequence to obtain a multi-subcarrier signal sampling sequence.

[0051] It should be noted that the subcarrier demultiplexing operation in this embodiment of the invention can employ various time-domain algorithms or frequency-domain algorithms.

[0052] Step 300: Perform dispersion compensation on the sampling sequences of the multi-subcarrier signals respectively;

[0053] Specifically, the electronic equipment performs dispersion compensation on the sampling sequences of each subcarrier signal. The dispersion compensation algorithm can be either a frequency domain algorithm or a time domain algorithm.

[0054] Step 400: Select one target subcarrier signal sampling sequence from the dispersion-compensated multi-subcarrier signal sampling sequence for timing error detection to obtain timing error information.

[0055] The electronic device selects one target subcarrier signal sampling sequence from the dispersion-compensated multi-channel subcarrier signal sampling sequence for timing error detection to obtain timing error information. The target subcarrier signal sampling sequence is any one of the multiple subcarrier signal sampling sequences.

[0056] This invention performs timing error detection on the sampled sequence of a target subcarrier signal and extracts timing error information. The timing error detection algorithm can be selected based on the subcarrier sampling rate. For example, taking a sampling rate of twice the subcarrier symbol rate, the timing error detection can employ the Godard algorithm, the Gardner algorithm, or other clock error detection algorithms. The output of the timing error detection algorithm is represented as ε(n), where n represents the sequence number of the current sampled value.

[0057] Step 500: Calculate the fractional interval and basic pointer based on the timing error information.

[0058] The electronic device determines the fractional interval and basic pointer for interpolating the multiplexed signal sampling sequence based on the timing error information. Specifically, step 500, calculating the fractional interval and basic pointer based on the timing error information, includes:

[0059] Step 510: Filter the timing error information to output a control word.

[0060] Step 520: Calculate the fractional interval and basic pointer based on the control word.

[0061] Specifically, embodiments of the present invention can track timing phase error and timing frequency error. After filtering the timing error information and eliminating noise, a control word W(n) is output.

[0062] The electronic device calculates the basic pointer and fractional interval based on the control word W(n).

[0063] Step 600: Determine the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and convert the fractional interval according to the conversion parameters; the conversion parameters are used to shorten the period of the fractional interval while keeping the amplitude unchanged.

[0064] Specifically, step 600, determining the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and converting the fractional interval according to the conversion parameters, includes:

[0065] The conversion parameters of the fractional interval are determined based on the sum of the symbol rates of the sampling sequences of each subcarrier signal and the symbol rate of the sampling sequence of the target subcarrier signal, and the fractional interval is converted according to the conversion parameters.

[0066] Specifically, the conversion parameter for determining the fractional interval based on the sum of the symbol rates of each of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence is calculated using the following formula:

[0067]

[0068] Where M represents the transformation parameter, R SCi R represents the symbol rate of the subcarrier signal sampling sequence i. SC_TED R represents the symbol rate of the target subcarrier signal sampling sequence. SC1 +R SC2 +…+R SCi The sum of the symbol rates based on the sampling sequences of each subcarrier signal is used to determine M. After that, the fractional interval period is shortened by a factor of M while keeping its amplitude unchanged.

[0069] It should be noted that in digital subcarrier multiplexing systems, different symbol rates R are typically assigned to each subcarrier according to actual needs. SCi A common configuration is to allocate a higher symbol rate to the center subcarriers and a lower symbol rate to the edge subcarriers. Alternatively, all subcarriers can be allocated the same symbol rate. This embodiment of the invention is applicable in both cases, but requires a composite symbol rate of the multiplexed signal sampling sequence. (i.e. R) SC1 +R SC2 +…+R SCiThe required value is the symbol rate R of the target subcarrier signal sampling sequence for which the timing error is being detected. SC_TED The multiples of the integer multiples of the basic pointer and the converted fractional interval are used to interpolate the multiplexed signal sampling sequence to correct timing errors in the multiplexed signal sampling sequence. Specifically, step 100 is then executed: interpolating the multiplexed signal sampling sequence based on the fractional interval and the basic pointer. The electronic device performs polynomial interpolation on the multiplexed signal sampling sequence using Lagrange interpolation or linear interpolation based on the basic pointer and the converted fractional interval to correct timing errors in the multiplexed signal sampling sequence. This completes one feedback loop processing. After multiple feedback loop processing, the fractional interval forms a stable periodic change, the clock synchronization loop finally converges, achieving clock synchronization of all subcarrier signals, and outputting the synchronized subcarrier signal sampling sequence.

[0070] Based on the characteristic that all subcarrier clocks in a digital subcarrier multiplexing system originate from the same source, timing error detection is performed only on one target subcarrier signal in the multi-channel subcarrier signal sampling sequence. Then, based on the timing error information obtained from the timing error detection, a fractional interval and a basic pointer are calculated. The conversion parameters of the fractional interval are determined based on the symbol rate of each subcarrier signal sampling sequence, and the fractional interval is converted according to the conversion parameters. Based on the basic pointer and the converted fractional interval, the multiplexed signal sampling sequence is interpolated to correct the timing error on the multiplexed signal sampling sequence. The above steps are executed iteratively. After several feedback loops, the fractional interval changes from an initially irregular variation to a stable periodic variation, eliminating the timing error on the multiplexed signal sampling sequence. Thus, this embodiment of the invention corrects timing errors on the multiplexed signal sampling sequence and completes the synchronization of all subcarrier signal sampling sequences. Compared to existing solutions that perform clock synchronization for each subcarrier signal sampling sequence separately, this embodiment of the invention does not require parallel computation of multiple subcarrier signal sampling sequences, thus requiring less circuit area, reducing circuit complexity, and reducing algorithm complexity.

[0071] Please refer to Figure 2In this invention, the analog signal received by the coherent optical receiver of the DSCM system is first sampled by an ADC (Analog-to-Digital Converter) to achieve analog-to-digital conversion, resulting in a multiplexed signal sampling sequence. The receiver IQ imbalance compensation and coarse frequency offset estimation are then performed on the multiplexed signal. Next, an interpolation filter is used to interpolate the multiplexed signal sampling sequence, which includes multiple subcarriers, based on fractional intervals and basic pointers. Subsequently, a subcarrier demultiplexer demultiplexes the interpolated multiplexed signal sampling sequence to obtain a multi-subcarrier signal sampling sequence. Subcarrier demultiplexing can employ either a time-domain algorithm or a frequency-domain algorithm. In this embodiment, the frequency-domain algorithm is used as an example. First, the multiplexed signal sampling sequence is grouped and transformed to the frequency domain using FFT (Fast Fourier Transform). Subcarrier demultiplexing is then performed in the frequency domain, resulting in a multi-channel subcarrier signal sampling sequence with dispersion compensation. A timing error detector is used to randomly select one target subcarrier sampling sequence with compensation for dispersion for timing error detection. The timing error is extracted by a loop filter and then filtered in the loop to generate a control word. A numerically controlled oscillator calculates the basic pointer and fractional interval based on the control word and converts the fractional interval. Lagrange cube polynomial interpolation is then performed on the next group of multiplexed signal sampling values ​​in the multiplexed signal sampling sequence to remove timing errors, forming a clock synchronization loop. This process is repeated cyclically to track and correct the timing frequency difference until the fractional interval forms a stable periodic change, achieving clock synchronization of each subcarrier signal sampling sequence. After obtaining the synchronous sampling sequence of each subcarrier signal sampling sequence, polarization demultiplexing and adaptive equalization, fine frequency offset estimation and phase offset compensation are performed on each subcarrier to finally recover the service information bits of each subcarrier signal sampling sequence.

[0072] The performance or effectiveness of the clock synchronization method in the digital subcarrier multiplexing system of this invention will be verified through Experiments 1 and 2 below.

[0073] Experiment 1 compares the performance of the clock synchronization method in the digital subcarrier multiplexing system of this invention with that of the existing method of synchronizing the clocks of each subcarrier separately. Experiment 1 uses a polarization-multiplexed 16-QAM-DSCM system with four subcarriers of 32 Gbaud each. Each subcarrier signal is shaped using Nyquist filtering at the transmitter with a roll-off factor of 0.1. During multiplexing, adjacent subcarriers have no overlap. The spectrum of the multiplexed signal is shown below. Figure 3As shown. In Experiment 1, the laser linewidth was 100kHz, the frequency offset was 1.5GHz, and the timing frequency difference was 50ppm. Under the condition of conventional single-mode fiber transmission over 20-40 spans (span length 80km), the simulation results using subcarrier 3 to detect the timing error show that, as Figure 4 As shown, the clock synchronization method in the digital subcarrier multiplexing system provided by this invention has a Q-value cost of less than 0.1 dB compared with the existing method of synchronizing clocks separately for each subcarrier.

[0074] Experiment 2 uses a polarization-multiplexed 16QAM-DSCM system with 8 subcarriers. Each subcarrier signal is shaped using a Nyquist filter at the transmitter with a roll-off factor of 0.1. During subcarrier multiplexing, adjacent subcarriers also have no overlap. The spectrum of the multiplexed signal is shown below. Figure 5 As shown, the symbol rate of subcarriers 1, 2, 7, and 8 is 8 Gbaud, the symbol rate of subcarriers 3 and 6 is 16 Gbaud, the symbol rate of subcarriers 4 and 5 is 32 Gbaud, and the composite symbol rate of the multiplexed signal is 128 Gbaud. In the simulation, the laser linewidth is 100 kHz, the frequency offset is 1.5 GHz, and the timing frequency difference is 50 ppm. Under the condition of conventional single-mode fiber transmission across 20-40 spans (span length 80 km), the simulation results using subcarrier 5 for timing error detection show that, as... Figure 6 As shown, the clock synchronization method in the digital subcarrier multiplexing system provided by this invention has a maximum Q-value cost of 0.1dB compared with the existing method of synchronizing clocks separately for each subcarrier.

[0075] Therefore, the clock synchronization method in the digital subcarrier multiplexing system provided by this invention only performs timing error detection and loop filtering on one of the multiple subcarriers. Thus, compared to existing schemes that perform clock synchronization on each subcarrier separately, the clock synchronization method provided by this invention has lower algorithm complexity and can reduce the circuit area required for implementing the clock synchronization DSP algorithm. Figure 7 As shown, starting from a number of subcarriers greater than or equal to 2, the clock synchronization method in the digital subcarrier multiplexing system provided by this invention has a lower algorithm complexity than the existing method of synchronizing clocks for each subcarrier separately. Furthermore, the more subcarriers there are, the more obvious the advantage of the clock synchronization method provided by this invention in terms of algorithm complexity becomes. When the number of subcarriers reaches 8, the clock synchronization method in the digital subcarrier multiplexing system provided by this invention can reduce the algorithm complexity by approximately 45%.

[0076] The clock synchronization device in the digital subcarrier multiplexing system provided by the present invention will be described below. The clock synchronization device in the digital subcarrier multiplexing system described below can be referred to in correspondence with the clock synchronization method in the digital subcarrier multiplexing system described above.

[0077] Please refer to Figure 8 A clock synchronization device in a digital subcarrier multiplexing system, comprising:

[0078] Interpolation module 201 is used to interpolate the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval;

[0079] Subcarrier demultiplexing module 202 is used to demultiplex the multiplexed signal sampling sequence to obtain a multi-subcarrier signal sampling sequence;

[0080] Dispersion compensation module 203 is used to perform dispersion compensation on the sampling sequences of the multi-subcarrier signals respectively;

[0081] Timing error detection module 204 is used to select one target subcarrier signal sampling sequence from the dispersion-compensated multi-subcarrier signal sampling sequence to perform timing error detection and obtain timing error information;

[0082] The fractional interval and basic pointer calculation module 205 is used to calculate the fractional interval and basic pointer based on the timing error information;

[0083] The fractional interval conversion module 206 is used to determine the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and to convert the fractional interval according to the conversion parameters; the conversion parameters are used to shorten the period of the fractional interval while keeping the amplitude unchanged;

[0084] The operation control module 207 is used to perform parameter control on the subcarrier demultiplexing module, the dispersion compensation module, the timing error detection module, the fractional interval and basic pointer calculation module, the fractional interval conversion module and the interpolation module.

[0085] The clock synchronization method and apparatus in a digital subcarrier multiplexing system provided by this invention, based on the characteristic that the clocks of all subcarriers in the digital subcarrier multiplexing system originate from the same source, performs timing error detection only on one target subcarrier signal in the multi-channel subcarrier signal sampling sequence, and then calculates a fractional interval and a basic pointer based on the timing error information obtained from the timing error detection; determines the conversion parameter of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and converts the fractional interval according to the conversion parameter: shortening the period of the fractional interval while keeping its amplitude unchanged; interpolating the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval, and repeating the above steps cyclically, after several feedback loops, the fractional interval changes from an initially irregular change to a stable periodic change, eliminating the timing error on the multiplexed signal sampling sequence. Thus, this embodiment of the invention corrects timing errors on the multiplexed signal sampling sequence and completes the synchronization of all subcarrier signal sampling sequences. Compared to existing solutions that perform clock synchronization for each subcarrier signal sampling sequence separately, the embodiments of the present invention do not require parallel processing of multiple subcarrier signal sampling sequences, thus requiring a smaller circuit area, reducing circuit complexity, and reducing algorithm complexity.

[0086] In one embodiment, determining the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and converting the fractional interval according to the conversion parameters, includes:

[0087] The conversion parameters of the fractional interval are determined based on the sum of the symbol rates of the sampling sequences of each subcarrier signal and the symbol rate of the sampling sequence of the target subcarrier signal, and the fractional interval is converted according to the conversion parameters.

[0088] In one embodiment, the conversion parameter for determining the fractional interval based on the sum of the symbol rates of each of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence is calculated using the following formula:

[0089]

[0090] Where M represents the transformation parameter, R SCi R represents the symbol rate of the subcarrier signal sampling sequence i. SC_TED R represents the symbol rate of the target subcarrier signal sampling sequence. SC1 +R SC2 +…+R SCi The sum of the symbol rates based on the sampling sequences of each subcarrier signal is used to determine M. After that, the fractional interval period is shortened by a factor of M while keeping the amplitude unchanged.

[0091] In one embodiment, the fractional interval and basic pointer calculation module includes:

[0092] The control word acquisition module is used to filter the timing error information to output the control word;

[0093] The fraction interval and basic pointer acquisition module is used to calculate the fraction interval and basic pointer based on the control word.

[0094] In one embodiment, the interpolation module is specifically used to perform polynomial interpolation on the multiplexed signal sampling sequence using Lagrange interpolation or linear interpolation based on the basic pointer and the converted fractional interval, in order to correct the timing error on the multiplexed signal sampling sequence.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus the necessary hardware platform, or of course by hardware.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock synchronization method in a digital subcarrier multiplexing system, characterized in that, include: Interpolation is performed on the multiplexed signal sampling sequence, which includes multiple subcarriers, based on fractional intervals and basic pointers; The multiplexed signal sampling sequence is demultiplexed with subcarriers to obtain a multi-subcarrier signal sampling sequence; Dispersion compensation is performed on the sampling sequences of the multi-subcarrier signals respectively; Select one target subcarrier signal sampling sequence from the dispersion-compensated multi-subcarrier signal sampling sequence for timing error detection to obtain timing error information; Calculate the fractional interval and basic pointer based on the timing error information; The conversion parameters of the fractional interval are determined based on the symbol rate of each of the subcarrier signal sampling sequences, and the fractional interval is converted according to the conversion parameters; the conversion parameters are used to shorten the period of the fractional interval while keeping the amplitude unchanged; Based on the basic pointer and the converted fractional interval, the multiplexed signal sampling sequence is interpolated, thus completing one feedback loop. After several feedback loops, the timing error of the multiplexed signal sampling sequence is eliminated. The step of determining the conversion parameters of the fractional interval based on the symbol rate of each of the subcarrier signal sampling sequences, and converting the fractional interval according to the conversion parameters, includes: The conversion parameters of the fractional interval are determined based on the sum of the symbol rates of each of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence, and the fractional interval is converted according to the conversion parameters. The conversion parameters are determined by the following formula: Where M represents the transformation parameter, R SCi R represents the symbol rate of the subcarrier signal sampling sequence i. SC_TED R represents the symbol rate of the target subcarrier signal sampling sequence. SC1 +R SC2 +…+R SCi The sum of the symbol rates based on the sampling sequences of each subcarrier signal is used to determine M. After that, the period of the fractional interval is shortened by a factor of M while keeping its amplitude unchanged.

2. The clock synchronization method in a digital subcarrier multiplexing system according to claim 1, characterized in that, The calculation of the fractional interval and basic pointer based on the timing error information includes: The timing error information is filtered to output a control word; The fractional interval and basic pointer are calculated based on the control word.

3. The clock synchronization method in a digital subcarrier multiplexing system according to claim 1, characterized in that, The interpolation of the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval includes: Based on the basic pointer and the converted fractional interval, polynomial interpolation is performed on the multiplexed signal sampling sequence using Lagrange interpolation or linear interpolation to correct timing errors on the multiplexed signal sampling sequence.

4. A clock synchronization device in a digital subcarrier multiplexing system, characterized in that, include: The interpolation module is used to interpolate the multiplexed signal sampling sequence based on the basic pointer and the converted fractional interval; A subcarrier demultiplexing module is used to demultiplex the multiplexed signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence. A dispersion compensation module is used to perform dispersion compensation on the multi-subcarrier signal sampling sequence; The timing error detection module is used to select one target subcarrier signal sampling sequence from the dispersion-compensated multi-subcarrier signal sampling sequence for timing error detection, and obtain timing error information. A fractional interval and basic pointer calculation module is used to calculate the fractional interval and basic pointer based on the timing error information; A fractional interval conversion module is used to determine the conversion parameters of the fractional interval based on the symbol rate of each subcarrier signal sampling sequence, and to convert the fractional interval according to the conversion parameters; the conversion parameters are used to shorten the period of the fractional interval while keeping its amplitude unchanged; The operation control module is used to control the parameters of the subcarrier demultiplexing module, the dispersion compensation module, the timing error detection module, the fractional interval and basic pointer calculation module, the fractional interval conversion module and the interpolation module; The fraction interval conversion module is specifically used for: The conversion parameters of the fractional interval are determined based on the sum of the symbol rates of each of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence, and the fractional interval is converted according to the conversion parameters. The conversion parameters are determined by the following formula: Where M represents the transformation parameter, R SCi R represents the symbol rate of the subcarrier signal sampling sequence i. SC_TED R represents the symbol rate of the target subcarrier signal sampling sequence. SC1 +R SC2 +…+R SCi The sum of the symbol rates based on the sampling sequences of each subcarrier signal is used to determine M. After that, the period of the fractional interval is shortened by a factor of M while keeping its amplitude unchanged.

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