Method for manufacturing a flash memory
By using a layered method to form sidewalls, the problem of performance degradation of peripheral devices caused by the shrinkage of memory cells in flash memory manufacturing is solved. This method improves the integration of memory cells and the performance of peripheral devices, reduces leakage current, and increases breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-10
- Publication Date
- 2026-03-20
AI Technical Summary
In existing flash memory manufacturing methods, as memory cells shrink, the reduced sidewall width of the memory cells leads to a decline in the performance of peripheral devices, including increased leakage current and reduced breakdown voltage, and voids are more likely to appear in the interlayer film.
By employing a layered sidewall formation method, first and second gate structures of different thicknesses are formed in the memory cell and peripheral device areas, respectively. The sidewall thickness is adjusted using photomask technology to ensure that the sidewalls in the memory cell area are thin while those in the peripheral device area are thick, thereby increasing the process window.
It achieves proportional reduction and increased integration of memory cells, while improving the performance of peripheral devices, reducing leakage current and increasing breakdown voltage, and avoiding interlayer film voids.
Smart Images
Figure CN115884597B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor integrated circuit manufacturing method, and more particularly to a flash memory manufacturing method. BACKGROUND
[0002] In the prior art, the SPACER of the Cell and the peripheral device are formed simultaneously. When the technology node is 0.13 μm to 65 nm / 55 nm, the Cell size is large enough, and the performance of the Cell and the peripheral device is not affected. However, when the Cell continues to shrink, the thickness of the SPACER required to ensure the performance of the peripheral device, the Cell may have a void in the ILD due to the small space, which eventually causes the disturbance between the CT and the CG or between the Cells; if the Cell space is maintained, the thickness of the SPACER needs to be reduced, which makes the SPACER of the peripheral device too thin, resulting in a large Ioff and a small BVDS of the peripheral device, or the resistance of the SAB after the formation of the Salicide is small due to the insufficient protection of the SPACER.
[0003] As shown in FIG. 1, it is a flow chart of the prior art flash memory manufacturing method; the prior art flash memory manufacturing method comprises the following steps: Figure 1
[0004] Step S101, Cell AA. AA represents an active region, which is usually defined by forming a shallow trench isolation.
[0005] Step S102, peripheral AA. Peripheral represents a peripheral device.
[0006] Step S103, peripheral & Cell Well, i.e. well implantation in the storage cell region and the peripheral device region.
[0007] Step S104, Cell Vt. Vt represents threshold voltage, threshold voltage adjustment implantation of the storage cell is performed.
[0008] Step S105, TunOX; TunOX represents a tunneling oxide layer.
[0009] Step S106, FG; FG represents a floating gate.
[0010] Step S107, ONO; ONO layer represents a stack of an oxide layer, a nitride layer and an oxide layer.
[0011] Step S108, CG; CG means control gate. The gate structure of the memory cell is formed by the stack of TunOX, FG, ONO and CG.
[0012] Step S109, Peripheral GT; GT means gate, i.e. the gate structure of the peripheral device is formed.
[0013] Step S110, Peripheral & Cell LDD. It means that the LDD (Lightly Doped Drain) implant is performed to form the LDD region of the memory cell and the LDD region of the peripheral device.
[0014] Step S111, SPA1 OX DEP. SPA1 means the first layer of side wall, SPA1 OX means the oxide layer constituting the first layer of side wall, and DEP means deposition process.
[0015] Step S112, SPA1 OX ETCH, ETCH means etching. It means that the self-aligned etching is performed to form the first layer of side wall self-aligned to the side surface of each gate structure.
[0016] Step S113, SPA2 SIN DEP. SPA2 means the second layer of side wall, and SPA2 SIN means the silicon nitride constituting the second layer of side wall.
[0017] Step S114, SPA2 SIN ETCH, ETCH means etching. It means that the self-aligned etching is performed to form the second layer of side wall self-aligned to the side surface of each gate structure.
[0018] Step S115, Cell S / D; S / D means the implantation of source region and drain region, i.e. the source / drain implantation of the memory cell.
[0019] Step S116, N+P+S / D; N+ means the N-type heavy doping of the peripheral NMOS, P+ means the P-type heavy doping of the peripheral PMOS, and S / D means the source / drain implantation.
[0020] Step S117, SAB. SAB means the metal silicide barrier layer.
[0021] Step S118, CT. CT means the contact hole, which will pass through the interlayer film. Therefore, the first layer of interlayer film needs to be formed before CT.
[0022] Step S119, BEOL. BEOL means the back-end-of-line process, which includes the formation process of the subsequent interlayer films and the front metal layer after CT. SUMMARY
[0023] The technical problem solved by the present application is to provide a flash memory manufacturing method, which can reduce the width of the sidewall of the memory cell and increase the width of the sidewall of the peripheral device at the same time, so as to increase the process window of the sidewall of the memory cell and the sidewall of the peripheral device at the same time, thereby facilitating the equal scaling of the memory cell and improving the integration of the memory cell area, and also improving the performance of the peripheral device, such as reducing the leakage of the peripheral device and increasing the breakdown voltage and reliability of the peripheral device.
[0024] To solve the above technical problem, the flash memory manufacturing method provided by the present application comprises the following steps:
[0025] Step one, providing a semiconductor substrate, which comprises a memory cell area of a flash memory and a peripheral device area at the same time.
[0026] Step two, forming a first gate structure of the memory cell in the memory cell area.
[0027] Step three, forming a second gate structure of the peripheral device in the peripheral device area.
[0028] The width of the first gate structure is smaller than the width of the second gate structure, the interval between the first gate structures is smaller than the interval between the second gate structures, and the withstand voltage of the second gate structure is greater than the withstand voltage of the first gate structure.
[0029] Step four, forming a first layer of sidewall, comprising the following sub-steps:
[0030] Step 41, forming a first sidewall material layer, which covers the side and top surface of the first gate structure, the side and top surface of the second gate structure, and the external surface of the first gate structure and the second gate structure.
[0031] Step 42, forming a second sidewall material layer on the surface of the first sidewall material layer.
[0032] Step 43, performing overall anisotropic etching on the second sidewall material layer to form a second sub-sidewall composed of the remaining second sidewall material layer on the side of the first gate structure and the side of the second gate structure, and the second sidewall material layer on the top surface of the first gate structure, the top surface of the second gate structure, and the external surface of the first gate structure and the second gate structure is removed.
[0033] Step 44, photoetching to open the memory cell area and cover the peripheral device area, and etching the second sidewall material layer to remove each second sub-sidewall in the memory cell area.
[0034] The first sub-side wall is composed of the first side wall material layer located at the side of the first gate structure and the side of the second gate structure.
[0035] The first layer side wall of the first gate structure is composed of the first sub-side wall at the side of the first gate structure.
[0036] The first layer side wall of the second gate structure is composed of the first sub-side wall and the second sub-side wall at the side of the second gate structure.
[0037] Step five, a second layer side wall is formed by a deposition and etching process of a third side wall material layer at the side of the first layer side wall of each first gate structure and the side of the first layer side wall of each second gate structure.
[0038] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0039] A further improvement is that the material of the first side wall material layer comprises an oxide layer.
[0040] A further improvement is that the material of the second side wall material layer comprises silicon nitride.
[0041] A further improvement is that the material of the third side wall material layer comprises an oxide layer.
[0042] A further improvement is that the thickness of the first side wall material layer is 100-2000 angstroms.
[0043] The thickness of the second side wall material layer is 100-2000 angstroms.
[0044] A further improvement is that in step two, the first gate structure comprises a first tunneling dielectric layer, a second polysilicon floating gate, a third control dielectric layer and a fourth polysilicon control gate which are stacked in sequence.
[0045] In step three, the second gate structure comprises a first gate dielectric layer and a second polysilicon gate which are stacked in sequence.
[0046] A further improvement is that the first tunneling dielectric layer is an oxide layer, the third control dielectric layer is an ONO layer, and the ONO layer is a stack of an oxide layer, a nitride layer and an oxide layer.
[0047] The material of the first gate dielectric layer is an oxide layer.
[0048] A further improvement is that before step four, a LDD implantation is performed to form a LDD region of the memory cell at the side of the first gate structure and a LDD region of the peripheral device at the side of the second gate structure.
[0049] A further improvement is that after etching the second layer of sidewall material in step 44, further comprising:
[0050] performing a first source / drain implant to form source / drain regions of the memory cells self-aligned to the first layer of sidewall of the first gate structure.
[0051] A further improvement is that after step five is completed, further comprising:
[0052] performing a second source / drain implant to form source / drain regions of the peripheral devices self-aligned to the second layer of sidewall of the second gate structure.
[0053] A further improvement is that in step one, further comprising the step of:
[0054] forming shallow trench isolation to define active areas in the memory cell region and the peripheral device region;
[0055] performing well implant in the memory cell region and the peripheral device region;
[0056] performing threshold voltage adjustment implant for the memory cells.
[0057] A further improvement is that after forming source / drain regions of the peripheral devices, further comprising:
[0058] forming metal silicide blocking layer and self-aligned metal silicide;
[0059] forming interlayer dielectric, contact hole and front metal layer and patterning the front metal layer.
[0060] A further improvement is that the flash memory is a NOR flash memory.
[0061] A further improvement is that the first layer of sidewall of the first gate structure has a thickness to ensure that the width of the space between the first gate structures is increased and to satisfy that there is no void when the space between the first gate structures is filled with the interlayer dielectric.
[0062] The present application divides the material layer forming the first layer side wall into two layers, i.e. the first side wall material layer and the second side wall material layer, the second side wall material layer forms the second sub side wall, and the first side wall material layer forms the first sub side wall. However, in the present application, after the full anisotropic etching of the second side wall material layer and the self-aligned formation of the second sub side wall, a mask process is added to remove the second sub side wall in the memory cell area by mask definition. Thus, the first layer side wall of the first gate structure of the memory cell is composed of the first sub side wall, and the first layer side wall of the peripheral device is composed of the first sub side wall and the second sub side wall. Compared with the prior art, the present application can reduce the width of the side wall of the memory cell and simultaneously increase the width of the side wall of the peripheral device, so as to simultaneously increase the process window of the side wall of the memory cell and the side wall of the peripheral device, i.e. the side wall of the memory cell can be set according to the requirement of thinner thickness, and the side wall of the peripheral device can be set according to the requirement of thicker thickness. The thinner thickness of the side wall of the memory cell is beneficial to the equal proportion reduction of the memory cell and the increase of the integration of the memory cell area, and the thicker side wall of the peripheral device can simultaneously improve the performance of the peripheral device, such as reducing the leakage of the peripheral device and increasing the breakdown voltage and reliability of the peripheral device. BRIEF DESCRIPTION OF DRAWINGS
[0063] The present application will be further described in detail below in combination with the drawings and specific embodiments:
[0064] Figure 1 is a flow chart of the manufacturing method of the prior flash memory;
[0065] Figure 2 is a flow chart of the manufacturing method of the flash memory of the embodiment of the present application;
[0066] Figure 3 is a flow chart of the manufacturing method of the flash memory of the preferred embodiment of the present application;
[0067] Figure 4A is a SAB resistance (RS) test chart of the P+ polysilicon of the peripheral device formed by the manufacturing method of the prior flash memory;
[0068] Figure 4B is a SAB RS test chart of the P+ polysilicon of the peripheral device formed by the manufacturing method of the preferred embodiment of the present application;
[0069] Figure 5 is a leakage current test chart of the peripheral device formed by the manufacturing method of the prior and the preferred embodiment of the present application;
[0070] Figure 6 is a breakdown voltage (BVDS) test chart of the peripheral device formed by the manufacturing method of the prior and the preferred embodiment of the present application. DETAILED DESCRIPTION
[0071] As Figure 2 shown in FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present application; as Figure 3 shown in FIG. 2 is a flow chart of a method for manufacturing a flash memory according to a preferred embodiment of the present application; the method for manufacturing a flash memory according to an embodiment of the present application comprises the following steps:
[0072] Step 1, providing a semiconductor substrate, which comprises a memory cell region of a flash memory and a peripheral device region.
[0073] In the embodiment of the present application, the semiconductor substrate comprises a silicon substrate.
[0074] In some preferred embodiments, the flash memory is a NOR flash memory. Step 1 further comprises the following steps:
[0075] forming a shallow trench isolation to define an active region in the memory cell region and the peripheral device region. This step corresponds to step S201, Cell AA; step S202, Peripheral AA in Figure 3 FIG. 1. Cell represents a device cell, and AA represents an active region. Peripheral represents the peripheral device.
[0076] performing a well implantation in the memory cell region and the peripheral device region. This step corresponds to step S203, Peripheral & Cell Well in Figure 3 FIG. 1.
[0077] performing a threshold voltage adjustment implantation for the memory cell. This step corresponds to step S204, Cell Vt in Figure 3 FIG. 1. Vt represents a threshold voltage.
[0078] Step 2, forming a first gate structure of a memory cell in the memory cell region.
[0079] In some embodiments, the first gate structure comprises a first tunneling dielectric layer, a second polysilicon floating gate, a third control dielectric layer and a fourth polysilicon control gate, which are sequentially stacked.
[0080] In some preferred embodiments, the first tunneling dielectric layer is an oxide layer, and the third control dielectric layer is an ONO layer, which is a stack of an oxide layer, a nitride layer and an oxide layer. Figure 3 In FIG. 1, the step of forming the first gate structure comprises:
[0081] Step S205, TunOX; TunOX represents a tunneling oxide layer, i.e. forming the first tunneling dielectric layer.
[0082] Step S206, FG; FG represents a floating gate, i.e. forming the second polysilicon floating gate.
[0083] Step S207, ONO; ONO means forming the third control medium layer composed of an ONO layer.
[0084] Step S208, CG; CG means control gate, i.e. forming the fourth polysilicon control gate.
[0085] Step three, forming a second gate structure of the peripheral device in the peripheral device area.
[0086] The width of the first gate structure is smaller than the width of the second gate structure, the interval between the first gate structures is smaller than the interval between the second gate structures, and the withstand voltage of the second gate structure is greater than the withstand voltage of the first gate structure.
[0087] In the embodiment of the present application, the second gate structure comprises a first gate medium layer and a second polysilicon gate which are stacked in sequence.
[0088] In some preferred embodiments, the material of the first gate medium layer adopts an oxide layer.
[0089] Figure 3 In some preferred embodiments, the step of forming the second gate structure comprises:
[0090] Step S209, peripheral GT; GT means gate, i.e. the second gate structure.
[0091] In some preferred embodiments, before the subsequent step four, it further comprises performing LDD injection to form an LDD area of the memory cell self-aligned to the side of the first gate structure and an LDD area of the peripheral device self-aligned to the side of the second gate structure. This step corresponds to Figure 3 Step S210, peripheral & Cell LDD, in the step S210 of
[0092] Step four, forming a first layer of side wall, comprising the following sub-steps:
[0093] Step 41, forming a first side wall material layer, which covers the side and top surface of the first gate structure and the side and top surface of the second gate structure and the outer surface of the first gate structure and the second gate structure.
[0094] In some preferred embodiments, the material of the first side wall material layer comprises an oxide layer.
[0095] The thickness of the first side wall material layer is
[0096] Step 42, forming a second side wall material layer on the surface of the first side wall material layer.
[0097] In some preferred embodiments, the material of the second spacer material layer comprises silicon nitride.
[0098] The thickness of the second spacer material layer is
[0099] Figure 3 In some preferred embodiments, steps 41 and 42 correspond to steps S211, SPAl OX / SIN DEP; SPAl denotes the first layer of spacers, SPAl OX denotes the first spacer material layer, SPAl SIN denotes the second spacer material layer, and DEP denotes a deposition process to form SPAl OX / SIN.
[0100] Step 43, performing a full anisotropic etch of the second spacer material layer to form second sub-spacers consisting of the remaining second spacer material layer on the sides of the first gate structure and the sides of the second gate structure, the top surface of the first gate structure, the top surface of the second gate structure, and the second spacer material layer on the outer surfaces of the first gate structure and the second gate structure are removed.
[0101] In some preferred embodiments, step 43 corresponds to Figure 3 Step S212, SPAl SIN ETCH, in some preferred embodiments. ETCH denotes an etch
[0102] Step 44, performing a photolithography to open the memory cell region and cover the peripheral device region, and etching the second spacer material layer to remove each of the second sub-spacers in the memory cell region.
[0103] In some preferred embodiments, step 44 corresponds to Figure 3 Step S212a, Cell SPAl PH / ET, in some preferred embodiments. PH denotes a photolithography process, and ET denotes an etch.
[0104] The first sub-spacers consist of the first spacer material layer on the sides of the first gate structure and the sides of the second gate structure.
[0105] The first layer of spacers of the first gate structure consists of the first sub-spacers on the sides of the first gate structure.
[0106] The first layer of spacers of the second gate structure consists of the first sub-spacers and the second sub-spacers on the sides of the second gate structure.
[0107] In some preferred embodiments, after etching the second spacer material layer in step 44, further comprising:
[0108] A first source / drain implant is performed to form source / drain regions of the memory cells self-aligned to the first layer of sidewall of the first gate structure. This step corresponds to Figure 3 Step S213, Cell S / D Dose Tune, in FIG. 4A. S / D stands for source / drain implant, i.e. the first source / drain implant, Dose stands for implant dose, and Tune stands for tuning. As can be seen, the first source / drain implant is defined by the lithography process in step 44, which has already been completed. Therefore, the lithography process in step 44 of the embodiment of the present application does not increase the cost of the whole process.
[0109] Step five, a second layer of sidewall is formed self-aligned to the first layer of sidewall of each of the first gate structure and the first layer of sidewall of each of the second gate structure by a deposition and etching process of a third layer of sidewall material.
[0110] In some preferred embodiments, the material of the third layer of sidewall material includes an oxide layer. Figure 3 Step five corresponds to:
[0111] Step S214, SPA2 OX DEP. SPA2 stands for the second layer of sidewall, and SPA2 OX stands for the third layer of sidewall material composed of an oxide layer.
[0112] Step S215, SPA2 OX ETCH.
[0113] After step five, it further includes:
[0114] A second source / drain implant is performed to form source / drain regions of the peripheral devices self-aligned to the second layer of sidewall of the second gate structure. This step corresponds to Figure 3 Step S216, N+P+S / D, in FIG. 4A. N+ stands for N-type heavy doping of the peripheral NMOS, P+ stands for P-type heavy doping of the peripheral PMOS, and S / D stands for source / drain implant, i.e. the second source / drain implant.
[0115] A metal silicide barrier layer is formed and self-aligned to form a metal silicide. This step corresponds to Figure 3 Step S217, SAB, in FIG. 4A. SAB stands for the metal silicide barrier layer.
[0116] An interlayer dielectric film is formed and a contact hole is formed. This step corresponds to Figure 3 Step S218, CT, in FIG. 4A. CT stands for the contact hole, which passes through the interlayer dielectric film. The thickness of the first layer of sidewall of the first gate structure formed in the foregoing ensures that the width of the spacing region between the first gate structures is increased and meets the requirement that there is no void when the spacing region between the first gate structures is filled with the interlayer dielectric film.
[0117] Continuously form the interlayer dielectric film and the front metal layer of each subsequent layer and pattern the front metal layer. This step corresponds to Figure 3 S219 in FIG. 19B, BEOL. BEOL means back end of line.
[0118] The embodiment of the present application divides the material layer for forming the first layer of side wall into two layers, i.e. the first side wall material layer and the second side wall material layer, and the second side wall material layer forms the second sub side wall and the first side wall material layer forms the first sub side wall. However, in the embodiment of the present application, after the full anisotropic etching of the second side wall material layer and the self-aligned formation of the second sub side wall are completed, a photomask process is added to remove the second sub side wall in the memory cell region by photomask definition. In this way, the first layer of side wall of the first gate structure of the memory cell is composed of the first sub side wall, while the first layer of side wall of the peripheral device is composed of the superposition of the first sub side wall and the second sub side wall. Compared with the prior art, the embodiment of the present application can reduce the width of the side wall of the memory cell and simultaneously increase the width of the side wall of the peripheral device, so as to simultaneously increase the process window of the side wall of the memory cell and the side wall of the peripheral device, i.e. the side wall of the memory cell can be set according to the requirement of thinner thickness and the side wall of the peripheral device can be set according to the requirement of thicker thickness. The thinner thickness of the side wall of the memory cell is beneficial to the equal proportion reduction of the memory cell and the increase of the integration of the memory cell region, while the thicker side wall of the peripheral device can simultaneously improve the performance of the peripheral device, such as reducing the leakage of the peripheral device and increasing the breakdown voltage and reliability of the peripheral device.
[0119] In addition, the photomask definition for removing the second sub side wall in the memory cell region can be used between the source and drain implantation of the memory cell, so from the whole process flow, the present application does not increase the cost of photomask.
[0120] In the embodiment of the present application, after the conventional Cell and peripheral AA process, the Well ion implantation process of Cell and peripheral is performed, then the Cell related process such as Cell VT adjustment, Tunnel Oxide, FG, ONO, CG is performed, the Gate process of the peripheral is performed, and then the LDD ion implantation process of the peripheral and Cell is performed.
[0121] Then, the improved process related to the side wall is performed: the first layer of side wall (SPACER1) is replaced by Oxide and SIN film deposition (Film Deposition) and SIN etching (Etch), and then the Cell opening mask (Open Mask) is used for photoetching (Photo) and Etch to remove part of the SPACER1 SIN to make the Cell space open enough.
[0122] After that, adjust Cell S / D ion implantation to Cell SPA1, i.e. SPACER1 Etch, and dose adjustment, then second layer side wall (SPACER2) Oxide Dep and Etch
[0123] Finally, peripheral S / D ion implantation and SAB, CT process and BEOL metal routing process are performed.
[0124] The method of the embodiment of the present application can improve the NOR Flash product shrink cell process, and can provide other memory products with balanced structure between cell and periphery when developing to small technology node process. The embodiment of the present application improves the balance of NOR Flash cell and peripheral SPACER protection process at 50 nm and below technology node by optimizing and changing SPACER, i.e. side wall process, and adjusting the position of Cell S / D ion implantation process, which can make the cell have space process window without causing the performance loss of peripheral device. In the embodiment of the present application, when the cell space is sufficient, there is no ILD void causing CT to CG short or adjacent cell disturb.
[0125] Implementation effect:
[0126] As shown in FIG. 1, it is a SAB RS test diagram of P+ polysilicon of a peripheral device formed by a manufacturing method of a prior art flash memory; as shown in FIG. 2, it is a SAB RS test diagram of P+ polysilicon of a peripheral device formed by a manufacturing method of a flash memory of a preferred embodiment of the present application; as can be seen from FIG. 1 and FIG. 2, Figure 3 Figure 4A Full Mapping Poly SAB RS is normal and stable in distribution, and Full Mapping represents a test diagram; and Figure 4B Figure 4B the baseline (Baseline) process W / E RS of the prior art manufacturing method only has 1 / 4 of normal.
[0127] As shown in FIG. 3, it is a SAB RS test diagram of P+ polysilicon of a peripheral device formed by a manufacturing method of a prior art flash memory; as shown in FIG. 4, it is a SAB RS test diagram of P+ polysilicon of a peripheral device formed by a manufacturing method of a flash memory of a preferred embodiment of the present application; as can be seen from FIG. 3 and FIG. 4, Figure 4A The diagram shows a test graph of the leakage current of peripheral devices formed by the manufacturing methods of existing flash memory and the preferred embodiment of the present invention. The higher leakage current corresponding to mark 101 is the leakage current of peripheral devices formed by the existing flash memory manufacturing method, and the lower leakage current corresponding to mark 102 is the leakage current of peripheral devices formed by the manufacturing method of flash memory in the preferred embodiment of the present invention. Therefore, the leakage current of peripheral devices formed by the manufacturing method of flash memory in the preferred embodiment of the present invention will be reduced. For example, the leakage current of peripheral Device Ioff@11V in the preferred embodiment of the present invention is reduced to <1nA / μm, while the leakage current baseline of peripheral devices in the existing method is >3nA / μm.
[0128] like Figure 5 Figure 6 The diagram shows test values for the breakdown voltage of peripheral devices formed by conventional flash memory manufacturing methods and those of the preferred embodiment of the present invention. Marker 103 corresponds to the breakdown voltage test value of peripheral devices formed by conventional flash memory manufacturing methods, and mark 104 corresponds to the breakdown voltage test value of peripheral devices formed by the preferred embodiment of the present invention. Therefore, the breakdown voltage test value of peripheral devices formed by the preferred embodiment of the present invention will be improved, such as an increase in BVDS of approximately 0.7V.
[0129] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing flash memory, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate, wherein the semiconductor substrate includes both a flash memory cell area and a peripheral device area; Step 2: Form the first gate structure of the memory cell in the memory cell region; Step 3: Form the second gate structure of the peripheral device in the peripheral device region; The width of the first gate structure is smaller than the width of the second gate structure, the spacing between the first gate structures is smaller than the spacing between the second gate structures, and the withstand voltage of the second gate structure is greater than the withstand voltage of the first gate structure. Step 4: Forming the first layer of sidewalls, including the following sub-steps: Step 41: Form a first sidewall material layer, which covers the side and top surfaces of the first gate structure, the side and top surfaces of the second gate structure, and the outer surfaces of the first gate structure and the second gate structure. Step 42: Form a second sidewall material layer on the surface of the first sidewall material layer; Step 43: Perform comprehensive anisotropic etching on the second sidewall material layer to form a second sub-sidewall composed of the remaining second sidewall material layer on the sidewall of the first gate structure and the sidewall of the second gate structure. The second sidewall material layer on the top surface of the first gate structure, the top surface of the second gate structure, and the outer surfaces of the first gate structure and the second gate structure are removed. Step 44: Photolithography is used to open the memory cell area and the area covering the peripheral device, and the second sidewall material layer is etched to remove each of the second sub-sidewalls in the memory cell area; The first sub-sidewall is composed of a first sidewall material layer located on the side of the first gate structure and the side of the second gate structure; The first sidewall of the first gate structure is composed of the first sub-sidewall on the side of the first gate structure; The first sidewall of the second gate structure is formed by superimposing the first sub-sidewall and the second sub-sidewall on the side of the second gate structure. Step 5: Using a deposition and etching process of a third sidewall material layer, a second sidewall is formed by self-alignment on the sidewall of the first sidewall on the side of each first gate structure and the sidewall of the first sidewall on the side of each second gate structure.
2. The method for manufacturing flash memory as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.
3. The method for manufacturing flash memory as described in claim 2, characterized in that: The material of the first sidewall material layer includes an oxide layer.
4. The method for manufacturing flash memory as described in claim 3, characterized in that: The material of the second sidewall material layer includes silicon nitride.
5. The method for manufacturing flash memory as described in claim 3, characterized in that: The material of the third sidewall layer includes an oxide layer.
6. The method for manufacturing flash memory as described in claim 4, characterized in that: The thickness of the first sidewall material layer is The thickness of the second sidewall material layer is 7. The method for manufacturing flash memory as described in claim 1, characterized in that: In step two, the first gate structure includes a first tunneling dielectric layer, a second polysilicon floating gate, a third control dielectric layer, and a fourth polysilicon control gate stacked sequentially. In step three, the second gate structure includes a first gate dielectric layer and a second polysilicon gate stacked sequentially.
8. The method for manufacturing flash memory as described in claim 7, characterized in that: The first tunneling dielectric layer is an oxide layer, and the third control dielectric layer is an ONO layer, wherein the ONO layer is a superposition layer of an oxide layer, a nitride layer and an oxide layer; The first gate dielectric layer is made of an oxide layer.
9. The method for manufacturing flash memory as described in claim 1, characterized in that: Prior to step four, the process includes performing LDD implantation to form the LDD region of the memory cell by self-alignment on the side of the first gate structure and to form the LDD region of the peripheral device by self-alignment on the side of the second gate structure.
10. The method for manufacturing flash memory as described in claim 9, characterized in that: After etching the second sidewall material layer in step 44, the process further includes: A first source-drain injection is performed to form the source-drain region of the memory cell that is self-aligned with the sidewall of the first layer of the first gate structure.
11. The method for manufacturing flash memory as described in claim 10, characterized in that: After step five is completed, the following also includes: A second source / drain injection is performed to form the source / drain region of the peripheral device that is self-aligned with the sidewall of the second layer of the second gate structure.
12. The method for manufacturing flash memory as described in claim 11, characterized in that: Step one also includes the following steps: Shallow trench isolation is formed to define active regions in the memory cell region and the peripheral device region; Well injection is performed in the memory cell area and the peripheral device area; Threshold voltage adjustment injection is performed on the memory cell.
13. The method for manufacturing flash memory as described in claim 11, characterized in that: After forming the source / drain regions of the peripheral devices, the method further includes: A metal silicide barrier layer is formed and self-aligned to form metal silicide; An interlayer film, contact holes, and a front metal layer are formed, and the front metal layer is patterned.
14. The method for manufacturing flash memory as described in claim 13, characterized in that: The flash memory is NOR flash memory.
15. The method for manufacturing flash memory as described in claim 13, characterized in that: The thickness of the first sidewall of the first gate structure ensures that the width of the gap region between the first gate structures is increased and that there are no voids when the interlayer film is filled in the gap region between the first gate structures.
Citation Information
Patent Citations
Flash memory manufacturing method
CN105097702A
Method for increasing floating gate flash memory side wall width and floating grid type flash memory structure
CN107994025A