A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The substrate has a plurality of first through holes. The first surface of the first through hole is located at the lower surface of the substrate and is used for connecting the first metal layer. The second surface of the through hole is located at the upper surface of the substrate. The device comprises: a first dielectric layer covering the upper surface of the substrate; a vertical hole corresponding to the first through hole in the first dielectric layer and being perpendicular to the second surface of the first through hole; a bottom electrode covering the bottom and the sidewall of the vertical hole; a resistance change layer covering the bottom electrode of the vertical hole and covering the upper surface of the first dielectric layer; an oxygen capturing layer filling the vertical hole and covering the resistance change layer; and a top electrode covering the oxygen capturing layer. The size of the resistance change structure can be adjusted by adjusting the depth of the vertical hole.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Among existing technologies, resistive random access memory (RRAM) is one of the most promising next-generation non-volatile memories. Compared with traditional floating gate flash memory, it has significant advantages in terms of device structure, speed, scalability, and three-dimensional integration potential.

[0003] The basic structure of a Resistive Random Access Array (RRAM) is a metal-insulator-metal (MIM) structure, mainly consisting of a bottom electrode, a resistive switching layer, and a top electrode. The resistive switching layer is made of various oxide thin film materials and can reversibly switch between different resistance states under the influence of applied voltage, current, or other electrical signals. This reversible switching is mostly achieved through the formation and breakage of conductive filaments.

[0004] Currently, the manufacturing method of MIM structures involves sequentially depositing all thin films and then etching them with a photomask to obtain a resistive switching structure (R). The size of the resistive switching structure is defined by the photomask, which has significant limitations. Summary of the Invention

[0005] The present invention provides a semiconductor device and a method for manufacturing the same, in order to at least solve the above-mentioned technical problems.

[0006] A first aspect of the present invention provides a method for manufacturing a semiconductor device, wherein a substrate has a plurality of first through-holes, a first surface of the first through-holes being located on the lower surface of the substrate for connecting a first metal layer, and a second surface of the first through-holes being located on the upper surface of the substrate, the method comprising: A first dielectric layer is deposited on the upper surface of the substrate, and the first dielectric layer is etched to form vertical holes in the first dielectric layer that correspond one-to-one with the first vias. The vertical holes are perpendicular to the second surface of the first vias. A bottom electrode layer is deposited, which covers the upper surface of the first dielectric layer and the bottom and sidewalls of the vertical hole; The vertical holes are filled with organic material and then flattened. An organic layer and a silicon-oxygen dielectric layer are deposited sequentially, and the silicon-oxygen dielectric layer, organic layer and bottom electrode layer are etched sequentially to remove the bottom electrode layer outside the vertical hole, thereby obtaining the bottom electrode in the vertical hole; A resistive switching layer is deposited such that the resistive switching layer covers the upper surface of the first dielectric layer and conformally covers the bottom electrode of the vertical hole; Deposit an oxygen-binding layer to cover the upper surface of the resistive switching layer and fill the vertical pores; A top electrode layer is deposited on the oxygen-binding layer; The top electrode layer, the oxygen-binding layer, and the resistive switching layer are etched to disconnect the resistive switching layer, the oxygen-binding layer, and the top electrode between two adjacent vertical holes.

[0007] Before depositing a dielectric layer on the upper surface of the substrate, the method further includes: An etching stop layer is deposited on the upper surface of the substrate; Accordingly, the first dielectric layer is deposited on the etch stop layer.

[0008] The method further includes etching the dielectric layer and the etch stop layer to obtain the vertical hole.

[0009] In this design, the resistive switching layer, oxygen-binding layer, and top electrode between each pair of adjacent vertical holes are disconnected.

[0010] In the array of vertical holes, the top electrodes of two adjacent vertical holes in the same row, the oxygen-binding layers, and the resistive switching layers are all connected; while the top electrodes of two adjacent vertical holes in the same column, the oxygen-binding layers, and the resistive switching layers are all disconnected.

[0011] The bottom electrode layer and the resistive switching layer are deposited using atomic layer deposition (ALD) technology.

[0012] Another aspect of the present invention provides a semiconductor device having a plurality of first through-holes in a substrate, wherein a first surface of the first through-hole is located on the lower surface of the substrate for connecting a first metal layer, and a second surface of the through-hole is located on the upper surface of the substrate, the device comprising: A first dielectric layer covers the upper surface of the substrate; Vertical holes are located in the first dielectric layer, corresponding one-to-one with the first through holes, and perpendicular to the second surface of the first through holes; The bottom electrode covers the bottom and sidewalls of the vertical hole; A resistive switching layer covers the bottom electrode of the vertical hole and the upper surface of the first dielectric layer; An oxygen-binding layer is formed, filling the vertical pores and covering the resistive switching layer. The top electrode covers the oxygen-binding layer.

[0013] The device further includes an etch stop layer covering the upper surface of the substrate. Correspondingly, the first dielectric layer covers the etch stop layer, and the vertical hole is located in the first dielectric layer and the etch stop layer.

[0014] In this configuration, the resistive switching layer, oxygen-binding layer, and top electrode are disconnected between every two adjacent vertical holes.

[0015] In the array of vertical holes, the top electrodes of two adjacent vertical holes in the same row, the oxygen-binding layers, and the resistive switching layers are all connected; while the top electrodes of two adjacent vertical holes in the same column, the oxygen-binding layers, and the resistive switching layers are all disconnected.

[0016] The resistive switching structure based on vertical holes disclosed herein is a three-dimensional structure. Adjusting only the depth of the vertical holes changes the size of the resistive switching region, effectively freeing it from the influence of the actual substrate area (i.e., aperture area) occupied by the resistive switching structure. Furthermore, based on this three-dimensional structure, the aperture of the vertical holes can be minimized, achieving miniaturization of the resistive switching structure and improving integration density. Simultaneously, the size of the resistive switching structure can be adjusted by changing the depth of the vertical holes to meet various electrical requirements of RRAM. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0018] Figure 1 This is a schematic diagram of a vertical hole provided as an example of this disclosure; Figure 2 A schematic diagram of a vertical hole provided as another example of this disclosure; Figure 3 A schematic diagram of the bottom electrode layer provided as an example of this disclosure; Figure 4 A schematic diagram of an example of filling a vertical hole with organic material provided in this disclosure; Figure 5 This is a schematic diagram of an organic layer and a silicon-oxygen dielectric layer provided as an example of this disclosure; Figure 6 A schematic diagram of the bottom electrode provided as an example of this disclosure; Figure 7 This is a schematic diagram of the bottom electrode layer etching provided as an example of this disclosure; Figure 8 This is a schematic diagram of a resistive switching layer provided as an example of this disclosure; Figure 9 A schematic diagram of the oxygen-binding layer provided as an example of this disclosure; Figure 10 A schematic diagram of the top electrode layer provided as an example of this disclosure; Figure 11This is a schematic diagram of a resistive switching structure provided as an example of the present disclosure; Figure 12 This is a top view of a resistive switching structure provided as an example of the present disclosure; Figure 13 A top view of a resistive switching structure provided as another example of this disclosure; Figure 14 A schematic diagram of the second metal layer (M2) is provided for the purpose of disclosing an example. Detailed Implementation

[0019] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] This disclosure provides an example of a semiconductor device, such as Figure 1 As shown, Figure 1 The diagram shows a cross-sectional view of a semiconductor device, including a substrate 10, a first dielectric layer 20, and a resistive switching structure. This resistive switching structure comprises at least a bottom electrode, a resistive switching layer, an oxide-binding layer, and a top electrode. It should be noted that more functional layers can be added to the resistive switching structure in all examples of this disclosure as needed, and this disclosure does not impose any limitations on this.

[0023] The substrate 10 has a plurality of first vias 01, as an example. Figure 1Only two first through holes are shown in the diagram, and the number of through holes is not limited in this disclosure. The first through hole 01 is filled with metal (e.g., copper), the first surface of the first through hole 01 is located on the lower surface of the substrate and is used to connect the first metal layer (M1), and the second surface of the first through hole 01 is located on the upper surface of the substrate 10.

[0024] The first dielectric layer 20 covers the upper surface of the substrate 10; the vertical hole 02 is located in the first dielectric layer, corresponding one-to-one with the first through hole 01, and is perpendicular to the second surface of the first through hole 01.

[0025] The bottom electrode 40, the resistive switching layer 80, the oxygen-binding layer 90, and the top electrode 100 form a resistive switching structure, wherein: Bottom electrode 40 covers the bottom and sidewalls of the vertical hole to form a vertical hole; resistive switching layer 80 covers the bottom and sidewalls of the second vertical through hole to form a vertical hole, and covers the upper surface of the first dielectric layer; oxygen-binding layer 90 fills the vertical hole and covers the resistive switching layer; top electrode 100 covers the oxygen-binding layer.

[0026] This disclosure provides a method for manufacturing a semiconductor device. A substrate 10 has a plurality of first vias. The first surface of each first via 01 is located on the lower surface of the substrate 10 and is used to connect to a first metal layer (M1). The second surface of each first via 01 is located on the upper surface of the substrate 10. The first via 01 is filled with a metal material. The process in this example begins by planarizing the first via 01 on the substrate 10 after filling it with the metal material, followed by the following steps: Step S1, as follows Figure 1 As shown, a first dielectric layer 20 is deposited on the upper surface of the substrate 10, and the first dielectric layer 20 is etched to form vertical holes 02 that correspond one-to-one with the first via 01 in the first dielectric layer 20. The vertical holes 02 are perpendicular to the second surface of the first via 01.

[0027] The first dielectric layer 20 can be made of silicon oxide (e.g., SiO2). The first dielectric layer 20 is etched using photolithography to obtain vertical holes 02. A corresponding vertical hole 02 is formed directly above each first via 01, and the vertical hole 02 overlaps with the orthographic projection of the first via 01 on the substrate 10.

[0028] Better, such as Figure 2 As shown, to improve the uniformity and consistency of etching, an etch stop layer 30 can be deposited first on the substrate 10, followed by the deposition of the first dielectric layer 20. Then, the first dielectric layer 20 and the etch stop layer 30 are etched using photolithography to obtain the vertical hole 02. The etch stop layer 30 has a significantly lower etching rate than the second dielectric layer 20, ensuring that the etching stops more uniformly within the etch stop layer 30.

[0029] Step S2, as follows Figure 3 As shown, a bottom electrode layer 40 is deposited, which covers the upper surface of the first dielectric layer 20 and the bottom and sidewalls of the vertical hole 01.

[0030] Accept Figure 1 or Figure 2 The structure, in this example, is... Figure 2 Taking this as an example, a bottom electrode layer 40 is deposited on the upper surface of the first dielectric layer 20, completely covering the bottom and sidewalls of the vertical hole 02. The bottom electrode layer 40 can be made of silicon nitride (TiN) and can be deposited using the ALD method. Figure 2 The bottom electrode layer 40 is grown conformally on the structure shown.

[0031] Step S3, as follows Figure 4 As shown, organic material 50 is filled into the vertical hole 02 and then flattened.

[0032] exist Figure 3 On the structure shown, organic material is deposited so that the vertical holes 02 are filled with organic material. The upper surface of the organic material 50 is flattened by chemical mechanical polishing (CMP) so that it is flush with the surface of the bottom electrode layer 40.

[0033] Step S4, as follows Figure 5 and Figure 6 As shown, an organic layer 60 and a silicon-oxygen dielectric layer 70 are deposited sequentially, followed by sequential etching of the silicon-oxygen dielectric layer 70, the organic layer 60, and the bottom electrode layer 40. The bottom electrode layer 40 outside the vertical hole 02 is removed, resulting in the bottom electrode 40 within the vertical hole 02. Figure 6 As shown.

[0034] exist Figure 4 An organic layer 60 and a silicon-oxygen dielectric layer 70 are sequentially deposited on top of the structure shown, as follows: Figure 5 As shown, the organic layer 60 can be made of a fluid organic material, such as ODL (Organic Dielectric Layer), and the silicon-oxygen dielectric layer 70 serves as a hard mask, which can be made of SHB (SiO2). O The photoresist is then etched layer by layer to transfer the pattern of the photoresist used for etching to the bottom electrode layer 40, thereby removing the bottom electrode layer 40 outside the vertical hole 02 and retaining only the bottom electrode 40 in the vertical hole 02. The specific process is as follows: 1. A photoresist layer is deposited on the silicon-oxide dielectric layer 70, and the patterned photoresist layer is used as a mask to etch the silicon-oxide dielectric layer 70, thereby transferring the pattern of the photoresist to the silicon-oxide dielectric layer 70. 2. Remove the photoresist layer and use the patterned silicon-oxygen dielectric layer 70 as a mask to etch the organic layer 60, thereby transferring the pattern to the organic layer 60. 3. Remove the silicon-oxide dielectric layer 70, and use the patterned organic layer 60 as a mask to etch the bottom electrode layer 40, thereby transferring the pattern to the bottom electrode layer 40, that is, removing the bottom electrode layer 40 except for the vertical hole 02. Figure 7 As shown, when etching the bottom electrode layer 40, the filling organic material 50 can effectively protect the bottom electrode 40 in the vertical hole 02 from being damaged.

[0035] 4. Remove the organic material 50 from the organic layer 60 and the vertical holes 02 to obtain... Figure 6 The bottom electrode 40 is shown.

[0036] In the etching method of the bottom electrode 40 described above, organic material 50 is first filled into the vertical hole 02 and then planarized to flatten the vertical hole 02. Then, an organic layer 60 is deposited. The organic layer 60 has good material flowability, resulting in a very flat surface. This ensures that the silicon-oxygen dielectric layer 70 and the photoresist layer are also very flat. The flat photoresist layer effectively protects the area containing the vertical hole 02. Simultaneously, the organic material 50 filling the vertical hole 02 also effectively protects the bottom electrode 40 within it. Therefore, when etching layer by layer until the bottom electrode layer 40 is finally cut off, the bottom electrode 40 on the sidewalls and bottom of the vertical hole 02 will not be damaged.

[0037] Step S5, as follows Figure 8 As shown, a resistive switching layer 80 is deposited so that the resistive switching layer 80 covers the upper surface of the first dielectric layer 20 and conformally covers the bottom electrode 40 of the vertical hole 02.

[0038] exist Figure 6 On the structure shown, a resistive switching layer 80 is deposited. The resistive switching layer 80 can be made of TMO (transition metal oxide) and deposited using the ALD process.

[0039] Since the bottom electrode 40 formed in step S4 is not damaged, the resistive switching layer 80 deposited by the ALD process is uniformly and flatly distributed on the bottom electrode 40, thus meeting the high flatness requirement of the resistive switching structure for the resistive switching layer 80. The flatness of the resistive switching layer 40 in the vertical hole 02 ensures the stability of the characteristics of the final resistive switching structure.

[0040] Step S6, as follows Figure 9As shown, an oxygen-binding layer 90 is deposited so that the oxygen-binding layer 90 covers the upper surface of the resistive switching layer 40 and fills the vertical pores 02.

[0041] exist Figure 8 An oxygen-binding layer 90 is deposited on top of the structure shown. After the oxygen-binding layer 90 binds oxygen atoms in the resistive switching layer 80, it leaves oxygen vacancies in the resistive switching layer 80, forming conductive filaments.

[0042] Step S7, as follows Figure 10 As shown, a top electrode layer 100 is deposited on top of the oxygen-binding layer 90.

[0043] Step S8, as follows Figure 11 As shown, the top electrode layer 100, the oxygen-binding layer 90, and the resistive switching layer 80 are etched to disconnect the resistive switching layer 80, the oxygen-binding layer 90, and the top electrode 100 between two adjacent vertical holes 02.

[0044] In this disclosure, there are two methods for disconnecting the resistive switching layer 80, the oxygen-binding layer 90, and the top electrode 100 between two adjacent vertical holes 02: one is to disconnect the resistive switching layer 80, the oxygen-binding layer 90, and the top electrode 100 between every two adjacent vertical holes 02, such as... Figure 12 The diagram shows a top view of a semiconductor device, where each pattern corresponds to a vertical hole 02. Firstly, in an array of vertical holes 02, the top electrodes 100, oxide-binding layers 90, and resistive switching layers 80 of adjacent vertical holes 02 in the same row are all connected (i.e., not disconnected). Conversely, the top electrodes 100, oxide-binding layers 90, and resistive switching layers 80 of adjacent vertical holes 02 in the same column are disconnected. Figure 13 The diagram shows a top view of a semiconductor device, where each dashed line corresponds to a vertical hole 02.

[0045] In another example, after obtaining the resistive switching structure, i.e. based on Figure 11 The structure shown deposits a second dielectric layer 110 and etches second vias 03 therein, which are filled with a metallic material as a second metal layer (M2). The top electrode 100 of the resistive switching structure in each vertical via 02 is connected to one of the second metal layers (M2).

[0046] The semiconductor device structure of this disclosure will be described in detail below with reference to the accompanying drawings, such as... Figure 11 As shown, the substrate 10 has a plurality of first vias 01. The first surface of the first via 01 is located on the lower surface of the substrate and is used to connect to the first metal layer (M1). The second surface of the via is located on the upper surface of the substrate. The semiconductor device includes: First dielectric layer 20, such as Figure 1 As shown, the first dielectric layer 20 can cover the upper surface of the substrate 10, preferably, as... Figure 2 and Figure 11As shown, the semiconductor device also includes an etch stop layer 30 covering the upper surface of the substrate 10, and correspondingly, a first dielectric layer 20 covers the upper surface of the etch stop layer 30.

[0047] Vertical hole 02, such as Figure 1 As shown, it is located in the first dielectric layer 20, preferably, as Figure 2 and Figure 11 As shown, the vertical hole 02 is located in the first dielectric layer 20 and the etch stop layer 30. The vertical hole 02 corresponds one-to-one with the first through hole 01 and is perpendicular to the second surface of the first through hole 01. The orthogonal projections of the two on the substrate 10 overlap.

[0048] The following Figure 11 The following is an example of how the structure of the semiconductor device disclosed herein will be described: Bottom electrode 40 covers the bottom and sidewalls of vertical hole 02; A resistive switching layer 80 covers the bottom electrode of the vertical hole 40 and the upper surface of the first dielectric layer 20. The resistive switching layer 80 can be divided into two parts: the first part is completely attached to the surface of the bottom electrode 40 in the vertical hole 02, and the second part is divided into left and right sides covering the upper surface of the first dielectric layer 20. The first part and the second part are connected.

[0049] Oxygen-binding layer 90, filled with vertical holes 02, and covered with resistive switching layer 80; Top electrode 100, covered with oxygen-binding layer 90.

[0050] The bottom electrode 40, resistive switching layer 80, oxygen-binding layer 90, and top electrode 100 in the aforementioned vertical hole 02 constitute a resistive switching structure.

[0051] In one example, the resistive switching layer 80, oxygen-binding layer 90, and top electrode 100 between the resistive switching structures corresponding to two adjacent vertical holes in this disclosure need to be cut off. There are two ways to cut them off, such as... Figure 12 As shown, the resistive switching layer 80, oxygen-binding layer 90, and top electrode 100 between every two adjacent vertical holes 02 are disconnected; or as shown... Figure 13 As shown, in the array composed of vertical holes 02, the top electrodes 100, oxygen-binding layers 90, and resistive switching layers 80 of two adjacent vertical holes 02 in the same row are all connected, while the top electrodes 100, oxygen-binding layers 90, and resistive switching layers 80 of two adjacent vertical holes 02 in the same column are all disconnected.

[0052] As can be seen from the above example, the resistive switching structure provided in this disclosure is a three-dimensional structure based on a vertical hole 02: first, a vertical hole 02 is formed, and a bottom electrode 40 is deposited on the inner wall (i.e., the bottom and side walls) of the vertical hole 02 using ALD. Then, a resistive switching layer 80 is deposited on the surface of the bottom electrode 40 using ALD. Then, an oxide-binding layer 90 is filled in the vertical hole 02, and a top electrode 100 is deposited on the surface of the oxide-binding layer 90. The existing stacked resistive switching structure is obtained by etching with a photomask after all the thin films are deposited in sequence, and it is a planar structure.

[0053] In the disclosed three-dimensional structure, the size of the resistive switching region is the sum of the area of ​​the vertical sidewall of the vertical hole 02 and the area of ​​the bottom. Thus, the size of the resistive switching region can be adjusted by modifying both the depth and the aperture area of ​​the vertical hole 02. Based on this three-dimensional structure, adjusting only the depth of the vertical hole 02 can change the size of the resistive switching region, effectively freeing it from the influence of the actual substrate area (i.e., aperture area) occupied by the resistive switching structure. Since some electrical properties of RRAM are sensitive to the size of the resistive switching structure, determining the size of the resistive switching structure by controlling the depth of the vertical hole 02 can better accommodate this sensitivity.

[0054] Furthermore, based on the three-dimensional structure disclosed herein, the aperture of the vertical hole 02 can be minimized (the aperture size is only affected by the process level), realizing the miniaturization of the resistive switching structure and improving the integration density. At the same time, the depth of the vertical hole 02 can be adjusted to adjust the size of the resistive switching structure to meet various electrical requirements of semiconductor devices.

[0055] In the three-dimensional structure disclosed herein, the resistive switching structure in a vertical hole 02 can be regarded as two resistive switching structures on the left and right. These two resistive switching structures are not etched and cut off, thus avoiding plasma damage to the resistive switching layer and better ensuring device performance.

[0056] Finally, the vertical hole 02 is formed in the dielectric layer, and no void is generated in the dielectric layer formed earlier. Therefore, the dielectric layer perfectly isolates the adjacent vertical hole 02, and no metal layer bridging problem occurs.

[0057] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0058] The foregoing description is intended to enable any person skilled in the art to implement and use the contents of this disclosure, and is provided in the context of a particular application and its requirements. Furthermore, the foregoing description of embodiments of this disclosure is given for illustrative and descriptive purposes only. They are not intended to be exhaustive or to limit this disclosure to the forms disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Moreover, the foregoing discussion of embodiments is not intended to limit this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown, but will be given the widest scope consistent with the principles and features disclosed herein.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The substrate has a plurality of first through-holes, the first surface of the first through-holes being located on the lower surface of the substrate for connecting a first metal layer, and the second surface of the first through-holes being located on the upper surface of the substrate. The method includes: A first dielectric layer is deposited on the upper surface of the substrate, and the first dielectric layer is etched to form vertical holes in the first dielectric layer that correspond one-to-one with the first vias. The vertical holes are perpendicular to the second surface of the first vias. A bottom electrode layer is deposited, which covers the upper surface of the first dielectric layer and the bottom and sidewalls of the vertical hole; The vertical holes are filled with organic material and then flattened. An organic layer and a silicon-oxygen dielectric layer are deposited sequentially, and the silicon-oxygen dielectric layer, organic layer and bottom electrode layer are etched sequentially, retaining the organic material in the vertical hole, so as to remove the bottom electrode layer outside the vertical hole and obtain the bottom electrode in the vertical hole. Remove organic material from the vertical holes; A resistive switching layer is deposited such that the resistive switching layer covers the upper surface of the first dielectric layer and conformally covers the bottom electrode of the vertical hole; Deposit an oxygen-binding layer to cover the upper surface of the resistive switching layer and fill the vertical pores; A top electrode layer is deposited on the oxygen-binding layer; The top electrode layer, the oxygen-binding layer, and the resistive switching layer are etched to disconnect the resistive switching layer, the oxygen-binding layer, and the top electrode between two adjacent vertical holes.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before depositing a dielectric layer on the upper surface of the substrate, the method further includes: An etching stop layer is deposited on the upper surface of the substrate; Accordingly, the first dielectric layer is deposited on the etch stop layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The method further includes etching the dielectric layer and the etch stop layer to obtain the vertical hole.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The resistive switching layer, oxygen-binding layer, and top electrode between each pair of adjacent vertical holes are disconnected.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, In an array of vertical holes, the top electrodes of two adjacent vertical holes in the same row, the oxygen-binding layers, and the resistive switching layers are all connected; the top electrodes of two adjacent vertical holes in the same column, the oxygen-binding layers, and the resistive switching layers are all disconnected.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The bottom electrode layer and the resistive switching layer are deposited using atomic layer deposition (ALD) technology.

Images