Chip and chip package

Abstract

The application provides a chip and a chip package, relates to the technical field of chip interconnection, and can reduce the power consumption and area of a chip interconnection interface. The chip comprises a chip interconnection interface, the chip interconnection interface comprises a buffer, the buffer is a standard unit, one of the output end and the input end of the buffer is connected with a connecting part of a chip active surface, and the other is connected with an internal digital circuit in the chip; and the connecting part of the chip active surface is connected with an external chip.

Description

Technical Field

[0001] This application relates to the field of chip interconnect technology, and in particular to a chip and chip package. Background Technology

[0002] 3D (three-dimensional) stacked packaging (also known as 3D IC) has the advantages of small package area, low cost, and high integration, making it the current development direction of chip packaging technology. The higher the integration of 3D IC, the higher the bandwidth and data volume requirements for inter-die interconnection, making the use of low-power, small-area interconnect interfaces between dies an urgent need.

[0003] In traditional 3D stacked packaging, GPIO (general purpose input / output) is often used for die interconnection. While GPIO can be applied to many scenarios, its internal structure is complex, it occupies a large area, and has high power consumption (1-3mW / Gbit). Alternatively, SERDES (serializer / deserializer) is used for die interconnection. This method requires simulating the PHY (physical layer) and suffers from drawbacks such as customization requirements, complex structure, high power consumption (1mW / Gbit), large area footprint, and numerous physical constraints. Furthermore, related technologies can also use customized small IO for die interconnection. This method also suffers from drawbacks such as requiring PHY simulation and customization, and its area and power consumption do not meet the expected requirements. Summary of the Invention

[0004] This application provides a chip and chip package that can reduce the power consumption and area of ​​the chip interconnect interface.

[0005] This application provides a chip including a chip interconnect interface; the chip interconnect interface includes a buffer; the buffer is a standard cell (std cell); the buffer includes an input terminal and an output terminal; one of the output terminal and the input terminal of the buffer is connected to a connection portion of the active surface of the chip, and the other is connected to internal digital circuitry within the chip; the connection portion of the active surface of the chip is connected to an external chip (i.e., the connection portion of the active surface of an external chip). In the embodiments of this application, the chip can refer to a die or a wafer.

[0006] It should be understood that in the chip interconnect interface of this application, the buffer of the standard cell may include a buffer built using general basic units such as inverters (i.e., NOT gates), AND gates, OR gates, tri-state gates, NAND gates, NOR gates, etc.; or it may use a buffer from the basic cell library (std cell lib) provided by the chip manufacturer (e.g., foundry, but not limited to this).

[0007] The chip interconnect interface provided in this application uses a standard cell buffer. On the one hand, the buffer in the chip interconnect interface can be directly selected according to the actual application scenario of the chip, using a standard cell with appropriate specifications and driving force. That is, the buffer can be flexibly selected without customization. On the other hand, the standard cell occupies a small area and has low power consumption, thus meeting the area and power consumption requirements of the chip interconnect interface. In other words, compared with the complex interconnect interfaces (such as GPIO, SERDES, etc.) used in the prior art, in this application, for the interconnection between two chips with a small gap, a suitable standard cell buffer with low driving force can be selected as the interconnect interface according to the actual needs of the chip, thereby effectively reducing the power consumption and area of ​​the chip interconnect interface.

[0008] In some possible implementations, the buffer described above may include one or more of the following: NOT gate, AND gate, OR gate, tri-state gate, NAND gate, and NOR gate.

[0009] In some possible implementations, the buffers described above can be buffers from the basic cell library (std cell lib) provided by the chip manufacturer (e.g., foundry, but not limited to).

[0010] In some possible implementations, the aforementioned buffer is a receive buffer, with its input connected to the connection portion of the active surface of the chip, and its output connected to the internal digital circuitry within the chip. The receive buffer (Rx buffer) serves as an interconnect interface to achieve unidirectional input of data signals, transmitting the data signals received by the connection portion of the active surface of the chip to the internal digital circuitry within the chip.

[0011] In some possible implementations, the aforementioned buffer is a transmit buffer, with its output connected to the connection portion of the chip's active surface and its input connected to the internal digital circuitry within the chip. The transmit buffer (Tx buffer) serves as an interconnect interface to achieve unidirectional output of the data signal, transmitting the data signal output from the chip's internal digital circuitry to the connection portion of the chip's active surface via this transmit buffer.

[0012] In some possible implementations, the buffer includes a receive buffer and a transmit buffer; the input terminal of the receive buffer and the output terminal of the transmit buffer are both connected to the same connection portion of the active surface of the chip; the output terminal of the receive buffer is connected to a first internal digital circuit in the chip; the input terminal of the transmit buffer is connected to a second internal digital circuit in the chip; the receive buffer also includes an input control terminal, and the transmit buffer also includes an output control terminal. This chip interconnect interface, as a bidirectional input / output interface, enables the input or output of data signals by simultaneously setting up receive and transmit buffers and switching between them via the input and output control terminals. This allows for dynamic input / output switching applications or internal loopback requirements.

[0013] In some possible implementations, the transmit buffer includes a tri-state buffer.

[0014] In some possible implementations, the chip interconnect interface also includes a level conversion circuit; the level conversion circuit is located on the connection path between the buffer and the internal digital circuit; the level conversion circuit performs level conversion to match the operating voltage domain of the chip where the interconnect interface is located.

[0015] In some possible implementations, the chip interconnect interface also includes an electrostatic discharge circuit; the electrostatic discharge circuit is located in the connection path of the connection between the buffer and the active surface of the chip; to solve the electrostatic problem introduced during the chip packaging process.

[0016] In some possible implementations, the chip includes multiple signal channels; these signal channels include a backup channel and multiple data channels; the chip also includes a test signal generation circuit, a multiplexer, and D flip-flops, dual-channel selectors, and chip interconnect interfaces located in each signal channel; wherein the chip interconnect interface includes a transmit buffer; in the data channel, the input of the D flip-flop is connected to the output of the dual-channel selector, and the output of the D flip-flop is connected to the input of the transmit buffer; the first input of the dual-channel selector is connected to the internal digital circuitry in the chip; the second input of the dual-channel selector is connected to the test signal generation circuit; in the backup channel, the input of the D flip-flop is connected to the output of the dual-channel selector, and the output of the D flip-flop is connected to the input of the transmit buffer; the first input of the dual-channel selector is connected to the output of the multiplexer; the second input of the dual-channel selector is connected to the test signal generation circuit; the multiple inputs of the multiplexer are respectively connected to the first input of the dual-channel selector located in the data channel.

[0017] In some possible implementations, the chip includes multiple signal channels; among the multiple signal channels are a backup channel and multiple data channels; the chip also includes a chip interconnect interface, a D flip-flop, a channel detection circuit, and a dual-channel selector located in each of the signal channels; wherein the chip interconnect interface includes a receive buffer; in the data channel, the input of the D flip-flop is connected to the output of the receive buffer, the output of the D flip-flop is connected to the first input of the dual-channel selector and the channel detection circuit, the second input of the dual-channel selector is connected to the output of the D flip-flop in the backup channel, and the output of the dual-channel selector is connected to the internal digital circuitry in the chip; in the backup channel, the input of the D flip-flop is connected to the output of the receive buffer, and the output of the D flip-flop is connected to the channel detection circuit.

[0018] By setting up a backup channel in the chip and combining it with the testing logic at each stage for channel identification, the chip can switch to the backup channel for normal data transmission when a yield problem occurs in a certain data channel, thereby improving the overall yield and reliability of the chip.

[0019] This application also provides a chip package, including a first chip and a second chip stacked together; both the first chip and the second chip include chips as described in any of the aforementioned possible implementations; a connection portion located on the active surface of the first chip is connected to a connection portion located on the active surface of the second chip.

[0020] This application embodiment also provides a method for selecting a buffer in a chip interconnect interface as described in any of the aforementioned possible implementations, including: a standard unit simulates a first buffer, auxiliary circuit, and drive path model through an SI simulation environment, and obtains simulation results; wherein, the type and driving capability of the first buffer are determined according to the application scenario and path parameters of the chip interconnect interface; the simulation results are used in conjunction with the power consumption and area of ​​the first buffer to determine whether the first buffer is used as a buffer in the chip interconnect interface.

[0021] Compared to related technologies where chip interconnect interfaces require customized and complex interface circuits, resulting in drawbacks such as large interconnect interface area and high power consumption, the selection method of this application is compatible with EDA development environments. By selecting the buffers actually needed in the chip interconnect interface from the std cell, the area and power consumption of the chip interconnect interface can be reduced. Attached Figure Description

[0022] Figure 1 A schematic diagram of partially stacked interconnect chips in a chip package provided in this application embodiment;

[0023] Figure 2 A chip interconnect interface provided in an embodiment of this application;

[0024] Figure 3 A chip interconnect interface provided in an embodiment of this application;

[0025] Figure 4 A chip interconnect interface provided in an embodiment of this application;

[0026] Figure 5 A chip interconnect interface provided in an embodiment of this application;

[0027] Figure 6 A schematic diagram of an interconnection interface between two chips provided in an embodiment of this application;

[0028] Figure 7 A schematic diagram of an interconnection interface between two chips provided in an embodiment of this application;

[0029] Figure 8 A schematic diagram of a partial connection circuit between two chips provided in an embodiment of this application;

[0030] Figure 9 This is a schematic flowchart illustrating a method for selecting a buffer in a chip interconnect interface, as provided in an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0033] This application provides a chip package, such as... Figure 1 As shown, the chip package includes multiple chips stacked together, such as a first chip 10 and a second chip 20, meaning the chip package is a 3D stacked package. In this embodiment, the chip can refer to a die or a wafer.

[0034] This application does not limit the application scenarios of each chip in the 3D stacked packaging. For example, the first chip 10 and the second chip 20 mentioned above can be logic chips, pixel chips, memory chips, interface chips, etc.

[0035] Understandably, for chips, reference Figure 1 As shown, the active surface of the chip has a raised structure that is electrically connected to an external chip. This raised structure serves as a connection part 01 on the active surface of the chip, enabling signal transmission between the chip and the external chip.

[0036] This application does not limit the arrangement of the connection part 01. For example, it can be a micro bump (μbump), an embedded micro bump (embedded μbump), a gold bump (gold bump), a copper bump (Cu bump), etc. In practice, the connection method of the connection parts of the two chips can be selected according to the specific arrangement of the connection part 01. For example, it can be a hybrid bonding (HB) or a fusion bonding.

[0037] In addition, the chip has internal digital circuits, which are specifically configured according to the actual application scenarios of the chip. The chip also has an interconnection interface (i.e., chip interconnection interface, or chip interconnection interface circuit) that connects the connection part located on the active surface to the internal digital circuit. The data signals of the chip's internal digital circuit need to be input and output through the interconnection interface to ensure normal interconnection and communication between chips.

[0038] For illustrative purposes only, please refer to the following: Figure 1 As shown, for the first chip 10 and the second chip 20 that perform interconnection communication in the chip package, the first chip 10 is provided with a first interconnection interface connecting the internal digital circuit and a first connection portion (such as a μbump) a1 on the active surface, and the second chip 20 is provided with a second interconnection interface connecting the internal digital circuit and a second connection portion a2 (such as a μbump) on the active surface; the interconnection interfaces in the first chip 10 and the second chip 20 are connected through the connection portions (a1, a2) located on the active surface, thereby realizing interconnection communication between the internal digital circuits. Of course, this application does not limit the connection method of the first connection portion and the second connection portion.

[0039] Additionally, it is understood that the data signal between the first chip 10 and the second chip 20 is transmitted through the first interconnect interface and the second interconnect interface. During the signal transmission process, the first interconnect interface and the second interconnect interface serve as an output interface and an input interface, respectively. For example, the second interconnect interface in the second chip 20 receives the data signal output from the first chip 10 through the first interconnect interface, that is, the second interconnect interface serves as an input interface and the first interconnect interface serves as an output interface.

[0040] In this application, the type of interconnect interface located in the chip (such as unidirectional data transmission or bidirectional data transmission) can be set according to requirements. For example, the first interconnect interface and the second interconnect interface may perform unidirectional data transmission. In this case, one of the first interconnect interface and the second interconnect interface serves as an output interface and the other as an input interface. Alternatively, the first interconnect interface and the second interconnect interface need to perform bidirectional data transmission. In this case, the first interconnect interface and the second interconnect interface have both input and output functions. By controlling the switching, one can ensure that one serves as an output interface and the other as an input interface.

[0041] Compared to interconnect interfaces in related technologies that use GPIO (general purpose input / output), serdes (serializer / deserializer), or small IO (custom small input / output), which have drawbacks such as high power consumption, large area, numerous physical constraints, and the need for custom implementation, the chip interconnect interface provided in this application has advantages such as low power consumption, small area, and no need for customization.

[0042] The following provides a further description of the chip interconnect interface (hereinafter also referred to as the interconnect interface) provided in the embodiments of this application.

[0043] This application provides a chip interconnect interface including a buffer. The buffer uses a standard cell (std cell), and one of its output and input terminals is connected to a connection portion (e.g., a μbump) located on the active surface of the chip, while the other is connected to an internal digital circuit within the chip. This buffer enables data signal transmission between the connection portion and the internal digital circuit. Of course, the internal digital circuit and the chip interconnect interface can be directly connected or indirectly connected through other circuits. This application does not impose specific limitations on this; in practice, the specific configuration can be tailored to the application scenario of the chip.

[0044] It should be understood that in the chip interconnect interface of this application, the buffer of the standard cell may include a buffer built using general basic units such as inverters (i.e., NOT gates), AND gates, OR gates, tri-state gates, NAND gates, NOR gates, etc.; or it may use a buffer from the basic cell library (std cell lib) provided by the chip manufacturer (e.g., foundry, but not limited to this).

[0045] In summary, the buffer in the chip interconnect interface provided in this application uses a standard cell (stdcell). In this case, on the one hand, the buffer in the chip interconnect interface can be directly selected based on the actual application scenario of the chip, choosing a stdcell with appropriate specifications and driving force; that is, the buffer can be flexibly selected without customization. On the other hand, the standard cell occupies a small area and consumes less power, thus meeting the area and power consumption requirements of the interconnect interface. In other words, compared to the complex interconnect interfaces (such as GPIO, SERDES, etc.) used in the prior art, in this application, for the interconnection between two chips with a small gap, a suitable standard cell buffer with low driving force can be selected as the interconnect interface according to the actual needs of the chip, thereby effectively reducing the power consumption and area of ​​the chip interconnect interface.

[0046] Furthermore, the chip interconnect interface of this application can adopt different types of chip interconnect interfaces depending on its application scenario, that is, the types of buffers in the chip interconnect interface are different; for example, when the interconnect interface is used as an output interface, a transmit buffer (Tx buffer) is used; when the interconnect interface is used as an input interface, a receive buffer (Rx buffer) is used; when the interconnect interface needs to switch to realize input and output, the interconnect interface can simultaneously set Tx buffer and Rx buffer to realize bidirectional transmission of data signals; the following describes the specific settings of the buffers set inside the chip interconnect interface in conjunction with the type of chip interconnect interface.

[0047] For example, in some possible implementations, the chip interconnect interface serves as an input interface, applicable only to unidirectional signal input scenarios; in this case, such as Figure 2 As shown, the buffer in the chip interconnect interface can be configured as a receive buffer (Rx buffer) B1, and the input terminal of the receive buffer B1 is connected to the connection portion O1 (such as μbump) located on the active surface of the chip, and the output terminal of the receive buffer B1 is connected to the internal digital circuitry in the chip. Figure 2 (Not shown in the image) The data signal C received by the connection part 01 of the active surface of the chip is transmitted to the internal digital circuit in the chip through the receiving buffer.

[0048] For example, in some possible implementations, the chip interconnect interface serves as an output interface, applicable only to unidirectional signal output scenarios; in this case, such as Figure 3 As shown, the buffer in the chip interconnect interface can be configured as a transmit buffer (Tx buffer) B2, and the input of the transmit buffer B2 is connected to the internal digital circuitry in the chip. Figure 3 (Not shown in the diagram) The output terminal of the transmit buffer B2 is connected to the connection part 01 (such as μbump) located on the active surface of the chip. The data signal I output by the internal digital circuit in the chip is output to the connection part 01 on the active surface of the chip through the transmit buffer B2.

[0049] For example, in some possible implementations, the chip interconnect interface serves as a bidirectional input / output interface, enabling dynamic switching between input and output scenarios or internal loopback requirements; in this case, such as Figure 4 As shown, the chip interconnect interface can be equipped with two buffers: a receive buffer (Rx buffer) B1 and a transmit buffer (Tx buffer) B2. The input terminal of the receive buffer B1 is connected to the connection portion O1 located on the active surface of the chip, and its output terminal is connected to the first internal digital circuit in the chip. The receive buffer B1 also includes an input control terminal IE. The input terminal of the transmit buffer B2 is connected to the second internal digital circuit in the chip, and its output terminal is connected to the connection portion O1 located on the active surface of the chip. The transmit buffer B2 also includes an output control terminal OE. The receive buffer B1 and transmit buffer B2 are switched via the input control terminal IE and the output control terminal OE to achieve data signal input or output. For example, the input control terminal IE controls the receive buffer B1 to be turned on for data signal input, and the output control terminal OE controls the transmit buffer B2 to be turned on for data signal output.

[0050] It should be noted that, for Figure 4 Regarding the interconnection interface shown in the figure, which uses a receive buffer B1 and a transmit buffer B2 for bidirectional data signal transmission, the first internal digital circuit connected to the receive buffer B1 and the second internal digital circuit connected to the transmit buffer B2 can be the same internal digital circuit or different internal digital circuits. This application does not impose specific restrictions on this, and in practice, specific settings can be made according to the application scenario of the chip.

[0051] This application does not limit the specific types of the above-mentioned receive buffer B1 and transmit buffer B2. In practice, the appropriate std cell can be selected as needed.

[0052] Illustratively, in some possible implementations, the aforementioned transmit buffer B2 can be a tri-state gate circuit (also known as a tri-state buffer).

[0053] Indicatively, in some possible implementations, the aforementioned receive buffer B1 can be an AND gate, a tri-state gate, a NOT gate, etc.

[0054] In addition, to match the operating voltage domain of the chip where the interconnect interface is located, in some possible implementations, a level shift circuit can be set on the connection path between the buffer and the internal digital circuit to convert the voltage of the transmitted signal to the operating voltage domain. This application does not limit the specific structure of the level shift circuit; in practice, a suitable level shift circuit can be selected as needed.

[0055] Indicative, such as Figure 5 As shown, a level conversion circuit LS1 can be set on the connection path between the input of the transmit buffer B2 and the internal digital circuit, and a level conversion circuit LS2 can be set on the connection path between the output of the receive buffer B1 and the internal digital circuit. Of course, for the two interconnecting chips, the level conversion circuit in the interconnection interface can be specifically configured according to the specific application scenario; for example, in some possible implementations, such as... Figure 6 As shown, in the two interconnect interfaces (A1 and A2) connecting the two chips, level conversion circuits (LS1, LS2) can be set only in interconnect interface A1, while no level conversion circuit is set in interconnect interface A2. Level conversion is performed by setting level conversion circuits (LS1, LS2) in interconnect interface A1 to meet the level requirements of the two chips during data signal transmission. Alternatively, in some possible implementations, a level conversion circuit can be set in each of the two interconnect interfaces (A1 and A2) to meet the operating voltage domain requirements of the two chips. This application does not limit this.

[0056] Furthermore, to address the electrostatic discharge (ESD) issues introduced during the chip packaging process, some possible solutions refer to... Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6As shown, an electrostatic discharge (ESD) circuit 02 can be provided on the connection path between the buffers (such as B1 and B2) in the interconnect interface and the connection part 01 to perform electrostatic discharge and achieve the purpose of electrostatic protection. This application does not limit the specific structure of the ESD protection circuit 02, and it can be selected as needed in practice; for example, the smallest unit (i.e., cell) of the ESD circuit of appropriate CDM (charged device model) specification can be selected according to the chip area, packaging process control capability, etc. Of course, for CDM specifications of different voltage and current levels, ESD may be multiple cells connected in parallel.

[0057] Additionally, it should be noted that the electrostatic discharge (ESD) protection circuit 02 in the chip interconnect interface of this application can be flexibly configured as needed; for example, such as Figure 7 As shown, in the two interconnected interfaces, one is an input interface A3 and the other is an output interface A4. The electrostatic discharge protection circuit 02 can be set only in the input interface A3 and not in the output interface A4. Electrostatic discharge protection for both interconnected interfaces can be achieved by using only the electrostatic discharge protection circuit 02 in the input interface A3.

[0058] Based on this, considering that there are certain yield issues in the packaging process of 3D stacked packaging structures, such as chip-to-chip bonding and through silicon via (TSV) fabrication, in some possible implementation methods, a backup channel can be set in the chip. Combined with various testing stages, such as the CP (chip probing) test stage and the FT (final test) stage, channel identification can be performed so that when a yield problem occurs in a certain data channel, the backup channel can be switched to perform normal data transmission, thereby improving the overall yield and reliability of the chip.

[0059] It is understandable that the data channel formed between the two chips is based on the connectivity of their interconnect interfaces, as referenced. Figure 8 As shown, the following example illustrates unidirectional data transmission between two chips (10, 20). The interconnection interface in the first chip 10 is an output interface (i.e., using Tx buffer B2), and the interconnection interface in the second chip 20 is an input interface (i.e., using Rx buffer B1). The first chip 10 and the second chip 20 are provided with 8 (not limited to) data channels P and 1 backup channel P'. The channels in the first chip 10 and the channels in the second chip 20 are connected one-to-one through the connection parts located on the active surface. The following describes the relevant circuit settings for channel identification and switching backup channels.

[0060] refer to Figure 8 As shown, in the first chip 10, each signal channel (including P, P') includes a D flip-flop and a dual-channel selector M2; in addition, the first chip 10 also includes a test signal generation circuit 100 and a multiplexer Mn. Indicatively, the test signal generation circuit 100 may employ a PRBS generator (pseudo random binary sequence generator), but is not limited to this.

[0061] In the data channel P of the first chip 10, the input of the D flip-flop is connected to the output of the dual-channel selector M2, and the output of the D flip-flop is connected to the input of the Tx buffer B2; the first input of the dual-channel selector M2 is connected to the internal digital circuit in the first chip 10 (to receive the transmitted signal snd_sig from the internal digital circuit); the second input of the dual-channel selector M2 is connected to the test signal generation circuit 100.

[0062] In the backup channel P' of the first chip 10, the input of the D flip-flop is connected to the output of the dual-channel selector M2, and the output of the D flip-flop is connected to the input of the Tx buffer B2; the first input of the dual-channel selector M2 is connected to the output of the multiplexer Mn; and the second input of the dual-channel selector M2 is connected to the test signal generation circuit 100.

[0063] The eight input terminals of the multiplexer Mn are connected one-to-one with the first input terminal of the dual multiplexer M2 in each of the eight data channels P. The output terminal of the Tx buffer B2 in each channel (including P and P') is connected to the connection part located on the active surface of the first chip 10.

[0064] refer to Figure 8 As shown, in the second chip 20, each data channel P includes a D flip-flop, a channel detection circuit 200, and a dual-channel selector M2; the backup channel P' includes a D flip-flop and a channel detection circuit 200. It is illustrated that the channel detection circuit 200 can employ a PRBS check (pseudo-random binary sequence check), but is not limited to this.

[0065] In data channel P, the input of the D flip-flop is connected to the output of Rx buffer B1, and the output of the D flip-flop is connected to the first input of the dual-channel selector M2 and the channel detection circuit 200. The second input of the dual-channel selector M2 is connected to the output of the D flip-flop in the backup channel P', and the output of the dual-channel selector M2 is connected to the internal digital circuit in the second chip 20. The internal digital circuit receives the signal (rcv_sig) sent through the output of the dual-channel selector M2.

[0066] In the backup channel P', the input of the D flip-flop is connected to the output of the Rx buffer B1, and the output of the D flip-flop is connected to the channel detection circuit 200.

[0067] The input terminals of Rx buffer B1 located in each path (including P and P') are respectively connected to the connection portion located on the active surface of the second chip 20.

[0068] Of course, it is understandable that for the D flip-flops in each signal channel (P, P'), it is necessary to control them through the clock signal at the clock signal terminal. The first chip 10 and the second chip 20 can set up a separate signal channel (i.e., clk channel) for the clock signal to transmit the clock signal in order to control the D flip-flops.

[0069] During the interconnection and communication between the first chip 10 and the second chip 20, the detection of each data channel P can be achieved by combining the test signal generation circuit 100 (such as PRBS generate) and the channel detection circuit 200 (such as PRBS check).

[0070] Specifically, the dual-channel selector M2 in the first chip 10 and the second chip 20 switches each signal channel to the testing phase. The test signal generated by the test signal generation circuit 100 is transmitted to the second chip 20 through the D flip-flops and interconnection interface (B2) in each signal channel of the first chip 10, and then received and detected by the channel detection circuit 200 after passing through the interconnection interface (B1) and D flip-flops in the second chip 20. In this case, if the channel detection circuit 200 in each signal channel of the second chip 20 receives the normal test signal generated by the test signal generation circuit 100, it indicates that the signal channel containing the test signal is normal. If the channel detection circuit 200 in a certain data channel P does not receive the normal test signal, it indicates that the data channel P containing the test signal is in an abnormal state. At this time, the data signal in the data channel P is switched to the backup channel P' for data transmission through the multiplexer Mn located in the first chip 10. Of course, during the data transmission phase, the dual-channel selector M2 in the first chip 10 and the second chip 20 needs to be switched to the data transmission phase to perform data transmission.

[0071] Furthermore, as mentioned above, the buffers in the chip interconnect interface of this application use standard cells (stdcell). Therefore, factors such as the area and power consumption of the chip interconnect interface are directly related to the selection of the buffers. Based on this, embodiments of this application provide a method for selecting buffers in a chip interconnect interface. This method can preferentially select buffers suitable for the chip interconnect interface, such as... Figure 9 As shown, the selection method includes:

[0072] Step 01: Determine the type of first buffer using std cell based on the application scenario of the chip interconnect interface, and determine the driving capability of the first buffer based on the path parameters of the first buffer.

[0073] As illustrated, if the chip interconnect interface is used as an output interface, in this case, a type of Tx buffer can be selected in the std cell; among the Tx buffers of the already determined type, a Tx buffer with appropriate driving capability is selected according to the path parameters of the buffers in the chip interconnect interface.

[0074] It should be noted here that the path parameters of the first buffer mentioned above refer to the comprehensive information parameters of factors such as path length and crosstalk in all stages between the two chip interconnect interfaces. Taking the first buffer as a Tx buffer as an example, this path parameter refers to the comprehensive path parameters of all stages between the Tx buffer and the Rx buffer in the other chip interconnected with it.

[0075] Step 02: Simulate the first buffer, auxiliary circuit, and drive path model using the SI simulation environment, and obtain the simulation results.

[0076] As illustrated, first, an SI simulation environment is established, and then the Tx buffer, auxiliary circuit, and drive path model determined in step 01 are simulated to obtain the simulation results.

[0077] Of course, it is understandable that the simulation results can clearly indicate the relevant parameters (such as duty cycle, peak value, etc.) of the signal output by the Tx buffer and the signal received by the Rx buffer in the chip interconnect interface for signal transmission.

[0078] Step 03: Based on the simulation results and the power consumption and area of ​​the first buffer, determine whether the first buffer should be used as a buffer in the chip interconnect interface.

[0079] As illustrated, based on the signal parameters transmitted between the two chip interconnect interfaces in the simulation results obtained in step 02, and combined with the power consumption and area of ​​the Tx buffer, the Tx buffer is evaluated. If the power consumption and area of ​​the Tx buffer meet the actual expected target, the Tx buffer can be selected as a buffer in the chip interconnect interface. If the power consumption and area of ​​the Tx buffer do not meet the actual expected target, the process of steps 01 and 02 can be repeated until the power consumption and area of ​​the Tx buffer meet the actual expected target, then the first buffer is determined as a buffer in the chip interconnect interface.

[0080] It should be noted that the above selection method is only illustrative to illustrate the Tx buffer selection process. In practice, this selection method can also be used to select both the Tx buffer and the Rx buffer simultaneously.

[0081] Once the buffer used in the chip interconnect interface is determined using the above selection method, no customization is required; it can be implemented using standard digital code development methods and processes.

[0082] Compared to related technologies where chip interconnect interfaces require customized and complex interface circuits, resulting in drawbacks such as large interconnect interface area and high power consumption, the selection method of this application can optimize the buffers actually needed in the chip interconnect interface within the std cell, and is also compatible with the current EDA (electronic design automation) development environment, thereby meeting the requirements of chip interconnect interfaces for area and power consumption.

[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized by The chip includes an internal digital circuit and a chip interconnection interface; the chip interconnection interface includes a buffer; the buffer is a standard cell; The buffer includes an input end and an output end; One of the output end and the input end of the buffer is connected with a connecting part of the chip active surface, and the other is connected with the internal digital circuit; the connecting part is connected with an external chip; The chip includes a plurality of signal channels; the plurality of signal channels include one backup channel and a plurality of data channels; The chip further includes a test signal generation circuit, a multiplexer, a D flip-flop, a two-way selector, and a chip interconnection interface in each signal channel; the chip interconnection interface includes a sending buffer; In the data channel, the input end of the D flip-flop is connected with the output end of the two-way selector, and the output end of the D flip-flop is connected with the input end of the sending buffer; the first input end of the two-way selector is connected with the internal digital circuit in the chip; and the second input end of the two-way selector is connected with the test signal generation circuit; In the backup channel, the input end of the D flip-flop is connected with the output end of the two-way selector, and the output end of the D flip-flop is connected with the input end of the sending buffer; the first input end of the two-way selector is connected with the output end of the multiplexer; and the second input end of the two-way selector is connected with the test signal generation circuit; The plurality of input ends of the multiplexer are respectively connected with the first input ends of the two-way selectors in the data channels.

2. The chip of claim 1, wherein The buffer includes one or more of a NOT gate, an AND gate, an OR gate, a tristate gate, an NAND gate, and an NOR gate.

3. The chip according to claim 1 or 2, characterized in that, The buffer is a receiving buffer, the input end of the receiving buffer is connected with the connecting part of the chip active surface, and the output end of the receiving buffer is connected with the internal digital circuit in the chip.

4. The chip of claim 1, wherein The buffer is a sending buffer, the output end of the sending buffer is connected with the connecting part of the chip active surface, and the input end of the sending buffer is connected with the internal digital circuit in the chip.

5. The chip of claim 1, wherein The buffer includes a receiving buffer and a sending buffer; The input end of the receiving buffer and the output end of the sending buffer are both connected with the same connecting part of the chip active surface; The output end of the receiving buffer is connected with a first internal digital circuit in the chip; The input end of the sending buffer is connected with a second internal digital circuit in the chip; The receiving buffer further includes an input control end, and the sending buffer further includes an output control end.

6. The chip according to claim 4 or 5, characterized in that The sending buffer includes a tristate buffer.

7. The chip according to claim 1 or 2, characterized in that, The chip interconnection interface further includes a level conversion circuit; the level conversion circuit is arranged on a connection path of the buffer and the internal digital circuit.

8. The chip according to claim 1 or 2, characterized by The chip interconnection interface further includes an electrostatic discharge circuit; the electrostatic discharge circuit is arranged on a connection path of the connecting part of the buffer and the chip active surface.

9. The chip of claim 1, wherein, The chip includes a plurality of signal channels; the plurality of signal channels include one backup channel and a plurality of data channels; The chip further comprises a chip interconnection interface, a D flip-flop, a channel detection circuit in each of the signal channels, and a two-way selector in each of the data channels; wherein the chip interconnection interface comprises a receiving buffer; In the data channel, an input end of the D flip-flop is connected with an output end of the receiving buffer, an output end of the D flip-flop is connected with a first input end of the two-way selector and the channel detection circuit, a second input end of the two-way selector is connected with an output end of the D flip-flop in the backup channel, and an output end of the two-way selector is connected with an internal digital circuit in the chip; In the backup channel, an input end of the D flip-flop is connected with an output end of the receiving buffer, and an output end of the D flip-flop is connected with the channel detection circuit.

10. A chip package, characterized by The chip further comprises a chip interconnection interface, a D flip-flop, a channel detection circuit in each of the signal channels, and a two-way selector in each of the data channels; wherein the chip interconnection interface comprises a receiving buffer; In the data channel, an input end of the D flip-flop is connected with an output end of the receiving buffer, an output end of the D flip-flop is connected with a first input end of the two-way selector and the channel detection circuit, a second input end of the two-way selector is connected with an output end of the D flip-flop in the backup channel, and an output end of the two-way selector is connected with an internal digital circuit in the chip; In the backup channel, an input end of the D flip-flop is connected with an output end of the receiving buffer, and an output end of the D flip-flop is connected with the channel detection circuit. The chip further comprises a chip interconnection interface, a D flip-flop, a channel detection circuit in each of the signal channels, and a two-way selector in each of the data channels; wherein the chip interconnection interface comprises a receiving buffer; In the data channel, an input end of the D flip-flop is connected with an output end of the receiving buffer, an output end of the D flip-flop is connected with a first input end of the two-way selector and the channel detection circuit, a second input end of the two-way selector is connected with an output end of the D flip-flop in the backup channel, and an output end of the two-way selector is connected with an internal digital circuit in the chip; In the backup channel, an input end of the D flip-flop is connected with an output end of the receiving buffer, and an output end of the D flip-flop is connected with the channel detection circuit. The chip further

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