An avalanche tolerance test circuit and a test method thereof

Abstract

The application provides an avalanche tolerance test circuit and a test method thereof. The avalanche tolerance test circuit comprises a power supply, a bus capacitor and a test circuit connected with a device under test. The power supply is configured to charge the bus capacitor in a capacitor charging stage. The bus capacitor is configured to charge an inductor in the test circuit in an inductor charging stage. The test circuit is configured to disconnect the device under test from the power supply and the bus capacitor when the energy stored in the inductor reaches a preset target energy in the inductor charging stage, and to make the device under test in an avalanche state in an avalanche test stage until the current flowing through the device under test decreases to 0A. When the device under test is short-circuited or the avalanche voltage is abnormal during the process, the device under test is short-circuited and connected with a discharge resistor to release the energy stored in the inductor. The application realizes the failure protection of the device under test, so that the device under test subjected to the avalanche tolerance test is effectively protected after failure, and the analysis of the failed device under test is facilitated.

Description

[Technical Field]

[0001] This application relates to the field of power electronic device testing technology, and in particular to an avalanche tolerance testing circuit and its testing method. [Background Technology]

[0002] Power semiconductor devices are mainly used for power conversion and circuit control in power electronic equipment. In practical applications, not only does their main circuit contain inductance, but stray inductance is also distributed internally. When the power semiconductor device is turned off, the energy release path of the inductance is broken, causing the inductor to generate a high voltage applied to the turned-off power semiconductor device. When this high voltage exceeds a certain value, the power semiconductor device will enter an avalanche breakdown state. If the avalanche energy exceeds a certain value, the power semiconductor device will be completely damaged. Therefore, research on the avalanche tolerance of power semiconductor devices is essential. This is extremely important for analyzing the causes of avalanche failure in power semiconductor devices, optimizing the avalanche tolerance of power semiconductor devices from the circuit structure perspective, providing a reference for users to select power semiconductor devices, and providing ideas for manufacturers to develop a new generation of power semiconductor devices with excellent avalanche tolerance characteristics.

[0003] In related technologies, when testing power semiconductor devices using avalanche tolerance testing equipment, the equipment still has many drawbacks. For example, it cannot quickly dissipate the inductor's stored energy, making it impossible to effectively protect the tested power semiconductor device after failure, and may even damage the testing equipment. This is detrimental to the analysis of power semiconductor device failures and the effective protection of the testing equipment. It cannot achieve rapid fault response, which is also detrimental to the analysis of power semiconductor device failures and the effective protection of the testing equipment. It cannot achieve precise control of the inductor current within a single pulse. That is, it is necessary to wait for the power semiconductor device to cool down at certain intervals before controlling the pulse time, and it is necessary to repeat the avalanche tolerance test multiple times to gradually bring the inductor current close to the target value.

[0004] Therefore, it is necessary to improve the circuit structure of the aforementioned avalanche tolerance testing equipment. [Summary of the Invention]

[0005] This application provides an avalanche tolerance test circuit and test method, aiming to solve the problem that power semiconductor devices used in avalanche tolerance tests in related technologies cannot be effectively protected after failure.

[0006] To address the aforementioned technical problems, a first aspect of this application provides an avalanche tolerance test circuit, including a power supply, a bus capacitor, and a test circuit. The power supply is connected to the bus capacitor, the bus capacitor is connected to the test circuit, and the test circuit is used to connect to a device under test (DUT). The test circuit includes an inductor, and the gate drive voltage of the DUT is less than or equal to 0V. The avalanche tolerance test circuit performs tests on the DUT that include a capacitor charging stage, an inductor charging stage, and an avalanche test stage performed sequentially in time.

[0007] The power supply is used to charge the bus capacitors during the capacitor charging phase.

[0008] Bus capacitors are used to charge the inductor during the charging phase.

[0009] The test circuit is used to disconnect the device under test (DUT) from the power supply and bus capacitor during the inductor charging phase and when the inductor's stored energy reaches the preset target stored energy. During the avalanche test phase, the DUT is placed in an avalanche state until the current flowing through the DUT decreases to 0A. If the DUT breaks down or the avalanche voltage is abnormal during the process, the DUT is short-circuited and a discharge resistor is connected to release the energy stored in the inductor.

[0010] A second aspect of this application provides an avalanche tolerance testing method applied to an avalanche tolerance testing circuit. The avalanche tolerance testing circuit includes a power supply, a bus capacitor, and a testing circuit. The power supply is connected to the bus capacitor, which is connected to the testing circuit. The testing circuit is used to connect to a device under test (DUT). The testing circuit includes an inductor. The gate drive voltage of the DUT is less than or equal to 0V. The avalanche tolerance testing circuit tests the DUT by sequentially performing a capacitor charging stage, an inductor charging stage, and an avalanche testing stage. The avalanche tolerance testing method includes:

[0011] The power supply charges the bus capacitor during the capacitor charging phase.

[0012] The bus capacitor charges the inductor during the inductor charging phase;

[0013] During the inductor charging phase, when the inductor's stored energy reaches the preset target energy, the test circuit disconnects the device under test (DUT) from the power supply and bus capacitor. During the avalanche test phase, the DUT is placed in an avalanche state until the current flowing through the DUT decreases to 0A. If the DUT breaks down or the avalanche voltage is abnormal during the process, the DUT is short-circuited and a discharge resistor is connected to release the energy stored in the inductor.

[0014] As can be seen from the above description, compared with related technologies, the beneficial effects of this application are as follows:

[0015] An avalanche withstand capability test circuit is constructed using a power supply, a bus capacitor, and a test circuit. The test of the device under test (DUT) is divided into three phases: a capacitor charging phase, an inductor charging phase, and an avalanche test phase, performed sequentially. In practical applications, the power supply charges the bus capacitor during the capacitor charging phase; the bus capacitor charges the inductor during the inductor charging phase; during the inductor charging phase, when the inductor's stored energy reaches a preset target, the test circuit disconnects the electrical connection between the DUT and the power supply and the bus capacitor. During the avalanche test phase, the DUT is subjected to an avalanche state until the current flowing through it decreases to 0A. If the DUT experiences a short circuit or an abnormal avalanche voltage, the DUT is short-circuited and a discharge resistor is connected to release the energy stored in the inductor. Therefore, during the avalanche withstand test of the device under test (DUT), when the DUT breaks down short-circuit or the avalanche voltage is abnormal (i.e., when the DUT fails), this application can short-circuit the DUT and connect a discharge resistor to release the energy stored in the inductor, thus achieving failure protection for the DUT. This allows the DUT to be effectively protected after failure during the avalanche withstand test, which is beneficial for the analysis of the DUT after failure. [Attached Image Description]

[0016] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the principle of a traditional avalanche tolerance test topology;

[0018] Figure 2 A block diagram of the avalanche tolerance test circuit provided in an embodiment of this application;

[0019] Figure 3 A schematic diagram of a circuit structure for an avalanche tolerance test circuit provided in an embodiment of this application;

[0020] Figure 4 A timing diagram of the avalanche tolerance test circuit provided in an embodiment of this application;

[0021] Figure 5 A schematic diagram of another circuit structure for the avalanche tolerance test circuit provided in the embodiments of this application;

[0022] Figure 6 This is a flowchart illustrating the avalanche tolerance testing method provided in an embodiment of this application.

Detailed Implementation Methods

[0023] To make the objectives, technical solutions, and advantages of this application more apparent and understandable, this application will be clearly and completely described below with reference to the embodiments and corresponding drawings. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. It should be understood that the various embodiments of this application described below are only for explaining this application and are not intended to limit this application. That is, based on the various embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0024] Figure 1 This is a schematic diagram of the traditional avalanche tolerance test topology. The test process of the traditional avalanche tolerance test topology includes two stages. In the first stage, the switch Q1 and the device under test (DUT) are turned on, and the power supply VDD, the switch Q1, the inductor L and the DUT form a power loop (1). The power supply VDD charges the inductor L, and the current of the inductor L increases linearly. The magnitude of the current of the inductor L depends on the turn-on time of the switch Q1 and the DUT. In the second stage, the switch Q1 and the DUT are turned off, and the diode, the DUT and the inductor L form a power loop (2). At this time, the DUT enters the avalanche state. Traditional avalanche withstand testing topologies have several drawbacks. First, when the device under test (DUT) is short-circuited, the energy stored in the inductor L is dissipated through the diode, the DUT, the inductor L's resistance, and the loop resistance. This results in a prolonged energy dissipation time, exacerbating DUT damage and hindering post-DUT failure analysis. Second, when the DUT is open-circuited, extremely high voltages appear across its terminals, posing a significant risk of damage to the avalanche withstand test instrument. Third, the inductance value of the inductor L is unstable during avalanche withstand measurement, requiring real-time sampling to control the inductor L's current. This significant delay leads to poor accuracy in inductor current control.

[0025] Therefore, this application provides an avalanche tolerance testing circuit, the block diagram of which is shown below. Figure 2As shown, the avalanche withstand test circuit includes a power supply VCC, a bus capacitor C1, and a test circuit. The power supply VCC is connected to the bus capacitor C1, which is in turn connected to the test circuit. The test circuit connects to the device under test (DUT) and includes an inductor L1. The gate drive voltage of the DUT is less than or equal to 0V. The avalanche withstand test circuit tests the DUT through a sequentially occurring capacitor charging phase, inductor charging phase, and avalanche test phase. It should be noted that this embodiment does not impose special requirements on the power supply VCC or the bus capacitor C1. The power supply VCC can be selected to meet specific parameters (such as output voltage and voltage output accuracy) based on the actual application requirements. The capacitance of the bus capacitor C1 can be calculated based on the bus voltage drop rate, and a capacitor with low stray inductance is preferable for the application.

[0026] Specifically, the power supply VCC is used to charge the bus capacitor C1 during the capacitor charging phase; the bus capacitor C1 is used to charge the inductor L1 during the inductor charging phase; the test circuit is used to disconnect the device under test (DUT) from the power supply VCC and the bus capacitor C1 during the inductor charging phase and when the energy stored in the inductor L1 reaches the preset target energy storage; and during the avalanche test phase, the DUT is kept in an avalanche state until the current flowing through the DUT decreases to 0A. During this process, if the DUT experiences a short circuit or an abnormal avalanche voltage, the DUT is short-circuited and a discharge resistor is connected to release the energy stored in the inductor L1. Since the bus capacitor C1 has a sufficiently large capacitance, it can effectively maintain the bus voltage during the inductor charging phase.

[0027] Understandably, since the capacitor charging stage, inductor charging stage, and avalanche test stage are performed sequentially, in practical applications, the capacitor charging stage is performed first, that is, the bus capacitor C1 is charged through the power supply VCC; then, the inductor charging stage is performed, that is, the inductor L1 is charged through the bus capacitor C1 (at this time, the bus capacitor C1 has been fully charged), and when the energy stored in the inductor L1 reaches the preset target energy storage, the test circuit will disconnect the connection between the device under test (DUT) and the power supply VCC and the bus capacitor C1, which means that the DUT is about to enter the avalanche state; finally, the avalanche test stage is performed, that is, the test circuit makes the DUT officially enter the avalanche state until the current flowing through the DUT decreases to 0A, and during this process, if the DUT breaks down short-circuit or the avalanche voltage is abnormal, the test circuit will short-circuit the DUT and connect a discharge resistor to release the energy stored in the inductor L1.

[0028] As can be seen from the above, during the avalanche withstand test of the device under test (DUT), when the DUT breaks down short-circuit or the avalanche voltage is abnormal (i.e., when the DUT fails), the embodiments of this application can short-circuit the DUT and connect a discharge resistor to release the energy stored in the inductor L1, thus realizing the failure protection of the DUT. This allows the DUT to be effectively protected after failure during the avalanche withstand test, which is beneficial for the analysis of the DUT after failure.

[0029] In some implementations, please refer to further details. Figure 3 , Figure 3 This is a schematic diagram of a circuit structure for an avalanche tolerance test circuit provided in an embodiment of this application. Besides inductor L1, the test circuit includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a first resistor R1, a second resistor R2, a third resistor R3, and a diode D1. The first resistor R1 serves as the discharge resistor described above. One end of the bus capacitor C1 is connected to the drain of the first switch Q1, and the other end is connected to the anode of the diode D1. The source of the first switch Q1 and the cathode of the diode D1 are connected to one end of inductor L1, and the other end of inductor L1 is connected to the first switch Q2, a second switch Q2, a third switch Q3, a fourth switch Q4, a first resistor R1, a second resistor R2, a third resistor R3, and a diode D1. One end of resistor R1 is connected to the drain of the third switch Q3. The other end of resistor R1 is connected to the drain of the second switch Q2. The sources of the second switch Q2 and the third switch Q3 are connected to the drain of the fourth switch Q4. The source of the fourth switch Q4 is connected to one end of the second resistor R2. The other end of the second resistor R2 and the anode of diode D1 are used to connect to the device under test (DUT) through the third resistor R3. The sources of the second switch Q2 and the third switch Q3, and the drain of the fourth switch Q4 are used to connect to the DUT.

[0030] Specifically, during the inductor charging stage, the first switch Q1, the third switch Q3, and the fourth switch Q4 are turned on, and the bus capacitor C1 charges the inductor L1. When the energy stored in the inductor L1 reaches the preset target energy (equivalent to the current of the second resistor R2 reaching the preset target current), the first switch Q1 is turned off, the diode D1 is turned on, and the connection between the device under test (DUT) and the bus capacitor C1 and the power supply VCC is broken, meaning that the device under test (DUT) is about to enter the avalanche state. During the avalanche phase, the fourth switch Q4 is turned off, and the current flowing through it rapidly decreases and is transferred to the device under test (DUT). Simultaneously, since the gate drive voltage of the DUT is less than or equal to 0V, the DUT officially enters the avalanche state until the current flowing through the third resistor R3 decreases to 0A. During this process, if the DUT experiences a short circuit or an abnormal avalanche voltage, the third switch Q3 turns off, and the second and fourth switches Q2 and Q4 quickly turn on to release the energy stored in the inductor L1 through the first resistor R1 and short-circuit the DUT. Preferably, the inductor L1 is a variable inductor, and the first resistor R1 is a variable resistor.

[0031] It should be noted that the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 can all be power switches or mechanical switches, such as IGBTs (Insulated Gate Bipolar Transistors) or relays. Diode D1 can be a freewheeling diode or can be replaced by a power switch or a mechanical switch. The second resistor R2 and the third resistor R3 can both be sampling resistors or can be replaced by shunts.

[0032] In some implementations, see still Figure 2 The avalanche tolerance test circuit described above, in addition to the power supply VCC, bus capacitor C1, and test circuit, also includes a control circuit. This control circuit is connected to the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4. Its purpose is to control the on / off state of these four switches. The control circuit can control the on / off state of these switches via a driver. Figure 2 U1, U2, U3, and U4 in the diagram correspond to the drivers of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4, respectively. That is, the drive signal is output to the corresponding driver to drive the corresponding switch, thereby realizing the conduction and disconnection of the corresponding switch.

[0033] Furthermore, the control circuit is also connected to the second resistor R2, the third resistor R3, and the device under test (DUT). In this case, the control circuit is used to: acquire the voltage of the second resistor R2, and when the voltage of the second resistor R2 is greater than or equal to a preset first voltage threshold, control the first switch Q1 and the fourth switch Q4 to disconnect; acquire the voltage of the third resistor R3, and when the voltage of the third resistor R3 is greater than or equal to a preset second voltage threshold, control the first switch Q1 and the third switch Q3 to disconnect, and the second switch Q2 and the fourth switch Q4 to conduct. This setting allows for faster and more precise control of the inductor current. The control circuit can control the opening and closing of the DUT via a driver. Figure 2 U5 in the diagram corresponds to the driver of the device under test (DUT), which outputs a drive signal to the driver of the DUT to drive the DUT, thereby enabling the DUT to be turned on and off.

[0034] As one implementation method, please refer to [the relevant documentation]. Figure 2 The control circuit includes a control chip XP and a first comparator COMP1. The non-inverting input of the first comparator COMP1 is connected to the second resistor R2, and the inverting input and output of the first comparator COMP1 are connected to the control chip XP. The control chip XP is connected to the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4. Specifically, the first comparator COMP1 is used to acquire the voltage of the second resistor R2 and compare it with a preset first voltage threshold. When the comparison result of the first comparator COMP1 indicates that the voltage of the second resistor R2 is greater than or equal to the preset first voltage threshold, the control chip XP controls the first switch Q1 and the fourth switch Q4 to disconnect.

[0035] In this embodiment, the control chip XP can output a first voltage threshold to the first comparator COMP1 according to the user's settings. Then, the first comparator COMP1 samples the voltage on the second resistor R2 (or samples it after voltage division). When the current flowing through the second resistor R2 reaches the preset target value, the sampled voltage of the second resistor R2 is just greater than the first voltage threshold, causing the level of the first comparator COMP1 to flip (that is, the comparison result of the first comparator COMP1 is that the voltage of the second resistor R2 is greater than or equal to the first voltage threshold), and generating a level flip signal to the control chip XP. After receiving the level flip signal, the control chip XP outputs a drive signal to the first switch Q1 and the fourth switch Q4 to control the first switch Q1 and the fourth switch Q4 to disconnect.

[0036] As another implementation method, please refer to [the relevant documentation]. Figure 2The control circuit includes a control chip XP and a first comparator COMP1, as well as a second comparator COMP2. The non-inverting input of the second comparator COMP2 is connected to a third resistor R3, and the inverting input and output of the second comparator COMP2 are connected to the control chip XP. The control chip XP is connected to the device under test (DUT). Specifically, the second comparator COMP2 is used to acquire the voltage of the third resistor R3 and compare the voltage of the third resistor R3 with a preset second voltage threshold. When the comparison result of the second comparator COMP2 is that the voltage of the third resistor R3 is greater than or equal to the preset second voltage threshold, the control chip XP controls the first switch Q1 and the third switch Q3 to disconnect, and the second switch Q2 and the fourth switch Q4 to turn on.

[0037] In this embodiment, the control chip XP can output a second voltage threshold to the second comparator COMP2 according to the user's settings. Then, the second comparator COMP2 samples the voltage on the third resistor R3 (or it can be sampled after voltage division). When the current flowing through the third resistor R3 reaches the preset target value, the sampled voltage of the third resistor R3 is just greater than the second voltage threshold, causing the level of the second comparator COMP2 to flip (that is, the comparison result of the second comparator COMP2 is that the voltage of the third resistor R3 is greater than or equal to the second voltage threshold), and generating a level flip signal to the control chip XP. After receiving the level flip signal, the control chip XP outputs a drive signal to the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 to control the first switch Q1 and the third switch Q3 to be disconnected and the second switch Q2 and the fourth switch Q4 to be turned on.

[0038] It should be noted that the above-described embodiments are merely preferred implementations of the present application, and are not the only limitation on the specific circuit structure and control logic of the test circuit and control circuit; those skilled in the art can make flexible settings based on the embodiments of the present application and according to the actual application scenario.

[0039] In summary, this application provides an avalanche tolerance test circuit that provides failure protection for the device under test (DUT). This ensures effective protection of the DUT after failure, facilitating post-failure analysis. Furthermore, it enables faster and more precise control of the inductor current, meeting the accuracy requirements of avalanche tolerance measurement. The timing diagram of this avalanche tolerance test circuit can be found in [reference needed]. Figure 4 ,exist Figure 4In the diagram, Q4_PWM represents the drive signal output from the control chip XP to the fourth switch Q4, IL represents the current in inductor L1, I_R3 represents the current in the third resistor R3, and V_DUT represents the voltage of the device under test (DUT). Furthermore, if the measurement accuracy of avalanche energy is not considered, or if driving the DUT is not considered, the circuit structure of this avalanche withstand capability test circuit can be simplified as follows: Figure 5 As shown.

[0040] Figure 6 This is a flowchart illustrating the avalanche tolerance testing method provided in an embodiment of this application. This application also provides an avalanche tolerance testing method based on the avalanche tolerance testing circuit described above, which includes the following steps 601 to 603.

[0041] Step 601: The power supply charges the bus capacitor during the capacitor charging stage.

[0042] In this embodiment of the application, the avalanche tolerance test of the device under test (DUT) is divided into three stages: capacitor charging stage, inductor charging stage and avalanche test stage. The capacitor charging stage, inductor charging stage and avalanche test stage are performed sequentially. Therefore, the capacitor charging stage needs to be performed first, that is, the bus capacitor C1 is charged through the power supply VCC.

[0043] Step 602: The bus capacitor charges the inductor during the inductor charging stage.

[0044] In this embodiment of the application, after the capacitor charging stage is completed, the inductor charging stage is also required, that is, the inductor L1 is charged through the bus capacitor C1, and when the energy stored in the inductor L1 reaches the preset target energy, the test circuit will disconnect the device under test (DUT) from the power supply VCC and the bus capacitor C1, which means that the device under test (DUT) is about to enter the avalanche state.

[0045] Step 603: During the inductor charging phase and when the inductor's stored energy reaches the preset target energy, the test circuit disconnects the device under test from the power supply and the bus capacitor. During the avalanche test phase, the device under test is placed in an avalanche state until the current flowing through the device under test decreases to 0A. If the device under test breaks down or the avalanche voltage is abnormal during the process, the device under test is short-circuited and a discharge resistor is connected to release the energy stored in the inductor.

[0046] In this embodiment, after the inductor charging stage is completed, an avalanche test stage is required. That is, the test circuit makes the device under test (DUT) officially enter the avalanche state until the current flowing through the DUT decreases to 0A. During this process, if the DUT breaks down or the avalanche voltage is abnormal, the test circuit will short-circuit the DUT and connect a discharge resistor to release the energy stored in the inductor L1.

[0047] As can be seen from the above, during the avalanche withstand test of the device under test (DUT), when the DUT breaks down short-circuit or the avalanche voltage is abnormal (i.e., when the DUT fails), this avalanche withstand test method can short-circuit the DUT and connect a discharge resistor to release the energy stored in the inductor L1, thus achieving failure protection for the DUT. This ensures that the DUT undergoing avalanche withstand test can be effectively protected after failure, which is beneficial for the analysis of the DUT after failure.

[0048] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For product-related embodiments, since they are similar to method-related embodiments, the descriptions are relatively simple, and relevant parts can be referred to the descriptions of the method-related embodiments.

[0049] It should also be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0050] The above description of the disclosed embodiments enables those skilled in the art to implement or use the content of this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this application may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An avalanche tolerance test circuit, characterized by, The power supply, the bus capacitor and the test circuit are connected, the bus capacitor is connected to the test circuit, the test circuit is used for connecting the device under test, the test circuit includes an inductor, the gate drive voltage of the device under test is less than or equal to 0V, and the avalanche resistance test circuit includes a capacitive charging phase, an inductive charging phase and an avalanche test phase in time sequence. The power supply is used for charging the bus capacitor in the capacitive charging phase; The bus capacitor is used for charging the inductor in the inductive charging phase; The test circuit is used for disconnecting the device under test from the power supply and the bus capacitor when the energy storage of the inductor reaches a preset target energy storage in the inductive charging phase, and making the device under test in an avalanche state in the avalanche test phase until the current flowing through the device under test reduces to 0A, and in the process, when the device under test is short-circuited or the avalanche voltage is abnormal, the device under test is short-circuited and a discharge resistor is connected to release the energy stored in the inductor. The test circuit further includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first resistor, a second resistor, a third resistor and a diode, one end of the bus capacitor is connected to the drain of the first switch tube, the other end is connected to the anode of the diode, the source of the first switch tube and the cathode of the diode are connected to one end of the inductor, the other end of the inductor is connected to one end of the first resistor and the drain of the third switch tube, the other end of the first resistor is connected to the drain of the second switch tube, the sources of the second switch tube and the third switch tube are connected to the drain of the fourth switch tube, the source of the fourth switch tube is connected to one end of the second resistor, the other end of the second resistor and the anode of the diode are used for connecting the device under test through the third resistor, and the sources of the second switch tube and the third switch tube and the drain of the fourth switch tube are used for connecting the device under test. In the inductive charging phase, the first switch tube, the third switch tube and the fourth switch tube are turned on, the bus capacitor charges the inductor, and when the energy storage of the inductor reaches a preset target energy storage, the first switch tube is disconnected, the diode is turned on, and the connection between the device under test and the bus capacitor and the power supply is disconnected. In the avalanche test phase, the fourth switch tube is disconnected, the current flowing through the fourth switch tube is reduced and transferred to the device under test, so that the device under test is in an avalanche state until the current flowing through the third resistor reduces to 0A, and in the process, when the device under test is short-circuited or the avalanche voltage is abnormal, the third switch tube is disconnected, the second switch tube and the fourth switch tube are turned on, so that the energy stored in the inductor is released through the first resistor and the device under test is short-circuited, wherein the first resistor serves as the discharge resistor.

2. The avalanche tolerance test circuit of claim 1, wherein, The control circuit is connected to the first switch tube, the second switch tube, the third switch tube and the fourth switch tube, and is used for controlling the conduction and disconnection of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube.

3. The avalanche tolerance test circuit of claim 2, wherein, The control circuit is also connected to the second resistor, the third resistor and the measured device, and is also used for: collecting the voltage of the second resistor, and controlling the first switch tube and the fourth switch tube to be disconnected when the voltage of the second resistor is greater than or equal to a preset first voltage threshold; collecting the voltage of the third resistor, and controlling the first switch tube and the third switch tube to be disconnected and the second switch tube and the fourth switch tube to be connected when the voltage of the third resistor is greater than or equal to a preset second voltage threshold.

4. The avalanche tolerance test circuit of claim 3, wherein, The control circuit includes a control chip and a first comparator, wherein the non-inverting input terminal of the first comparator is connected to the second resistor, the inverting input terminal and the output terminal of the first comparator are connected to the control chip, and the control chip is connected to the first switch tube, the second switch tube, the third switch tube and the fourth switch tube; wherein: the first comparator is used for collecting the voltage of the second resistor and comparing the voltage of the second resistor with a preset first voltage threshold; the control chip is used for controlling the fourth switch tube to be disconnected when the comparison result of the first comparator is that the voltage of the second resistor is greater than or equal to the preset first voltage threshold.

5. The avalanche tolerance test circuit of claim 4, wherein, The control circuit also includes a second comparator, the non-inverting input terminal of the second comparator is connected to the third resistor, the inverting input terminal and the output terminal of the second comparator are connected to the control chip, and the control chip is connected to the measured device; wherein: the second comparator is used for collecting the voltage of the third resistor and comparing the voltage of the third resistor with a preset second voltage threshold; the control chip is used for controlling the measured device to be turned off when the comparison result of the second comparator is that the voltage of the third resistor is greater than or equal to the preset second voltage threshold.

6. The avalanche tolerance test circuit of claim 1, wherein, The inductor is a variable inductor, and the first resistor is a variable resistor.

7. The avalanche tolerance test circuit of claim 1, wherein, The second resistor and / or the third resistor is replaced by a shunt.

8. The avalanche tolerance test circuit of claim 1, wherein, The diode is replaced by an IGBT.

9. An avalanche withstand test method applied to the avalanche withstand test circuit according to any one of claims 1 to 8, characterized by, The avalanche resistance test circuit includes a power supply, a bus capacitor and a test circuit, the power supply is connected to the bus capacitor, the bus capacitor is connected to the test circuit, the test circuit is used for connecting a measured device, the test circuit includes an inductor, the gate drive voltage of the measured device is less than or equal to 0V, and the test of the measured device by the avalanche resistance test circuit includes a capacitor charging stage, an inductor charging stage and an avalanche test stage which are sequentially performed in time sequence. The avalanche resistance test method includes: the power supply charges the bus capacitor in the capacitor charging stage; the bus capacitor charges the inductor in the inductor charging stage; The test circuit disconnects the DUT from the power supply and the bus capacitor when the energy stored in the inductor reaches a preset target energy during the inductor charging phase, and causes the DUT to be in an avalanche state during the avalanche test phase until the current flowing through the DUT decreases to 0A, and in the process, when the DUT breaks down, shorts or the avalanche voltage is abnormal, the DUT is short-circuited and a discharge resistor is connected to release the energy stored in the inductor.

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