PCBA circuit failure mode and influence analysis method
By defining functional interfaces in PCBA circuits and establishing a bottom-up failure mode mapping, the problem of inconsistent failure mode representation is solved, and the effectiveness and accuracy of the analysis are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUNAN GINGKO RELIABILITY TECH RES INST CO LTD
- Filing Date
- 2022-10-25
- Publication Date
- 2026-07-24
AI Technical Summary
In the existing technology, the expression of failure modes of PCBA circuits is inconsistent and lacks standardization, which leads to loopholes in failure mode analysis and affects the effectiveness of the analysis.
By obtaining the input, output, and ground terminals of each stage of the PCBA circuit as functional interfaces, failure modes are listed according to reference standards, and a bottom-up failure mode mapping is established up to the highest level. Similar modes are merged to determine the fault mode.
This achieves a unified and quantifiable representation of PCBA circuit failure modes, improving the effectiveness and accuracy of failure mode and effect analysis.
Smart Images
Figure CN115902578B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of PCBA circuit failure mode analysis technology, and in particular to a PCBA circuit failure mode and effect analysis method. Background Technology
[0002] Failure Mode and Effects Analysis (FMEA), also known as Potential Failure Mode and Effects Analysis, is a quantitative and qualitative analytical method that analyzes and assesses the potential (and / or already occurring) consequences of possible (and / or already occurring) failure modes, and the degree of risk associated with those consequences. Furthermore, based on the predicted risk level, targeted improvements can be implemented, achieving a proactive prevention and improvement approach. Effective implementation of FMEA can shorten development time and costs, improve product quality, and enhance product reliability and safety.
[0003] Failure Mode and Effects Analysis (FMEA) of electronic circuits begins with analyzing various failure modes of a specific circuit. This involves accurately representing and deeply analyzing the various phenomena that may occur when a circuit fails. Correctly listing all failure modes is a prerequisite for FMEA. In practice, many failure mode representations are incorrect. For example, an incorrect external input to the analyzed object may be considered a failure mode; a failure mode of a component, device, or part within the analyzed object may be considered the failure mode of the analyzed object itself; the cause of the failure may be considered the failure mode; and failure modes may be expressed too generally or overlap. Incomplete or inaccurate failure mode listings can lead to undetected potential failure modes, resulting in gaps in FMEA and rendering it ineffective. Furthermore, the lack of appropriate reference standards in practice means that comprehensively and correctly listing failure modes relies heavily on the individual technical experience of engineers. Even for the same analyzed object, different engineers may express failure modes with subtle differences.
[0004] With the increasing trend towards circuit integration, integrated packaged circuits are widely used. Due to the manufacturing process of integrated packaged components, users do not need to pay much attention to their internal structure, but only to their performance and function, which are manifested through the input and output signals on the functional interface. In PCBA circuit design, circuit modules are also divided according to function, especially as circuit designs become more complex.
[0005] Therefore, based on the existing failure mode and effect analysis of PCBA electronic products, how to ensure the uniformity of its failure mode expression, and thus improve the effectiveness of the failure mode and effect analysis of electronic circuits, has become an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0006] In view of the above problems, the present invention proposes a PCBA circuit failure mode and effect analysis method that at least solves some of the above technical problems. This method can effectively ensure the uniformity of PCBA circuit failure mode expression and significantly improve the operability of failure mode quantification.
[0007] This invention provides a method for analyzing failure modes and effects of PCBA circuits, including:
[0008] Obtain the input terminals, output terminals, and ground terminals of each stage of the PCBA circuit to be analyzed; and use the input terminals, output terminals, and ground terminals of each stage as the functional interfaces of each stage; each stage of the PCBA circuit to be analyzed refers to the components or unit circuits of the PCBA circuit to be analyzed.
[0009] Taking the functional interfaces at each level as the analysis object, and based on the reference standard, completely list and output the failure modes of the functional interfaces at each level;
[0010] Based on the failure modes of the functional interfaces at each level, starting from the lowest level of the PCBA circuit to be analyzed, a failure mode mapping is established from each level of functional interface to the next level of functional interface, up to the highest level.
[0011] By merging the same failure modes from each functional interface to the functional interface of the next higher level, the failure modes of the PCBA circuit to be analyzed caused by internal circuit failure are obtained.
[0012] Based on the described failure modes, an impact analysis is performed on the PCBA circuit to be analyzed.
[0013] Furthermore, based on the failure modes of the functional interfaces at each level, starting from the lowest level of the PCBA circuit to be analyzed, a failure mode mapping is established from each level's functional interface to the next level's functional interface, up to the highest level, including:
[0014] Based on the failure modes of the functional interfaces at each level, starting from the lowest level of the PCBA circuit to be analyzed, the failure modes of all functional interfaces at that level are listed and their impact on the functional interfaces at the next higher level is analyzed, up to the highest level.
[0015] Furthermore, the hierarchy, from lowest to highest, is: component level, unit circuit level, and system circuit level.
[0016] Furthermore, the reference standard is:
[0017] When there is an open circuit with no signal input or a short circuit to ground at the input terminal of each level, it is determined that there is a corresponding failure mode.
[0018] When the output signal of each stage is a substandard signal, it is determined that there is a corresponding failure mode. The substandard signals include: no output signal, intermittent no output signal, output signal deviation, excessive output signal deviation, output signal with undesirable delay, excessive output signal fluctuation, incomplete output signal, and output signal error.
[0019] When an open circuit exists at the grounding terminal of any of the aforementioned levels, it is determined that a corresponding failure mode exists.
[0020] Furthermore, when each stage of the PCBA circuit to be analyzed consists of individual components of the PCBA circuit to be analyzed, the failure modes expressed by the component's own characteristic parameters are used instead of the failure modes expressed by the functional interface.
[0021] Furthermore, the failure mode from each functional interface to the next functional interface is either a one-to-one relationship or a one-to-many relationship.
[0022] Furthermore, when the failure mode from each functional interface to the next functional interface is a one-to-many relationship, the failure mode of the next level can be obtained through superposition analysis.
[0023] The beneficial effects of the above-described technical solutions provided in the embodiments of the present invention include at least the following:
[0024] This invention provides a method for PCBA circuit failure mode and effect analysis, comprising: acquiring the input terminals, output terminals, and ground terminals of each stage of the PCBA circuit to be analyzed, as functional interfaces of each stage; taking each functional interface as the analysis object, and completely listing the failure modes of each functional interface according to a reference standard; starting from the lowest level of the PCBA circuit to be analyzed, establishing a failure mode mapping from each level's functional interface to the next level's functional interface, up to the highest level; merging the same failure modes from each level's functional interface to the next level's functional interface to obtain the failure modes of the PCBA circuit to be analyzed caused by internal circuit failure; and performing impact analysis on the PCBA circuit to be analyzed based on the failure modes. This method ensures the uniformity of PCBA circuit failure mode expression, improves the operability of failure mode quantification, and thus significantly improves the effectiveness of PCBA circuit failure mode and effect analysis in practical applications.
[0025] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.
[0026] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0027] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0028] Figure 1 This is a flowchart of the PCBA circuit failure mode and effect analysis method provided in the embodiments of the present invention;
[0029] Figure 2 The circuit functional interface logic structure diagram provided in the embodiments of the present invention;
[0030] Figure 3 This is an example of the internal structure diagram of a 12V to 5V DC power supply unit circuit provided in an embodiment of the present invention;
[0031] Figure 4 This is a unit function interface diagram provided for an embodiment of the present invention. Detailed Implementation
[0032] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0033] This invention provides a method for analyzing the failure modes and effects of PCBA circuits, referring to... Figure 1 As shown, it includes:
[0034] Obtain the input, output, and ground terminals of each stage of the PCBA circuit to be analyzed; and use the input, output, and ground terminals of each stage as the functional interfaces of each stage; each stage of the PCBA circuit to be analyzed refers to the individual components or unit circuits of the PCBA circuit to be analyzed.
[0035] Taking the functional interfaces at each level as the analysis objects, and based on the reference standards, completely list and output the failure modes of the functional interfaces at each level;
[0036] Based on the failure modes of each functional interface, starting from the lowest level of the PCBA circuit to be analyzed, a failure mode mapping is established from each functional interface to the functional interface of the next higher level, up to the highest level.
[0037] By merging the same failure modes from each functional interface level to the functional interface level above, we can obtain the failure modes of the PCBA circuit under analysis caused by internal circuit failure.
[0038] Based on the failure modes, an impact analysis is performed on the PCBA circuit to be analyzed.
[0039] The PCBA circuit failure mode and effect analysis method provided in the embodiments ensures the uniformity of failure mode expression, improves the operability of failure mode quantification, and thus improves the effectiveness of PCBA circuit failure mode and effect analysis in practical applications.
[0040] Specifically, in circuit design, a three-layer structure can be established. Components form unit circuits with specific functions, and these unit circuits then form system circuits to realize the system functions. For PCBA circuit boards, components, unit circuits, and system circuits all have functional interfaces for external connections to realize and express their functions. That is, in actual circuit connections, each functional interface performs a specific function.
[0041] Specifically, this embodiment adopts the following... Figure 2 The circuit functional interface logic structure shown is used for energy transmission or information transmission. All functions of components, unit circuits and system circuits are reflected in the functional interfaces.
[0042] Specifically, a functional interface is essentially the external interface for function implementation and output. From the perspective of the circuit output terminal, the output signal carries the functional output of the component, unit, and system; from the perspective of the circuit input terminal and ground terminal, the input terminal is used for signal input, and the ground terminal is used for grounding, both contributing to the realization of the function. Therefore, the input, output, and ground terminals can be considered as functional interfaces, which are essentially the external interfaces for functional output. Thus, when performing failure mode and effects analysis, the functional interfaces at each level that perform specific functions can be directly used as the analysis objects, establishing a failure mode mapping between functional interfaces at each level to reflect the failure mode relationships of electronic components and various circuits.
[0043] Specifically, this embodiment executes a bottom-up logical analysis structure, which ensures a complete enumeration of system failure modes. It enumerates the failure modes of all functional interfaces at the next lower level and analyzes their impact on functional interfaces at the previous level, i.e., the mapping relationship between the failure modes of functional interfaces at the next and previous levels (the failure of a functional interface at the next lower level will inevitably cause the failure of a certain functional interface at the previous level, which is determined by the circuit structure). Then, the failure modes of the same functional interfaces at the previous level are merged. After merging, all failure modes at the previous level are enumerated, as shown in Table 1. The failure modes of each functional interface of unit circuits A, B, C, and D correspond to the failure modes of the functional interfaces of system M. After complete enumeration, 11 failure modes caused by internal circuit failures are found in the system.
[0044] Table 1 - Failure Mode Logical Mapping of Unit-System Functional Interfaces
[0045]
[0046] In Table 1 above, A1 indicates energy output failure; A3 indicates information transmission failure; A4 indicates grounding failure; A5 indicates energy input failure; P01 indicates one energy output failure; M01 indicates the functional interface failure mode of system M; and M02 is a combination of P02, P03, P04, P05, P06, and P07. Optionally, analysts can define the names as needed, but the meaning is a combination of these interface failure modes.
[0047] Specifically, the failure of a device's functional interface is the failure of the device itself (component). The failure of a system or unit circuit is either the failure of a single functional interface or a combination of failures of multiple functional interfaces. In practical applications, a functional interface may have 1, 2, 3, or even more failure modes. The mapping of functional interface failure modes is shown in Table 2 below.
[0048] Table 2 - Specific Mapping of Failure Modes for Unit-Specific System Functional Interfaces
[0049]
[0050] In Table 2 above, A01-1 indicates no energy output; A01-2 indicates intermittent energy output; A01-3 indicates low energy output; A03-1 indicates no information output; A03-2 indicates no information input; and A03-3 indicates incorrect information output.
[0051] When performing three-level failure mode and effect analysis (FMEA) for components, units, and systems, the failure modes of unit circuits are obtained after mapping the failure modes of functional interfaces at the component and unit levels. When mapping failure modes at the unit and system levels, the failure mapping relationship between unit functional interfaces and system functional interfaces is first established using functional interfaces as the direct analysis object. Then, based on the failure modes determined by the combination of unit-level functional interface failure modes for the determined unit-level circuits, a matching analysis is performed on the combination of system-level functional interfaces to determine the system's failure modes. If the three-level functional interface failure mapping for a specific system circuit is as shown in Table 3, then the three-level structural failure mapping for this system circuit can be shown in Table 4. Furthermore, the logic for more complex hierarchical structure analysis follows the same pattern.
[0052] Table 3 Examples of Failure Mode Mapping for Functional Interfaces at Various Levels in a Certain System
[0053]
[0054] Table 4. Three-level fault mode mapping for a certain system
[0055] C01 X01 Y01(U01, U02) C02 X02 Y02(U02, U03) C03 X02 Y02(U02, U03) C04 X03 Y03(U04, U05) C05 X03 Y03(U04, U05)
[0056] Furthermore, the identification and expression of functional interface failure modes are based on reference standards, with specific expressions implemented. From the perspective of circuit functional interfaces, the output terminal and ground terminal can essentially be considered interfaces with connection functions. The input terminal receives the input signal, and the ground terminal connects to ground; both serve as the stimuli and conditions for functional operation. Therefore, the circuit input terminal, as a connection functional interface, only has two failure modes: open circuit and short circuit to ground, resulting in no signal input; no other failure modes need to be considered. The ground terminal is considered for whether it is grounded, i.e., whether the grounding functional interface is open-circuited. The output functional interface is judged by whether its output signal meets the standards. According to the output signal performance requirements, it can be classified into seven categories: no output, intermittent no output, output bias or excessive deviation, output with undesirable delay, excessive output fluctuation, incomplete output, and output error.
[0057] In practical applications, the specific expression of failure modes should be determined based on the corresponding signal performance parameter standards under different environments and usage conditions, combined with the given failure mode classification (a classification derived from summarizing the non-compliant manifestations of circuit output signals). Examples include the parameter values and standard classifications for parameters such as no 12V output or output voltage deviation exceeding 5%. For some discrete components, whose structures are simple, using their corresponding characteristic values to directly express their failure modes is more suitable for common practice. The expression of their failure modes can be adaptively adjusted, using the component's own characteristic parameters to express failure instead of the functional interface concept. However, this expression transformation still corresponds to the functional interface failure mode expression reference standard. For example, for resistors, resistance drift corresponds to output bias or excessive deviation; for capacitors, capacitance change also corresponds to output bias or excessive deviation. Therefore, the specific expression methods may differ, but the internalized reference standard remains consistent. Furthermore, referring to the given standard to list failure modes can reduce omissions.
[0058] Specifically, the failure modes of functional interfaces may not be in a one-to-one correspondence, but rather a one-to-many relationship, resulting in combinations of various interface failure modes, i.e., different unit or system-level failure modes. Failure mapping relationships are divided into interface failure mapping relationships and hierarchical failure mapping relationships. When analyzing hierarchical failure mapping relationships, the entire hierarchical circuit is considered as the analysis object. A single functional interface failure at a lower level corresponds to the failure of one or more functional interfaces at a higher level. If a certain failure mode at a lower level contains multiple functional interface failure modes, the failure mode at the higher level can be obtained through superposition analysis.
[0059] Optionally, according to the specific analysis process of the method provided in this embodiment, the actual analysis personnel need to rely on the circuit diagram to analyze the functional interface connection, and then conduct a specific analysis of the failure mode of the PCBA circuit.
[0060] The method provided in this embodiment is illustrated below through a specific practical application example:
[0061] Reference Figure 3 The diagram shows the internal structure of a power supply unit circuit for a 12V to 5V DC voltage conversion example. The internal components include integrated devices (voltage conversion chip IC) and discrete components (resistors R1, R2, and capacitor C2). Figure 3 It can be seen that this unit circuit has four external functional interfaces, namely V1, V2, GND1, and GND2. Therefore, the functional interfaces of this unit can be obtained as follows: Figure 4 As shown.
[0062] Device Failure Modes and Examples. Integrated circuit devices (voltage conversion chips, ICs) have four functional interfaces: interfaces 2 and 4 are for grounding, and interfaces 1 and 3 are for voltage input and output. According to reference standards, the failure modes of interfaces 2 and 4 are open circuits; the failure modes of interface 1 are open circuits and short circuits to ground; and the failure modes of interface 3 are no voltage output, intermittent voltage output, low output voltage (below a certain standard threshold), and high output voltage (above a certain standard threshold). Similarly, according to reference standards, the failure modes of discrete components R1 and R2 are open circuits, short circuits, and resistance values that are too high / too low (high / below a certain threshold); the failure modes of capacitor C2 are open circuits, short circuits, and capacitance values that are too high / too low (high / below a certain threshold).
[0063] Failure modes of the unit circuit functional interfaces are described and listed. The V2 functional interface of this unit circuit is used for 5V voltage output. By referring to the reference standard, its failure modes can be determined as follows: no 5V voltage output, intermittent 5V voltage output, excessive 5V voltage fluctuation (exceeding a certain limit), output voltage below 5V, and output voltage above 5V. The GND1 and GND2 functional interfaces are used for grounding, and their failure mode is floating ground (open circuit).
[0064] Establish a failure mode mapping relationship. Unit-level failure modes are composed of failure modes from unit-level functional interfaces. Failure mode mapping between different levels can be completed based on the functional interface failure mode mapping. The failure mode mapping relationship for this voltage conversion unit, analyzed and constructed in conjunction with the unit structure diagram, is shown in Table 5. Table 5 shows that the unit failure modes mapped from internal devices are M1, M2, M3, M4, M5, M6, and M7. These seven unit failure modes are derived from the unit functional interface failure modes. Regardless of how a unit failure mode is described, it always corresponds to a specific functional interface failure.
[0065] Table 5 Unit Fault Mode Mapping
[0066]
[0067]
[0068] The PCBA circuit failure mode and effect analysis method provided in this embodiment offers a new approach to optimizing the practical application of PCBA electronic product failure mode and effect analysis. It generally focuses on the functional interfaces implemented by each level of the PCBA circuits as the objects of failure mode and effect analysis, establishing a failure mode mapping structure from components to unit circuit functional interfaces and then to system functional interfaces. A bottom-up analysis approach is adopted, first analyzing the failure modes of component functional interfaces, then analyzing the possible failure modes of unit functional interfaces, and finally analyzing the possible failure modes of system functional interfaces, thereby determining the failure mode mapping relationship from components to unit circuits and then to the system.
[0069] This embodiment provides a standardized reference method for expressing failure modes at various functional interfaces of PCBA circuits, greatly improving the accuracy, standardization, and referenceability of PCBA failure mode expression, and ensuring a complete and effective enumeration of failure modes for devices, units, and system circuits. This helps reduce the complexity of implementing PCBA circuit failure mode and effect analysis, and improves the efficiency, effectiveness, and standardization of the PCBA circuit failure mode and effect analysis process.
[0070] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for analyzing failure modes and effects of PCBA circuits, characterized in that, include: Obtain the input terminals, output terminals, and ground terminals of each stage of the PCBA circuit to be analyzed; and use the input terminals, output terminals, and ground terminals of each stage as the functional interfaces of each stage; Each level of the PCBA circuit to be analyzed refers to the individual components or unit circuits of the PCBA circuit to be analyzed. Taking the functional interfaces at each level as the analysis object, and based on the reference standard, completely list and output the failure modes of the functional interfaces at each level; The failure mode of each level of functional interface to the next level of functional interface is either a one-to-one relationship or a one-to-many relationship. When the failure mode from each functional interface to the next functional interface is a one-to-many relationship, the failure mode of the next level can be obtained through superposition analysis. Based on the corresponding signal performance parameter standard requirements under different environments and usage conditions, and combined with the classification obtained by summarizing the non-compliant manifestations of circuit output signals, the specific failure mode standard expression is determined. Based on the failure modes of the functional interfaces at each level, starting from the lowest level of the PCBA circuit to be analyzed, a failure mode mapping is established from each level of functional interface to the next level of functional interface, up to the highest level. Based on the failure modes of the functional interfaces at each level, starting from the lowest level of the PCBA circuit to be analyzed, the failure modes of all functional interfaces at that level are listed and their impact on the functional interfaces at the next higher level is analyzed, up to the highest level. The hierarchy, from lowest to highest, is: component level, unit circuit level, and system circuit level; By merging the same failure modes from each functional interface to the functional interface of the next higher level, the failure modes of the PCBA circuit to be analyzed caused by internal circuit failure are obtained. Based on the described failure modes, an impact analysis is performed on the PCBA circuit to be analyzed.
2. The PCBA circuit failure mode and effect analysis method as described in claim 1, characterized in that, The reference standard is as follows: When there is an open circuit with no signal input or a short circuit to ground at the input terminal of each level, it is determined that there is a corresponding failure mode. When the output signal of each stage is a substandard signal, it is determined that there is a corresponding failure mode. The substandard signals include: no output signal, intermittent no output signal, output signal deviation, excessive output signal deviation, output signal with undesirable delay, excessive output signal fluctuation, incomplete output signal, and output signal error. When an open circuit exists at the grounding terminal of any of the aforementioned levels, it is determined that a corresponding failure mode exists.
3. The PCBA circuit failure mode and effect analysis method as described in claim 1, characterized in that, When each stage of the PCBA circuit to be analyzed consists of its own components, the failure modes expressed by the component's own characteristic parameters are used instead of those expressed by the functional interface.