Display panel, circuit board and display device

Abstract

Embodiments of the present application provide a display panel, a circuit board and a display device. The display panel comprises a substrate; a plurality of first signal lines arranged on one side of the substrate, and a projection of at least one first signal line on the substrate is located in a fan-out area and a binding area; a first binding structure arranged on the same side of the substrate as the first signal lines, and a projection of the first binding structure on the substrate is located in the binding area; wherein: the first binding structure comprises a plurality of first binding pin groups, and the plurality of first binding pin groups are arranged in sequence along a first direction; each first binding pin group comprises at least one first binding pin, and the first signal lines are connected to the at least one first binding pin in correspondence; the first binding pin has a first preset included angle between an extension direction and a second direction, and the second direction is perpendicular to the first direction. Through the technical scheme of the embodiments of the present application, the width of the arrangement space of the first signal lines and the first binding pins can be effectively reduced, and the display product can obtain a narrow frame.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a circuit board, and a display device. Background Technology

[0002] Currently, large-size display panels are gradually moving towards BDL (borderless) and SNB (super narrow bezel), and customers' demand for ultra-narrow bezels is increasing day by day. Summary of the Invention

[0003] This application proposes a display panel, circuit board, and display device that can effectively reduce the width of the arrangement space of the first signal line and the first bonding pin, thereby enabling the display product to achieve a narrow bezel.

[0004] In a first aspect, embodiments of this application provide a display panel, including a substrate, the substrate having a display area and a border area located on at least one side of the display area, the border area including a fan-out area and a bonding area, and further including: a plurality of first signal lines disposed on one side of the substrate, and the orthographic projection portion of at least one first signal line on the substrate located in the fan-out area and the bonding area; a first bonding structure disposed on the same side of the substrate as the first signal lines, and the orthographic projection of the first bonding structure on the substrate located in the bonding area; wherein: the first bonding structure includes a plurality of first bonding pin groups, the plurality of first bonding pin groups being sequentially disposed along a first direction; the first bonding pin group includes at least one first bonding pin, and the first signal lines are correspondingly connected to at least one first bonding pin; the extension direction of the first bonding pin has a first preset angle with a second direction, the second direction being perpendicular to the first direction.

[0005] Optionally, the first binding pin group includes multiple first binding pins, and the multiple first binding pins of each first binding pin group are arranged sequentially along the second direction, and there is a preset distance between two adjacent first binding pins.

[0006] Optionally, the length of the first bonding pin group along the second direction is less than or equal to the length of the first bonding pin along the extension direction of the first bonding pin.

[0007] Optionally, each first bonding pin group includes the same number of first bonding pins; or, at least one first bonding pin group includes a different number of first bonding pins than the other first bonding pin groups, and along the first direction, from the edge of the bonding area to the center, the number of first bonding pins in each first bonding pin group increases.

[0008] Optionally, a plurality of first binding pin groups are arranged sequentially at intervals along a first direction, and along the first direction, there is a preset distance between two adjacent first binding pin groups, the preset distance being greater than or equal to 25 micrometers and less than or equal to 35 micrometers; and / or, the first preset included angle is greater than 0° and less than 180°.

[0009] Optionally, the bezel area further includes a circuit area, and the circuit area and the fan-out area surround the periphery of the display area; the display panel further includes a gate driving circuit and a pixel circuit, the gate driving circuit is disposed on one side of the substrate and its orthographic projection on the substrate is located in the circuit area, the pixel circuit is disposed on one side of the substrate and its orthographic projection on the substrate is located in the display area; the display panel further includes a second signal line and a second bonding pin, both the second signal line and the second bonding pin are disposed on one side of the substrate, and the orthographic projection of the second signal line on the substrate is located in the fan-out area, the orthographic projection of the second bonding pin on the substrate is located in the bonding area, the second bonding pin extends along a second direction, one end of the second signal line is connected to the second bonding pin, and the end of the second signal line away from the second bonding pin is connected to the pixel circuit; at least a portion of the multiple first signal lines have their ends away from the first bonding pin connected to the gate driving circuit, and the remaining portions of the first signal lines have their ends away from the first bonding pin connected to the pixel circuit.

[0010] Optionally, the first bonding pins of all first bonding pin groups are located in the same preset plane, and the preset plane is parallel to the substrate; and / or, the first bonding pins of all first bonding pin groups are arranged in rows and columns.

[0011] Optionally, multiple first signal lines are connected one-to-one with multiple first binding pins; or, at least one of the multiple first signal lines corresponds to multiple first binding pins, the first signal line corresponding to multiple first binding pins is connected to one end of one of the multiple first binding pins, and the other end of the first binding pin is connected in series with the remaining first binding pins in the multiple first binding pins.

[0012] Optionally, each first signal line includes a slanted segment, which is inclined relative to the second direction, and the orthogonal projection of at least one slanted segment on the substrate is located in the bonding region; at least one first signal line also includes a straight segment, which extends along the second direction, and at least a portion of the orthogonal projection of the straight segment on the substrate is located in the bonding region, the straight segment and the slanted segment of the same first signal line are connected, and the end of the straight segment away from the slanted segment is connected to at least one first bonding pin; the slanted segment of the first signal line that does not include the straight segment is directly connected to at least one first bonding pin.

[0013] Secondly, embodiments of this application provide a circuit board including a second bonding structure, the second bonding structure including a plurality of second bonding pin groups, the plurality of second bonding pin groups being arranged sequentially along a first direction; the second bonding pin group includes at least one third bonding pin, the third bonding pin being used to bond with the first bonding pin of the aforementioned display panel; the extension direction of the third bonding pin has a first preset angle with the second direction, the second direction being perpendicular to the first direction.

[0014] Optionally, the circuit board also includes a fourth bonding pin, which is spaced apart from the third bonding pin and extends along a second direction. The fourth bonding pin is used to bond with the second bonding pin of the display panel.

[0015] Thirdly, embodiments of this application provide a display device, including: a circuit board and the aforementioned display panel, wherein the circuit board is bonded to the display panel via a first bonding pin of the display panel.

[0016] The beneficial technical effects of the technical solutions provided in this application include:

[0017] In this embodiment, multiple first signal lines and a first bonding structure are disposed on a substrate. The substrate supports the first signal lines and the first bonding structure. The first bonding structure is used to bond the flexible circuit board, and the first signal lines are used to transmit signals. First bonding pins are configured to bond with the flexible circuit board. Each first signal line is connected to at least one first bonding pin to transmit signals.

[0018] In this embodiment, the first bonding structure includes multiple first bonding pin groups, which are sequentially arranged along a first direction. Each first bonding pin group includes at least one first bonding pin, and the extension direction of the first bonding pin has a first preset angle with a second direction perpendicular to the first direction. This arrangement reduces the width of the arrangement space of the first bonding pins along the second direction, thereby reducing the width of the arrangement space of the first signal line and the first bonding pins along the second direction. Specifically, it effectively reduces the width of the arrangement space of the first signal line and the first bonding pins along the width extension direction (i.e., the second direction) of the display panel's border area, resulting in a narrow bezel for the display product.

[0019] In addition, by dividing multiple first binding pins into multiple first binding pin groups and arranging multiple first binding pin groups sequentially along the first direction, the length of the arrangement space of the first binding pins along the first direction can be reduced, thereby reducing the length of the arrangement space of the first signal line and the first binding pins along the first direction. That is, the length of the arrangement space of the first signal line and the first binding pins along the length extension direction of the border area of ​​the display panel can be effectively reduced, so that the arrangement space of the first signal line and the first binding pins is more reasonable.

[0020] This application embodiment improves the arrangement of the first bonding pin and the first signal line, effectively compressing the arrangement space of the first signal line and the first bonding pin without affecting product performance, yield, and bonding capability, thereby reducing the width of the bezel area of ​​the display panel and helping to achieve a narrow bezel in the display product.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 This is a schematic diagram of the signal lines and bonding pins of a display panel in the prior art.

[0024] Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0025] Figure 3 This is a partial structural diagram of another display panel provided in an embodiment of this application;

[0026] Figure 4 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0027] Figure 5 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0028] Figure 6 This is a partial structural diagram of a circuit board provided in an embodiment of this application.

[0029] Figure label:

[0030] 100 - Display panel; 10 - Substrate; 11 - Fan-out area; 12 - Bonding area; 20 - First signal line; 21 - Diagonal segment; 22 - Straight segment; 23 - Connecting line; 30 - First bonding structure; 31 - First bonding pin group; 32 - First bonding pin; 40 - Second signal line; 50 - Second bonding pin; 200 - Circuit board; 201 - Third bonding pin; 202 - Fourth bonding pin. Detailed Implementation

[0031] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0032] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, “connected” or “coupled” as used herein may include wireless connection or wireless coupling. The term “and / or” as used herein means at least one of the items defined by the term; for example, “A and / or B” may be implemented as “A,” or as “B,” or as “A and B.”

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0034] First, let me introduce and explain the terms used in this application:

[0035] COF (Chip On Flex, or Chip On Film), commonly known as flip-chip film, is a die-on-film packaging technology that fixes integrated circuits (ICs) onto flexible printed circuit boards (FPCs). It uses a flexible attached circuit board as a chip carrier to combine the chip with the flexible substrate circuit, or it can refer to a flexible attached circuit board without packaged chips. It includes tape-and-roll packaging production (TAB substrate, the process is called TCP), flexible board connection chip assembly, and flexible IC carrier board packaging.

[0036] FHD (Full High Definition) refers to full high definition. It typically achieves a resolution of 1920*1080 (in pixels).

[0037] The following describes the existing technology:

[0038] For COF (Crystal-on-Foil) products, the compression of the bezel width around the display panel is limited by the compression of the space on the DP (Data Pad, i.e., data signal output) side.

[0039] COF ICs transmit drive signals to the bonding pins of the display panel via FPC. Some bonding pins send drive signals to the gate drive circuit (GOA circuit) to activate it, while others send drive signals to the pixel circuits in the display area to control the display area. These two sets of pins do not interfere with each other. In COF products, the bonding pins corresponding to the pixel display area drive circuits constitute the majority, typically including 720 pins, 960 pins, and 1280 pins, while the bonding pins corresponding to the gate drive circuits usually only include 50 to 70 pins.

[0040] like Figure 1 As shown, the conventional wiring method for signal lines 20' and bonding pins 32' corresponding to the gate drive circuit is as follows: multiple bonding pins 32' are sequentially spaced along a first direction (the first direction is parallel to the length extension direction of the bezel area of ​​the display panel, the bezel area extends circumferentially along the display area of ​​the display panel, and the length extension direction of the bezel area is the circumferential direction of the display area), and the extension direction of the bonding pins 32' is parallel to a second direction (the second direction is parallel to the width extension direction of the bezel area, the width extension direction of the bezel area is perpendicular to the length extension direction of the bezel area, that is, the width extension direction of the bezel area is perpendicular to the circumferential direction of the display area, that is, the second direction is perpendicular to the first direction). The orthographic projection of the bonding pins 32' on the substrate 10' is located within the bonding area 12' of the bezel area, and a portion of the orthographic projection of the signal line 20' on the substrate 10' is located within the fan-out area 11'. The length of the conventional bonding pin 32' along its extension direction is much greater than its width perpendicular to its extension direction. For example, the length of the bonding pin is 400 micrometers, and its width is only 17 micrometers, indicating that the length-to-width ratio of the bonding pin is large. Since the extension direction of the bonding pin 32' is parallel to the width extension direction of the bezel area, the width of the bezel area of ​​the display panel is limited by the length of the arrangement space of the signal lines and bonding pins along the second direction. The arrangement space of the signal lines and bonding pins is limited by the length of the bonding pins along their own extension direction (i.e., the second direction). The longer the bonding pins are along their own extension direction, the longer the arrangement space of the signal lines and bonding pins is along the second direction, which results in a wider bezel area of ​​the display panel.

[0041] Furthermore, since signal lines 20' need to be connected to corresponding bonding pins 32', and each signal line 20' is connected sequentially according to its corresponding order, at least a portion of the diagonal segments 21' of signal lines 20' have a certain distance between the end used to connect to the corresponding bonding pin 32' and the corresponding bonding pin 32' along the second direction. To achieve the connection between the diagonal segment 21' and the corresponding bonding pin 32', a straight segment 22' needs to be extended from that end of the diagonal segment 21', so that the end of the straight segment 22' away from the diagonal segment 21' is connected to the corresponding bonding pin 32'. This will result in the bonding pin 32' being further away from the diagonal segment 21' when the draw slope of each diagonal segment 21' is the same. The more signal lines there are, including the 22' straight segment, the longer the straight segment along the second direction becomes, and the closer it is to the center of the bonding area, the greater the difference in length between the straight segments near the center and near the edge of the bonding area. This will cause the following technical problems: 1. The longer the arrangement space of the signal lines and bonding pins along the second direction, the wider the bezel of the display product, and the more space is lost in wiring; 2. The greater the difference in length between the straight segments near the center and near the edge of the bonding area, the greater the difference in resistance of the signal lines and bonding pins at the edge of the bonding area to the drive signal compared to the signal lines and bonding pins at the center of the bonding area to the drive signal.

[0042] Currently, under the same process conditions and without affecting product performance and yield, the only way to achieve the purpose of compressing the arrangement space of signal lines and bonding pins is to increase the number of COFs. However, this compression method will inevitably lead to increased costs and decreased competitiveness.

[0043] Therefore, there is a need for a way of arranging signal lines and bonding pins that can effectively reduce the width of the arrangement space of signal lines and bonding pins along the width extension direction (i.e., the second direction) of the bezel area of ​​the display panel, thereby enabling the display product to achieve a narrow bezel.

[0044] The display panel, circuit board, and display device provided in this application are intended to solve at least one of the above-mentioned technical problems existing in the prior art.

[0045] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0046] It should be noted that, in this embodiment, the substrate 10 has a display area and a border area surrounding the display area. The border area includes a circuit area, a fan-out area 11, and a bonding area 12. The fan-out area 11 is located on one side of the display area, and the bonding area 12 is located on the side of the fan-out area 11 away from the display area. The display panel includes a pixel circuit disposed in the display area and a gate driving circuit disposed in the circuit area. One end of the first signal line 20 is connected to the first bonding pin 32. At least a portion of the first signal lines 20 have their ends away from the corresponding first bonding pin 32 electrically connected to the gate driving circuit to transmit the driving signal to the gate driving circuit. The remaining portions of the first signal lines 20 have their ends away from the corresponding first bonding pin 32 electrically connected to the pixel circuit to transmit the signal to the pixel circuit. Of course, according to actual needs, the ends of the first signal lines 20 away from the corresponding first bonding pin 32 can also be connected to other components of the display panel to achieve signal transmission. This is not limited or further explained here.

[0047] Since the technical solution of this application mainly concerns the improvement of the arrangement of the first bonding pin 32 and the first signal line 20 in order to reduce the width of the bezel area of ​​the display panel, the specific form of the connection between the end of the first signal line 20 away from the corresponding first bonding pin 32 and the corresponding component of the display panel (such as pixel circuit or gate driving circuit or other components) and the specific components involved will not be described here.

[0048] This application embodiment uses the example of the first signal line 20 being electrically connected to the gate drive circuit at one end away from the first bonding pin 32. The case where the first signal line 20 is connected to the pixel circuit or other components of the display panel at one end away from the first bonding pin 32 is similar and will not be described again here.

[0049] It should be noted that, in the embodiments of this application, the first direction is parallel to the length extension direction of the border area of ​​the display panel, the border area extends along the circumference of the display area of ​​the display panel, and the length extension direction of the border area is the circumference of the display area; the second direction is parallel to the width extension direction of the border area, the width extension direction of the border area is perpendicular to the length extension direction of the border area, that is, the width extension direction of the border area is perpendicular to the circumference of the display area, that is, the second direction is perpendicular to the first direction.

[0050] This application provides a display panel, the structural schematic diagram of which is shown below. Figures 2 to 4As shown, the system includes: a substrate 10, multiple first signal lines 20, and a first bonding structure 30. The substrate 10 has a fan-out region 11 and a bonding region 12 arranged sequentially; the multiple first signal lines 20 are disposed on one side of the substrate 10, and the orthographic projection of at least one first signal line 20 on the substrate 10 is located in the bonding region 12; the first bonding structure 30 is disposed on the same side of the substrate 10 as the first signal lines 20, and the orthographic projection of the first bonding structure 30 on the substrate 10 is located in the bonding region 12.

[0051] Wherein: the first binding structure 30 includes a plurality of first binding pin groups 31, which are arranged sequentially along a first direction; the first binding pin group 31 includes at least one first binding pin 32, and the first signal line 20 is correspondingly connected to at least one first binding pin 32; the extension direction of the first binding pin 32 has a first preset angle α between it and the second direction, and the second direction is perpendicular to the first direction.

[0052] In this embodiment, multiple first signal lines 20 and first bonding structures 30 are disposed on a substrate 10. The substrate 10 is used to support the first signal lines 20 and the first bonding structures 30. The first bonding structures 30 are used to bond the flexible circuit board. The first signal lines 20 are used to transmit signals, such as clock signals required by the GOA circuit, or DC signals such as VGH, VGL, etc.

[0053] In this embodiment, the first bonding pin 32 is configured to be bonded to the flexible circuit board. A first signal line 20 is connected to at least one first bonding pin 32 to transmit a signal.

[0054] Optionally, in this embodiment, the border area further includes a circuit area, and the circuit area and the fan-out area 11 surround the periphery of the display area; the display panel further includes a gate driving circuit and a pixel circuit, the gate driving circuit is disposed on one side of the substrate 10 and its orthogonal projection on the substrate 10 is located in the circuit area, and the pixel circuit is disposed on one side of the substrate 10 and its orthogonal projection on the substrate 10 is located in the display area.

[0055] Optionally, such as Figure 5 As shown in the embodiment of this application, the display panel further includes a second signal line 40 and a second bonding pin 50. The second signal line 40 and the second bonding pin 50 are both disposed on one side of the substrate 10. The orthographic projection of the second signal line 40 on the substrate 10 is located in the fan-out region, and the orthographic projection of the second bonding pin 50 on the substrate 10 is located in the bonding region. The second bonding pin 50 extends along a second direction, and one end of the second signal line 40 is connected to the second bonding pin 50.

[0056] Optionally, in this embodiment of the application, at least a portion of the first signal lines 20 are connected to the gate driving circuit at one end away from the first bonding pin 32, and the remaining portion of the first signal lines 20 are connected to the pixel circuit at one end away from the first bonding pin 32.

[0057] Optionally, in this embodiment, the end of the second signal line 40 away from the second bonding pin 50 is connected to the pixel circuit.

[0058] Specifically, in this embodiment, the end of the first signal line 20 away from the first bonding pin 32 is connected to the gate driving circuit, and the end of the second signal line 40 away from the second bonding pin 50 is connected to the pixel circuit through a data line.

[0059] In one optional embodiment of this application, at least some signal lines and corresponding bonding pins connected to the gate driving circuit can be arranged in the manner of the first signal line 20 and the first bonding pin 32 in the technical solution of this application, and at least some signal lines and corresponding bonding pins connected to the pixel circuit can be arranged in the manner of the second signal line 40 and the second bonding pin 50 in the technical solution of this application, depending on actual needs; at least some signal lines and corresponding bonding pins connected to the pixel circuit can also be arranged in the manner of the first signal line 20 and the first bonding pin 32 in the technical solution of this application, and at least some signal lines and corresponding bonding pins connected to the gate driving circuit can also be arranged in the manner of the second signal line 40 and the second bonding pin 50 in the technical solution of this application; of course, at least some signal lines and corresponding bonding pins connected to the gate driving circuit and at least some signal lines and corresponding bonding pins connected to the pixel circuit can both be arranged in the manner of the first signal line 20 and the first bonding pin 32 in the technical solution of this application.

[0060] It should be noted that in the embodiments of this application, the structure, connection relationship and arrangement of the second signal line and the second bonding pin are similar to those of the prior art, and will not be described again here.

[0061] It should be noted that, in the embodiments of this application, the display panel also includes grid lines and data lines disposed in the display area and arranged in a cross pattern. Optionally, the first bonding pin in the embodiments of this application may be of the same layer and material as the grid line, or of the same layer and material as the data line layer, or may be of the same layer and material as at least one of the grid line layer, data line layer and electrode layer, which is not limited here.

[0062] In this embodiment, the first bonding structure 30 includes a plurality of first bonding pin groups 31, which are sequentially arranged along a first direction. Each first bonding pin group 31 includes at least one first bonding pin 32, and the extension direction of the first bonding pin 32 has a first preset angle α between it and a second direction perpendicular to the first direction. This arrangement reduces the width of the arrangement space of the first bonding pin 32 along the second direction, thereby reducing the width of the arrangement space of the first signal line 20 and the first bonding pin 32 along the second direction. In other words, it effectively reduces the width of the arrangement space of the first signal line 20 and the first bonding pin 32 along the width extension direction (i.e., the second direction) of the display panel's border area, resulting in a narrow bezel for the display product.

[0063] In addition, by dividing the multiple first binding pins 32 into multiple first binding pin groups 31 and arranging the multiple first binding pin groups 31 sequentially along the first direction, the length of the arrangement space of the first binding pins 32 along the first direction can be reduced, thereby reducing the length of the arrangement space of the first signal line 20 and the first binding pins 32 along the first direction. That is, the length of the arrangement space of the first signal line 20 and the first binding pins 32 along the length extension direction of the border area of ​​the display panel can be effectively reduced (which can avoid the problem of unreasonable arrangement space due to excessive length), so that the arrangement space of the first signal line 20 and the first binding pins 32 is more reasonable.

[0064] This application embodiment improves the arrangement of the first bonding pin 32 and the first signal line 20, effectively compressing the arrangement space of the first signal line 20 and the first bonding pin 32 without affecting product performance, yield, and bonding capability, thereby reducing the width of the bezel area of ​​the display panel and helping to achieve a narrow bezel in the display product.

[0065] Optionally, such as Figure 2 As shown in the embodiment of this application, the first preset included angle α is greater than 0° and less than 180°.

[0066] In existing technologies, such as Figure 2 As shown, the extension direction of the first bonding pin is parallel to the second direction, that is, the angle between the extension direction of the first bonding pin and the second direction is 180°. At this time, the width of the arrangement space of the first bonding pin along the second direction is equal to the length of the first bonding pin along its own extension direction, which causes the arrangement space of the first signal line and the first bonding pin to be limited by the length of the first bonding pin, resulting in the compression and limitation of the bezel width of the display panel.

[0067] In this embodiment, the extension direction of the first binding pin 32 is set to have a first preset angle α with the second direction, and the angle range of the first preset angle α is limited to between 0° and 180°. This makes the width of the arrangement space of the first binding pin 32 along the second direction smaller than the length of the first binding pin 32 along its own extension direction. Furthermore, the width of the arrangement space of the first binding pin 32 along the second direction can be further adjusted by setting the specific value of the first preset angle α (for example, in actual production, the first preset angle α can be set to 90°). This allows the width value to be reduced as much as possible according to actual needs, so that the arrangement space of the first binding pin 32 is no longer limited by the length of the first binding pin 32. This avoids the problem that the arrangement space of the first signal line and the first binding pin is limited by the length of the first binding pin, and can effectively compress the width of the bezel area of ​​the display panel, realizing a narrow bezel or even a bezel-less display product.

[0068] Optionally, such as Figure 2 As shown in the embodiment of this application, the first preset included angle α is 90°.

[0069] In this embodiment, the first preset included angle α is 90°, that is, the extension direction of the first binding pin 32 is perpendicular to the second direction (that is, the first binding pin 32 extends along the first direction). At this time, the width of the arrangement space of the first binding pin 32 along the second direction is equal to the width of the first binding pin 32 (the width direction of the first binding pin 32 is perpendicular to the extension direction of the first binding pin 32). Since the length value of the first binding pin 32 is much greater than the width value, the width of the arrangement space of the first binding pin 32 along the second direction can be minimized by the above setting method, thereby effectively reducing the width of the arrangement space of the first signal line 20 and the first binding pin 32 along the second direction, and achieving the purpose of effectively compressing the width of the bezel area of ​​the display panel.

[0070] It should be noted that in this embodiment, the structure of the first binding pin 32 is similar to that of the prior art, and will not be described again here.

[0071] This application embodiment achieves the goal of effectively compressing the bezel width of the display panel, so as to enable the display product to obtain an ultra-narrow bezel or even a bezel-less design, by improving the arrangement of the first bonding pin 32 and the arrangement of the first signal line 20 due to the change in the arrangement of the first bonding pin 32 without affecting the bonding capability.

[0072] Optionally, such as Figures 2 to 4 As shown in the embodiment of this application, the first binding pin group 31 includes a plurality of first binding pins 32. The plurality of first binding pins 32 of each first binding pin group 31 are arranged sequentially along the second direction, and there is a preset distance between two adjacent first binding pins 32.

[0073] In this embodiment, the extension direction of the first binding pin 32 has a first preset angle α with the second direction perpendicular to the first direction. This arrangement reduces the width of the arrangement space of the first binding pin 32 along the second direction. While ensuring a compression effect on the first binding structure 30 along the second direction, having each first binding pin group 31 include multiple first binding pins 32 reduces the number of first binding pin groups 31, thereby reducing the length of the arrangement space of the first binding structure 30 in the first direction. This helps to compress the arrangement space of the first binding structure 30 and improves the rationality of the arrangement of the first binding pins 32.

[0074] Furthermore, in this embodiment, the multiple first binding pins 32 of each first binding pin group 31 are arranged sequentially along the second direction, and there is a preset distance between two adjacent first binding pins 32, which can keep each first binding pin 32 independent and avoid interference. In addition, since the multiple first binding pins 32 are arranged sequentially at intervals along the second direction, the distance between at least a portion of the first binding pins 32 and the corresponding first signal line 20 is reduced. When the first signal line 20 is connected to the corresponding first binding pin 32, a portion of the first signal line 20 is hidden between two adjacent first binding pin groups 31. This not only saves wiring space, but also shortens the length of at least a portion of the first signal line 20, reducing the difference between the resistance of the first signal line 20 and the first binding pin 32 at the edge of the binding area 12 to the drive signal and the resistance of the first signal line 20 and the first binding pin 32 at the center of the binding area 12 to the drive signal.

[0075] Optionally, in this embodiment, the spacing along the second direction between any two adjacent first binding pins 32 of each first binding pin group 31 is the same. This arrangement makes the arrangement of the first binding pins 32 more uniform, making the manufacturing and binding process more convenient.

[0076] Optionally, in this embodiment of the application, the preset distance between two adjacent first binding pins 32 of each first binding pin group 31 is 30 micrometers along the second direction.

[0077] Of course, in an optional embodiment of this application, the length of the preset distance between at least one pair of adjacent first binding pins 32 in at least one first binding pin group 31 along the second direction may be different from the length of the preset distance between other adjacent first binding pins 32 along the second direction, depending on actual needs.

[0078] Optionally, in this embodiment, the length of the first binding pin group 31 along the second direction is less than the length of the first binding pin 32 along its own extension direction.

[0079] In the prior art, the extension direction of the first bonding pin is parallel to the second direction, and the width of the arrangement space of the first bonding pin along the second direction is equal to the length of the first bonding pin along its own extension direction.

[0080] In this embodiment, the length of the first binding pin group 31 along the second direction is less than the length of the first binding pin 32 along its own extension direction. Compared with the prior art, the arrangement space of the first binding pin group 31 in this embodiment is reduced along the second direction, thereby reducing the width of the bezel area of ​​the display panel and helping to achieve narrow bezels or even bezel-less display products.

[0081] Of course, in an optional embodiment of this application, the length of the first binding pin group 31 along the second direction can be made equal to the length of the first binding pin 32 along its own extension direction, depending on actual needs.

[0082] In the prior art, the extension direction of the first binding pin is parallel to the second direction, which is referred to as "vertical placement". In the embodiment of this application, the extension direction of the first binding pin 32 has a first preset angle α of 90° with the second direction (the extension direction of the first binding pin 32 is parallel to the first direction), which is referred to as "lateral placement".

[0083] Optionally, such as Figure 2 As shown in the embodiment of this application, the first first bonding pin 32 of each first bonding pin group 31 on the side away from the fan-out area 11 is located on the same preset straight line L. The extension direction of the preset straight line L is parallel to the first direction, and the preset straight line L is parallel to the substrate 10.

[0084] In this embodiment, multiple first binding pins 32 of each first binding pin group 31 are arranged sequentially with a preset straight line L as the reference, so that the multiple first binding pins 32 are arranged neatly and aesthetically, and the first binding pins 32 of each first binding pin group 31 and their arrangement number can adapt to the wiring trend of the corresponding first signal line 20, which facilitates connection.

[0085] Optionally, in this embodiment, the first bonding pins 32 of all first bonding pin groups 31 are located in the same preset plane, and the preset plane is parallel to the substrate 10. This arrangement simplifies the fabrication and bonding process.

[0086] Optionally, such as Figures 2 to 4As shown in the embodiment of this application, the first binding pins 32 of all first binding pin groups 31 are arranged in rows and columns. This arrangement makes the arrangement of the first binding pins 32 neater and more aesthetically pleasing, and the arrangement is simple, clear, and easier to process, manufacture, and bind.

[0087] It should be noted that, in this embodiment, the row-column arrangement refers to arranging all the first binding pins 32 in a horizontal and vertical format, with the first direction being the row direction of the first binding pins 32 and the second direction being the column direction of the first binding pins 32. Optionally, the spacing between each row is the same, and the spacing between each column is the same.

[0088] Optionally, such as Figure 2 As shown in the embodiment of this application, a plurality of first binding pin groups 31 are arranged sequentially at intervals along a first direction. Along the first direction, there is a preset distance d between two adjacent first binding pin groups 31. The preset distance d is greater than or equal to 25 micrometers (um) and less than or equal to 35 micrometers.

[0089] If the preset spacing d is less than 25 micrometers, it will be difficult to arrange the first signal line 20; if the preset spacing d is greater than 35 micrometers, it will increase the length of the arrangement space of the first bonding structure 30 along the first direction, wasting wiring space.

[0090] In this embodiment, the preset spacing d is greater than or equal to 25 micrometers and less than or equal to 35 micrometers. This allows for convenient arrangement of the first signal line 20, saving wiring space, and also controls the length of the arrangement space of the first bonding structure 30 along the first direction within a reasonable range, effectively compressing the arrangement space of the first bonding structure 30. In other words, through the above-described arrangement, the arrangement space of the first signal line 20 and the first bonding pin 32 can be reasonably arranged, thereby achieving the goal of effectively compressing the arrangement space of the first signal line 20 and the first bonding pin 32.

[0091] Optionally, such as Figure 2 As shown in the embodiment of this application, the preset spacing d is 30 micrometers.

[0092] In one optional embodiment of this application, such as Figure 2 and Figure 3 As shown, multiple first signal lines 20 are connected one-to-one with multiple first binding pins 32. In this embodiment, one first signal line 20 is connected to one first binding pin 32 (i.e., the first signal line 20 and the first binding pin 32 are set one-to-one). By setting multiple first binding pins 32 and multiple first signal lines 20 connected one-to-one with the multiple first binding pins 32, multiple signals can be transmitted simultaneously, improving the efficiency of signal transmission.

[0093] Of course, in one specific embodiment of this application, at least two first bonding pins 32 connected to the flexible circuit board can be connected together by metal (the at least two first bonding pins 32 connected together by metal are equivalent to one first bonding pin), and then connected to a first signal line 20. The signal output by the flexible circuit board can be transmitted to the first signal line 20 through the at least two first bonding pins 32 connected together by metal. This arrangement can improve the signal transmission rate, increase the amount of signal transmitted at the same time, and reduce losses.

[0094] In another alternative embodiment of this application, such as Figure 4 As shown, at least one of the multiple first signal lines 20 corresponds to multiple first binding pins 32. The first signal line 20 corresponding to the multiple first binding pins 32 is connected to one end of one of the multiple first binding pins 32, and the other end of the first binding pin 32 is connected in series with the remaining first binding pins 32 in the multiple first binding pins 32.

[0095] In this embodiment, at least one of the multiple first signal lines 20 corresponds to multiple first binding pins 32 (i.e., a one-to-many arrangement of first signal lines 20 and first binding pins 32). In this case, the first signal line 20 corresponding to the multiple first binding pins 32 and the corresponding multiple first binding pins 32 are connected in series. That is, one end of the first signal line 20 is connected to one end of one of the multiple first binding pins 32, and the other end of the first binding pin 32 connected to the first signal line 20 is connected in series with the remaining first binding pins 32. This arrangement reduces the resistance and impedance of the first signal line 20 and the corresponding first binding pin 32 to the drive signal, and allows for flexible adjustment of the number of first binding pins 32 connected to the first signal line 20 according to actual needs.

[0096] Optionally, such as Figure 4 As shown in the embodiment of this application, the plurality of first bonding pins 32 connected in series with the first signal line 20 come from different first bonding pin groups 31 to facilitate wiring. Of course, in an optional embodiment of this application, at least two of the plurality of first bonding pins 32 connected in series with the first signal line 20 may come from the same first bonding pin group 31, depending on actual needs.

[0097] Optionally, such as Figure 4As shown in the embodiment of this application, the display panel 100 further includes a connecting line 23. The connecting line 23 is used to connect a plurality of first binding pins 32 connected in series with the first signal line 20, and to realize signal transmission between two adjacent first binding pins 32. That is, two adjacent first binding pins 32 connected in series are connected and transmit signals through the connecting line 23.

[0098] Optionally, such as Figures 2 to 4 As shown in the embodiments of this application, each first signal line 20 includes a slanted line segment 21, which is inclined relative to the second direction, and at least one slanted line segment 21 has its orthogonal projection portion on the substrate 10 located in the bonding region 12.

[0099] In this embodiment, the diagonal line segment 21 enables signal transmission. By setting the diagonal line segment 21, the wiring transition of the first signal line 20 between the circuit area and the bonding area or between the pixel area and the bonding area can be achieved.

[0100] Optionally, in this embodiment, the orthographic projection of the oblique line segment 21 on the substrate 10 is partly located in the bonding region 12 and partly located in the fan-out region 11. Of course, depending on actual needs, part of the orthographic projection of the oblique line segment 21 can also be located in the circuit area or display area. This arrangement facilitates the connection of one end of the first signal line 20 to the first bonding pin 32 and the other end to the gate driving circuit, pixel circuit, or other components of the display panel.

[0101] Optionally, such as Figures 2 to 4 As shown in the embodiments of this application, at least one first signal line 20 further includes a straight segment 22, which extends along a second direction. At least a portion of the orthographic projection of the straight segment 22 onto the substrate 10 is located in the bonding region 12. The straight segment 22 of the same first signal line 20 is connected to the oblique segment 21, and the end of the straight segment 22 away from the oblique segment 21 is connected to at least one first bonding pin 32. The oblique segment 21 of the first signal line 20 excluding the straight segment 22 is directly connected to at least one first bonding pin 32.

[0102] The oblique segment 21 of the first signal line 20 is routed with a certain slope. According to the routing rule of the oblique segment, there will be a certain gap between the oblique segment 21 of the first signal line 20 and the corresponding first bonding pin 32 along the second direction. According to the principle of the shortest straight line, a straight segment 22 is set at the end of at least one oblique segment 21 near the bonding area 12. The oblique segment 21 is connected to the first bonding pin 32 through the straight segment 22. This not only enables the connection to transmit signals, but also saves wiring space and resources and reduces costs.

[0103] In this embodiment, each first bonding pin group 31 includes a plurality of first bonding pins 32 arranged sequentially at intervals along a second direction. The distances along the second direction between different first bonding pins 32 in each first bonding pin group 31 and the fan-out region 11 are different. When the position of the first signal line 20 relative to the substrate 10 (i.e., relative to the fan-out region 11) is fixed, if the distances along the second direction between a first bonding pin 32 connected to the first signal line 20 and the fan-out region 11 are different, the distances between the first bonding pin 32 and the first signal line 20 will be different. Therefore, in this embodiment, the first bonding pin 32 corresponding to the first signal line 20 that is closer to the edge of the bonding area 12 is set at a position farther away from the fan-out area 11 along the second direction, and the first bonding pin 32 corresponding to the first signal line 20 that is closer to the center of the bonding area 12 is set at a position closer to the fan-out area 11 along the second direction. This can make the distance between different first signal lines 20 and their corresponding first bonding pins 32 as small as possible, that is, make each straight line segment 22 as short as possible, so as to save wiring space and resources and reduce costs. Furthermore, after the first signal line 20 is connected to the corresponding first bonding pin 32, a portion of the straight segment 22 of the first signal line 20 will be hidden between two adjacent first bonding pin groups 31. This not only saves wiring space but also shortens the length of at least a portion of the first signal line 20, reducing the difference between the resistance of the first signal line 20 and the first bonding pin 32 at the edge of the bonding area 12 to the driving signal and the resistance of the first signal line 20 and the first bonding pin 32 at the center of the bonding area 12 to the driving signal. It also compresses the width of the arrangement space of the first signal line 20 and the first bonding pin 32 along the second direction, thereby compressing the width of the bezel area of ​​the display panel.

[0104] This application uses a gate driving circuit as an example for illustration. One end of the slanted segment 21 of the first signal line 20 is electrically connected to the gate driving circuit, and the other end of the slanted segment 21 is connected to one end of the straight segment 22. The other end of the straight segment 22 is connected to the first bonding pin 32, which is used for bonding with a flexible circuit board. The flexible circuit board transmits the driving signal to the first bonding pin 32, and then the driving signal is transmitted to the gate driving circuit sequentially through the straight segment 22 and the slanted segment 21, causing the gate driving circuit to work. Of course, if the first signal line 20 does not include the straight segment 22, then the end of the slanted segment 21 away from the gate driving circuit is directly connected to the first bonding pin 32, and correspondingly, the first bonding pin 32 directly transmits the driving signal to the slanted segment 21.

[0105] In one optional embodiment of this application, such as Figure 2 As shown, each first binding pin group 31 includes the same number of first binding pins 32.

[0106] In this embodiment, multiple first binding pins 32 are evenly distributed among each first binding pin group 31, and the multiple first binding pin groups 31 are arranged sequentially at intervals to form a horizontal arrangement of multiple first binding pins 32 in a "matrix form". This arrangement can make reasonable use of space, and when the first signal line 20 is connected to the corresponding first binding pin 32, a portion of the first signal line 20 is hidden between two adjacent first binding pin groups 31. This not only saves wiring space, but also shortens the length of at least a portion of the first signal line 20, reducing the difference between the resistance of the first signal line 20 and the first binding pin 32 at the edge of the binding area 12 to the drive signal and the resistance of the first signal line 20 and the first binding pin 32 at the center of the binding area 12 to the drive signal.

[0107] Specifically, such as Figure 2 As shown in the embodiment of this application, taking a 43-inch FHD (Full High Definition) display product size as an example, the first bonding pin 32 of COF has a total of 63 pins, which are divided into 7 groups of 9 pins each. The preset distance between two adjacent first bonding pins 32 in each group is 30µm. To ensure that each first bonding pin 32 is connected to the first signal line 20, the preset spacing d between two adjacent first bonding pin groups 31 needs to be approximately 30µm. Using this arrangement and connecting the first signal line 20 to the corresponding first bonding pin 32, as shown... Figure 2 As shown, the straight segments 22 of the first signal line 20 gradually decrease and are hidden in the gap between two adjacent first bonding pin groups 31.

[0108] In this embodiment, by arranging the 63 first bonding pins 32 horizontally, while ensuring that the number of first bonding pins is consistent and the bonding capability remains unchanged, it is found through wiring that the overall arrangement space of the first signal line 20 and the first bonding structure 30 can be compressed by 400um compared with the existing vertical placement technology.

[0109] In addition, in this embodiment of the application, the formula for the difference in resistance between the near and far first signal lines is defined as: ΔR=(R_Max-R_Min) / R_Min, where ΔR is the difference in resistance between the near and far first signal lines, R_Max is the resistance of the far first signal line, R_Min is the resistance of the near first signal line, the far first signal line refers to the first signal line near the edge of the bonding area, and the near first signal line refers to the first signal line near the center of the bonding area.

[0110] According to the above formula, the resistance difference of the prior art with the first bonding pin placed vertically is 24.7%, while the resistance difference of the first bonding pin 32 placed horizontally in the embodiment of this application is 23.5%. Therefore, it can be seen that the technical solution of this application can reduce the resistance difference of the first signal line at the near and far ends.

[0111] In another alternative embodiment of this application, such as Figure 3 and Figure 4 As shown, the number of first binding pins 32 included in at least one first binding pin group 31 is different from the number of first binding pins 32 included in the remaining first binding pin groups 31, and along the first direction, from the edge to the center of the binding area 12, the number of first binding pins 32 included in each first binding pin group 31 increases.

[0112] In the prior art, since each first bonding pin extends along the second direction, the first bonding pins near the edge of the bonding area and the first bonding pins near the center of the bonding area are arranged at the same height. At this time, the wiring is done according to the wiring trend, so that the first signal line near the center of the bonding area includes a straight segment, and the bottleneck point of the overall wiring is the far end position near the edge of the bonding area.

[0113] In this embodiment, the number of first binding pins 32 included in at least one first binding pin group 31 is different from the number of first binding pins 32 included in the remaining first binding pin groups 31, and along the first direction, from the edge to the center of the binding area 12, the number of first binding pins 32 included in each first binding pin group 31 increases. This arrangement forms a horizontal arrangement of multiple first binding pins 32 in a "stepped" manner, which optimizes the arrangement height of each first binding pin group 31 from the edge to the center of the binding area 12, reduces the distance between the first signal line 20 and the corresponding first binding pin 32 along the second direction, and shortens the length of the straight line segment 22.

[0114] In this embodiment, referring to the wiring trend of the first signal line 20, the number of first bonding pins 32 in each group can be gradually reduced according to the wiring trend, forming a stepped arrangement. For example, 65 pins can be divided into 9 groups, each group including 9, 9, 8, 8, 7, 7, 6, 6, and 5 pins respectively. The wiring effect is as follows: Figure 3 As shown, in each group, the straight segment 22 of the first signal line 20 corresponding to the first bonding pin 32 is reduced and hidden in the gap between two adjacent first bonding pin groups 31, resulting in a better overall wiring effect.

[0115] In this embodiment, the “stepped arrangement” arrangement can make full use of the extra space and can compress the overall arrangement space of the first signal line 20 and the first binding structure 30 by 500µm compared with the existing vertical placement technology. This means that the bottom bezel of the display panel can be compressed by 500µm, which can further enhance the product competitiveness.

[0116] The arrangement of the first bonding pin and the first signal line in this embodiment can be used to arrange the first bonding pin and the first signal line corresponding to the gate driving circuit. Of course, it can also be used to arrange the first bonding pin and the first signal line corresponding to the pixel circuit, or applied to other situations involving the first bonding pin and the first signal line. The display panel with this arrangement can be used to bond with COF (Chip-on-Foil), and of course, it can also be bonded with any other type of circuit board. The display panel with this arrangement can be applied to display devices using COF or any other type of display device.

[0117] Based on the same inventive concept, this application provides a circuit board, the structural schematic diagram of which is shown below. Figure 6 As shown, it includes a second binding structure, which includes multiple second binding pin groups arranged sequentially along a first direction; each second binding pin group includes at least one third binding pin 201, which is used to bind one-to-one with the first binding pin 32 of the display panel mentioned above; the extension direction of the third binding pin 201 has a first preset angle with the second direction, and the second direction is perpendicular to the first direction.

[0118] It should be noted that in the embodiments of this application, the circuit board can be a flexible circuit board, especially a COF (chip flip-flop), and of course, it can also be a printed circuit board.

[0119] It should be noted that, since the third bonding pin of the circuit board of this application is used to bond one-to-one with the first bonding pin of the display panel of this application, and the arrangement of the third bonding pin of the circuit board of this application is adapted to the arrangement of the first bonding pin of the display panel of this application, the circuit board of this application also has the above-mentioned beneficial effects of the display panel of this application, which will not be elaborated here.

[0120] Optionally, such as Figure 6 As shown in the embodiments of this application, the circuit board 200 further includes a fourth bonding pin 202, which is spaced apart from the third bonding pin 201. The fourth bonding pin 202 extends along a second direction and is used to bond with the second bonding pin of the display panel.

[0121] Based on the same inventive concept, this application provides a display device, including: a circuit board and the above-mentioned display panel 100, wherein the circuit board is bonded to the display panel 100 through a first bonding pin 32.

[0122] Specifically, the display device can be any of the following: LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode), Micro LED (Micro Light Emitting Diode), Mini LED (Mini Light Emitting Diode), etc. The display device can also be any product or component with display function, such as a monitor, television, digital camera, mobile phone, tablet computer, etc.

[0123] Optionally, in this embodiment, the circuit board of the display device is the circuit board provided in this embodiment. Of course, in an optional embodiment of this application, a circuit board similar to the prior art can also be used as the circuit board of the display device in this embodiment, as long as the bonding pins of the circuit board can be bonded one-to-one with the first bonding pins of the display panel in this embodiment.

[0124] It should be noted that since the display device of this application includes the display panel of this application, the display device of this application also has the above-mentioned beneficial effects of the display panel of this application, which will not be repeated here.

[0125] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0126] In this embodiment, multiple first signal lines and a first bonding structure are disposed on a substrate. The substrate supports the first signal lines and the first bonding structure. The first bonding structure is used to bond the flexible circuit board, and the first signal lines are used to transmit signals. First bonding pins are configured to bond with the flexible circuit board. Each first signal line is connected to at least one first bonding pin to transmit signals.

[0127] In this embodiment, the first bonding structure includes multiple first bonding pin groups, which are sequentially arranged along a first direction. Each first bonding pin group includes at least one first bonding pin, and the extension direction of the first bonding pin has a first preset angle with a second direction perpendicular to the first direction. This arrangement reduces the width of the arrangement space of the first bonding pins along the second direction, thereby reducing the width of the arrangement space of the first signal line and the first bonding pins along the second direction. Specifically, it effectively reduces the width of the arrangement space of the first signal line and the first bonding pins along the width extension direction (i.e., the second direction) of the display panel's border area, resulting in a narrow bezel for the display product.

[0128] In addition, by dividing multiple first binding pins into multiple first binding pin groups and arranging multiple first binding pin groups sequentially along the first direction, the length of the arrangement space of the first binding pins along the first direction can be reduced, thereby reducing the length of the arrangement space of the first signal line and the first binding pins along the first direction. That is, it can effectively reduce the length of the arrangement space of the first signal line and the first binding pins along the length extension direction of the display panel's border area (which can avoid the problem of unreasonable arrangement space due to excessive length), so as to make the arrangement space of the first signal line and the first binding pins more reasonable.

[0129] This application embodiment improves the arrangement of the first bonding pin and the first signal line, effectively compressing the arrangement space of the first signal line and the first bonding pin without affecting product performance, yield, and bonding capability, thereby reducing the width of the bezel area of ​​the display panel and helping to achieve a narrow bezel in the display product.

[0130] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0131] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0132] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0133] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0134] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0135] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A display panel, comprising a substrate, the substrate having a display area and a bezel area located on at least one side of the display area, the bezel area including a fan-out area and a bonding area, the fan-out area being located on one side of the display area, the bonding area being located on the side of the fan-out area away from the display area, the display area having intersecting grid lines and data lines, characterized in that, Also includes: Multiple first signal lines are disposed on one side of the substrate, and at least one first signal line has its orthogonal projection portion on the substrate located in the fan-out region and the bonding region; A first bonding structure is disposed on the same side of the substrate as the first signal line, and the orthographic projection of the first bonding structure on the substrate is located in the bonding area; Wherein: the first binding structure includes a plurality of first binding pin groups, and the plurality of first binding pin groups are arranged sequentially along a first direction; The first bonding pin group includes a plurality of first bonding pins, and the plurality of first bonding pins in the same first bonding pin group are arranged along a second direction; the first signal line is connected to at least one of the first bonding pins. The first bonding pin has a first preset angle between its extension direction and the second direction, the second direction is perpendicular to the first direction, and the first preset angle is 90°. The first signal line further includes a straight segment that extends along the second direction. At least a portion of the orthographic projection of the straight segment onto the substrate is located in the bonding region. The straight segment of the same first signal line is connected to the oblique segment, and the end of the straight segment away from the oblique segment is connected to the first bonding pin. Multiple first-bonding pins of the same first-bonding pin group are electrically connected through multiple straight line segments and multiple oblique line segments; The display panel further includes a gate driving circuit and a pixel circuit, and at least a portion of the first signal lines are connected to the gate driving circuit at the end away from the first bonding pin. The display panel further includes a second signal line and a second bonding pin. Both the second signal line and the second bonding pin are disposed on one side of the substrate. The orthographic projection of the second signal line on the substrate is located in the fan-out area, and the orthographic projection of the second bonding pin on the substrate is located in the bonding area. The second bonding pin extends along the second direction. One end of the second signal line is connected to the second bonding pin, and the end of the second signal line away from the second bonding pin is connected to the pixel circuit.

2. The display panel according to claim 1, characterized in that, The plurality of first binding pins of each first binding pin group are arranged sequentially along the second direction, and there is a preset distance between two adjacent first binding pins.

3. The display panel according to claim 1, characterized in that, The length of the first bonding pin group along the second direction is less than or equal to the length of the first bonding pin along the extension direction of the first bonding pin.

4. The display panel according to any one of claims 1 to 3, characterized in that, Each of the first binding pin groups includes the same number of first binding pins; or, At least one of the first bonding pin groups includes a number of first bonding pins that is different from the number of first bonding pins included in the remaining first bonding pin groups, and along the first direction, from the edge of the bonding area to the center, the number of first bonding pins included in each first bonding pin group increases.

5. The display panel according to any one of claims 1 to 3, characterized in that, Multiple first bonding pin groups are sequentially spaced along a first direction, and a preset spacing is provided between adjacent first bonding pin groups along the first direction, the preset spacing being greater than or equal to 25 micrometers and less than or equal to 35 micrometers; and / or, The first preset included angle is greater than 0° and less than 180°.

6. The display panel according to any one of claims 1 to 3, characterized in that, The bezel area also includes a circuit area, and the circuit area and the fan-out area surround the periphery of the display area; the gate driving circuit is disposed on one side of the substrate and its orthographic projection on the substrate is located in the circuit area, and the pixel circuit is disposed on one side of the substrate and its orthographic projection on the substrate is located in the display area; The remaining portion of the first signal lines, at the end furthest from the first bonding pin, is connected to the pixel circuit.

7. The display panel according to any one of claims 1 to 3, characterized in that, All the first bonding pins of the first bonding pin group are located in the same preset plane, and the preset plane is parallel to the substrate; and / or, The first binding pins of all the first binding pin groups are arranged in rows and columns.

8. The display panel according to any one of claims 1 to 3, characterized in that, Multiple first signal lines are connected one-to-one with multiple first binding pins; or, At least one of the multiple first signal lines corresponds to multiple first binding pins. The first signal line corresponding to the multiple first binding pins is connected to one end of one of the multiple first binding pins, and the other end of the first binding pin is connected in series with the remaining first binding pins in the multiple first binding pins.

9. The display panel according to any one of claims 1 to 3, characterized in that, Each of the first signal lines includes a slanted segment, which is inclined relative to the second direction, and at least one of the slanted segments has its orthogonal projection portion on the substrate located in the bonding region; The diagonal segment of the first signal line, excluding the straight segment, is directly connected to at least one of the first bonding pins.

10. A circuit board, characterized in that, It includes a second bonding structure, which includes multiple second bonding pin groups, which are arranged sequentially along a first direction; The second bonding pin group includes at least one third bonding pin, the third bonding pin being used to bond to a corresponding first bonding pin of the display panel according to any one of claims 1 to 9; The extension direction of the third bonding pin has a first preset angle with the second direction, and the second direction is perpendicular to the first direction.

11. The circuit board according to claim 10, characterized in that, The circuit board further includes a fourth bonding pin, which is spaced apart from the third bonding pin and extends along the second direction. The fourth bonding pin is used to bond with the second bonding pin of the display panel.

12. A display device, characterized in that, include: The circuit board and the display panel according to any one of claims 1 to 9, wherein the circuit board is bonded to the display panel via a first bonding pin of the display panel.

Images