Electronic device

Abstract

An electronic device is provided. The electronic device includes a semiconductor element and a pixel circuit. The pixel circuit includes a first comparator, a second comparator, and a subtraction unit. The first comparator generates a first comparison signal. The second comparator generates a second comparison signal. The subtraction unit is coupled to the semiconductor element and configured to receive the first comparison signal and the second comparison signal, and generate a subtraction signal.

Description

Technical Field

[0001] This disclosure generally relates to an electronic device, and more specifically to an electronic device including a pixel circuit that reduces voltage errors caused by transistors. Background Technology

[0002] Generally, electronic devices including pixel circuits require transistor reset to reset the voltage values ​​on the pixel circuits. However, the parasitic capacitance of the reset transistor causes voltage errors. These voltage errors lead to transmission timing errors in pulse-width modulation (PWM). Reducing the voltage errors caused by transistors in the pixel circuits of electronic devices is one of the key research and development focuses for those skilled in the art. Summary of the Invention

[0003] This disclosure relates to an electronic device that includes pixel circuitry to reduce voltage errors caused by transistors.

[0004] This disclosure provides an electronic device. The electronic device includes a semiconductor element and a pixel circuit. The pixel circuit includes a first comparator, a second comparator, and a subtraction unit. The first comparator generates a first comparison signal. The second comparator generates a second comparison signal. The subtraction unit is coupled to the semiconductor element and configured to receive the first comparison signal and the second comparison signal, and generate a subtraction signal.

[0005] To make the foregoing easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0006] This document includes accompanying drawings to provide a further understanding of the disclosure, and the drawings are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0007] Figure 1 A schematic diagram of an electronic device according to a first embodiment of the present disclosure is shown.

[0008] Figure 2 The operation timing diagram of the electronic device is shown.

[0009] Figure 3 A schematic diagram of an electronic device according to a second embodiment of the present disclosure is shown.

[0010] Figure 4 Show Figure 3 The operation timing diagram.

[0011] Figure 5 Show Figure 3a timing chart of the operation of the electronic device according to the first embodiment of the present disclosure.

[0012] Figure 6 a schematic diagram showing an electronic device according to a third embodiment of the present disclosure.

[0013] Figure 7 a schematic diagram showing Figure 6 another schematic diagram showing a relationship between the pulse widths of the subtraction signal, the first data signal, and the second data signal.

[0014] Figure 8 a schematic diagram showing an electronic device according to a fourth embodiment of the present disclosure.

[0015] Figure 9 a timing chart of the operation of the electronic device according to the fourth embodiment of the present disclosure. Figure 8

[0016] Figure 10 a schematic diagram showing an electronic device according to a fifth embodiment of the present disclosure.

[0017] Figure 11 a schematic diagram showing an electronic device according to a sixth embodiment of the present disclosure.

[0018] Figure 12 a schematic diagram showing an electronic device according to a seventh embodiment of the present disclosure.

[0019] Figure 13 a schematic diagram showing a subtraction unit according to an eighth embodiment of the present disclosure.

[0020] Figure 14 a schematic diagram showing a subtraction unit according to a ninth embodiment of the present disclosure.

[0021] LEGEND

[0022] 100, 200, 200', 200", 300, 400, 500, 600, 700: electronic device

[0023] 110, 210, 310, 410, 510, 610_1, 610_2, 710_1, 710_2, 710_3: semiconductor element

[0024] 120, 210, 220, 220', 220", 320, 420, 520, 620, 720: pixel circuit

[0025] 121_A, 121_B, 221_A, 221_B, 221_B', 321_A, 321_B, 421_A, 421_B, 521_A, 521_B, 621_A, 621_B, 721_A1, 721_A2, 721_A3, 721_B: comparator​

[0026] 122, 222, 222', 322, 422, 522, 622, 722_1, 722_2, 722_3: subtraction unit

[0027] 123, 323, 523, 623_1, 623_2, 723_1, 723_2, 723_3: transmission control unit

[0028] 130, 230, 330, 430, 530, 630, 730_1, 730_2, 730_3: current source

[0029] C1, C2: capacitor

[0030] CE1, CE2: comparison element

[0031] CL: common line

[0032] CP1, CP2: parasitic capacitance

[0033] DL1, DL2: data line

[0034] EM: emission enable signal

[0035] EM1: first emission enable signal / emission enable signal

[0036] EM2: second emission enable signal / emission enable signal

[0037] EML, EML1, EML2: emission enable line

[0038] IE, IE1, IE2, IE3: emission current

[0039] IVT, IVT1, IVT2: inverter

[0040] L1, L2, L3: light

[0041] N1, N2, N3, N4, N5: node

[0042] PW, PW1, PW2, PW3: pulse width

[0043] REF, SD_A: first data signal

[0044] SC_A: first comparison signal

[0045] SC_A1, SC_A2, SC_A3: second comparison signal

[0046] SC_B: second comparison signal / first comparison signal

[0047] SD_A1, SD_A2, SD_A3, SD_B: second data signal

[0048] SN1: first control signal

[0049] SN2: second control signal

[0050] SS, SS1, SS2, SS3: subtraction signal

[0051] SWP: scan signal

[0052] T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, Tem, TI1, TI2, TI3, TI4: thin film transistor (TFT)

[0053] TD1: reset time interval

[0054] TD2: emission time interval

[0055] tp1, tp2, tp3, tp4: time point

[0056] V1, V2, V3, V4, V5, V6: voltage value

[0057] VDD: high reference voltage

[0058] VDD_LEU, VSS_LEU: power supply

[0059] VL: reference signal

[0060] VSS: low reference voltage

[0061] VSWPH: maximum voltage value

[0062] Vth: threshold value DETAILED DESCRIPTION

[0063] The present disclosure can be understood by referring to the following detailed description in conjunction with the following drawings that are as set forth below. It should be noted that the various drawings of the present disclosure show only a portion of an electronic device for clarity in illustration and to facilitate understanding of the various drawings by those skilled in the art, and that certain elements in the various drawings can not be drawn to scale. Furthermore, the number and size of each device shown in the drawings is merely illustrative and is not intended to limit the scope of the present disclosure.

[0064] Certain terms are used throughout the following description and claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "coupled" as used herein is used to mean the joined together. As one skilled in the art will appreciate, electronic equipment manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Accordingly, when the specification states that a component, feature, structure, or means includes, has, or comprises something, it is meant that the specification includes something, but is not limited only to that something. When the specification states that a component, feature, structure, or means includes, has, or comprises something that includes, has, or comprises something else, it is meant that the component, feature, structure, or means includes, has, or comprises something as well as something else, but is not limited only to that something or something else.

[0065] It will be understood that when an element is referred to as being "coupled to", "connected to", or "conducted to" another element, it can be directly connected to the other element or electrically connected to the other element with intervening elements present therebetween (indirect electrical connection). In contrast, when an element is referred to as being "directly coupled to", "directly connected to", or "directly conducted to" another element, there are no intervening elements present therebetween.

[0066] Although the use of the terms first, second, third, etc. can be used to describe different constituent elements, such constituent elements are not limited by the terms. The terms are used only to distinguish one constituent element from another constituent element in the specification. The claims can not use the same terms, but can use the terms first, second, third, etc. for the order of the elements claimed. Therefore, in the following description, a first constituent element can be a second constituent element in the claims.

[0067] In this disclosure, an embodiment uses "pixel" or "pixel unit" as a unit to describe a certain region including at least one functional circuit for at least one specific function. The disclosure can be used to describe "a pixel having a circuit" as "a circuit". For example, "a pixel having a current source" can be described as "a current source", or "a pixel having a current sink" can be described as "a current sink". The region of "a pixel" depends on the unit providing a specific function, and adjacent pixels can share the same component or wiring, but can also include their own specific components therein. For example, adjacent pixels can share the same sweep line or the same data line, but the pixels can also have their own transistors or capacitors.

[0068] In this disclosure, a current source circuit is a circuit unit for outputting current, and a current sink is a circuit unit for drawing current. Adjacent circuit units may share the same components or wiring, and may also include their own specific components.

[0069] It should be noted that, without departing from the spirit of this disclosure, the technical features in the different embodiments described below may be replaced, recombined, or mixed to form another embodiment.

[0070] Figure 1 A schematic diagram of an electronic device according to a first embodiment of this disclosure is shown. (Refer to...) Figure 1 In an embodiment, the electronic device 100 includes a semiconductor element 110 and a pixel circuit 120. The pixel circuit 120 includes comparators 121_A and 121_B and a subtraction unit 122. Comparator 121_A generates a first comparison signal SC_A. Comparator 121_B generates a second comparison signal SC_B. The subtraction unit 122 is coupled to comparators 121_A and 121_B and the semiconductor element 110. The subtraction unit 122 receives the first comparison signal SC_A and the second comparison signal SC_B. The subtraction unit 122 generates a subtraction signal SS based on the first comparison signal SC_A and the second comparison signal SC_B. The pixel circuit 120 provides the subtraction signal SS to control the semiconductor element 110. In an embodiment, the semiconductor element 110 includes at least one light output element. For example, the semiconductor element 110 includes at least one light-emitting diode (LED), but this disclosure is not limited thereto. The semiconductor element 110 emits emitted light based on the subtraction signal SS. Semiconductor element 110 may be an organic light emitting diode (OLED), a minimeter-sized light emitting diode (mini-LED), a micrometer-sized light emitting diode (micro-LED), or a quantum dot light emitting diode (QLED), but is not limited to these.

[0071] Subtraction unit 122 performs a subtraction operation on the first comparison signal SC_A and the second comparison signal SC_B to generate a subtraction signal SS. For example, the subtraction signal SS is the difference between the timing of the first comparison signal SC_A and the timing of the second comparison signal SC_B.

[0072] In general, the parasitic capacitance of the reset transistor in the comparator 121_A causes a voltage error in the comparator 121_A, such that the timing of the first comparison signal SC_A is shifted. The parasitic capacitance of the reset transistor in the comparator 121_B causes a voltage error in the comparator 121_B, such that the timing of the second comparison signal SC_B is shifted. It is noted that the subtraction unit 122 generates a subtraction signal SS according to the first comparison signal SC_A and the second comparison signal SC_B. The voltage error caused by the comparator 121_A and the comparator 121_B can be eliminated. Therefore, the voltage error caused by the transistors in the electronic device 100 can be reduced.

[0073] In an embodiment, the electronic device 100 further includes a current source 130 for providing an emission current IE. The pixel circuit 120 further includes an emission control unit 123. The emission control unit 123 is coupled to the subtraction unit 122 and the semiconductor element 110. The emission control unit 123 transmits the emission current IE to the semiconductor element 110 in response to the subtraction signal SS and an emission enable signal EM. In an embodiment, the current source 130 is coupled between a power supply VDD LEU and the emission control unit 123. The current source 130 can provide the emission current IE through the power supply VDD LEU. The semiconductor element 110 is coupled between a power supply VSS LEU and the emission control unit 123. The power supply VSS LEU can be a ground voltage.

[0074] In an embodiment, the subtraction unit 122 can be implemented by a logic circuit or a subtraction circuit. The emission control unit 123 can be implemented by a sweep circuit or a switching circuit controlled by the emission enable signal EM.

[0075] Reference is made to Figure 1 and Figure 2 , Figure 2 An operation timing diagram of the electronic device is shown. In an embodiment, the comparator 121_A receives the first data signal SD_A and a scan signal SWP. The comparator 121_A generates the first comparison signal SC_A according to the first data signal SD_A and the scan signal SWP. In an embodiment, the transition point (e.g., the point in time of a falling edge) of the first comparison signal SC_A is determined based on the voltage value of the first data signal SD_A. For example, the voltage value of the scan signal SWP is scanned at a point in time tpi. When the voltage value of the scan signal SWP is lower than the voltage value of the first data signal SD_A, the comparator 121_A generates the first comparison signal SC_A with a high voltage value. When the voltage value of the scan signal SWP is higher than or equal to the voltage value of the first data signal SD_A, the comparator 121_A generates the first comparison signal SC_A with a low voltage value. Therefore, the first comparison signal SC_A is transitioned from the high voltage value to the low voltage value at a point in time tp3.

[0076] The comparator 121_B receives the second data signal SD_B and the scan signal SWP. The comparator 121_B generates the second comparison signal SC_B according to the second data signal SD_B and the scan signal SWP. In an embodiment, the transition point (e.g., the point of falling edge) of the second comparison signal SC_B is determined based on the voltage value of the second data signal SD_B. For example, the voltage value of the scan signal SWP is scanned at the point of time tp1. When the voltage value of the scan signal SWP is lower than the voltage value of the second data signal SD_B, the comparator 121_B generates the second comparison signal SC_B with a high voltage value. When the voltage value of the scan signal SWP is higher than or equal to the voltage value of the second data signal SD_B, the comparator 121_B generates the second comparison signal SC_B with a low voltage value. Thus, the second comparison signal SC_B is transitioned from the high voltage value to the low voltage value at the point of time tp2.

[0077] The subtraction unit 122 generates the subtraction signal SS according to the difference between the timing of the first comparison signal SC_A and the timing of the second comparison signal SC_B. Thus, the subtraction signal SS has the high voltage value between the point of time tp2 and the point of time tp3. In other words, the subtraction signal SS is a PWM signal determined by the first comparison signal SC_A and the second comparison signal SC_B.

[0078] In an embodiment, the emission enable signal EM is transitioned from the low voltage value to the high voltage value at the point of time tp1. At the point of time tp4, the emission enable signal EM is transitioned from the high voltage value to the low voltage value. The emission enable signal EM has the high voltage value from the point of time tp1 to the point of time tp4. Thus, the emission control unit 123 provides the emission current IE to the semiconductor element 110 in response to the subtraction signal SS between the point of time tp1 and the point of time tp4.

[0079] In the present embodiment, the emission control unit 123 is enabled in response to the high voltage level of the emission enable signal EM. In some embodiments, the emission control unit 123 is enabled in response to the low voltage level of the emission enable signal EM.

[0080] Figure 3 A schematic diagram of an electronic device according to a second embodiment of the present disclosure is shown. Figure 4 A schematic diagram of an electronic device according to a second embodiment of the present disclosure is shown. Figure 3 A timing diagram of the operation of the electronic device is shown. Reference is made to Figure 3 and Figure 4In an embodiment, the electronic device 200 includes a semiconductor element 210, a pixel circuit 220, and a current source 230. The pixel circuit 220 includes comparators 221_A, 221_B and a subtraction unit 222. The comparator 221_A includes thin-film transistors (TFTs) T1, T2, T3, a capacitor C1, and a comparison element CE1. A first terminal of the TFT T1 is coupled to a data line DL1 and receives a first data signal SD_A via the data line DL1. A control terminal of the TFT T1 receives a first control signal SN1. A first terminal of the TFT T2 receives a scan signal SWP. A control terminal of the TFT T2 receives the first control signal SN1. A first terminal of the capacitor C1 is coupled to a second terminal of the TFT T1 and a second terminal of the TFT T2. A first terminal (i.e., a node N1) of the comparison element CE1 is coupled to a second terminal of the capacitor C1, and a second terminal (i.e., a node N2) of the comparison element CE1 is coupled to the subtraction unit 222. A first terminal of the TFT T3 is coupled to the first terminal of the comparison element CE1. A second terminal of the TFT T3 is coupled to the second terminal of the comparison element CE1. A control terminal of the TFT T3 receives the first control signal SN1. In an embodiment, the TFTs T1 and T3 are of a first type, respectively. The TFT T2 is of a second type. For example, the TFT T1 and the TFT T3 can be P type metal oxide semiconductors (PMOS), respectively, and the TFT T2 can be an N type metal oxide semiconductor (NMOS). In other embodiments, the TFT T1 and the TFT T3 can be NMOS, respectively, and the TFT T2 can be PMOS.

[0081] In an embodiment, the comparison element CE1 is an inverter. The comparison element CE1 includes TFTs TIl and TI2. A first terminal of the TFT TIl is coupled to a high reference voltage VDD. A second terminal of the TFT TIl is coupled to the node N2. A control terminal of the TFT TIl is coupled to the node Nl. A first terminal of the TFT TI2 is coupled to the node N2. A second terminal of the TFT TI2 is coupled to a low reference voltage VSS. A control terminal of the TFT TI2 is coupled to the node Nl.

[0082] The comparator 221_B includes TFTs T4, T5, T6, a capacitor C2, and a comparison element CE2. The first terminal of the TFT T4 is coupled to the data line DL2 and receives the second data signal SD_B via the data line DL2. The control terminal of the TFT T4 receives the second control signal SN2. The first terminal of the TFT T5 receives the scan signal SWP. The control terminal of the TFT T5 receives the second control signal SN2. The first terminal of the capacitor C2 is coupled to the second terminal of the TFT T4 and the second terminal of the TFT T5. The first terminal (i.e., node N3) of the comparison element CE2 is coupled to the second terminal of the capacitor C2, and the second terminal (i.e., node N4) of the comparison element CE2 is coupled to the subtraction unit 222. The first terminal of the TFT T6 is coupled to the first terminal of the comparison element CE2. The second terminal of the TFT T6 is coupled to the second terminal of the comparison element CE2. The control terminal of the TFT T6 receives the second control signal SN2. In an embodiment, the TFTs T4 and T6 are of a first type of TFTs, respectively. The TFT T5 is of a second type of TFT. For example, the TFTs T4 and T6 are PMOS, respectively, and the TFT T5 is NMOS. In other embodiments, the TFTs T4 and T5 can be NMOS, respectively, and the TFT T6 can be PMOS.

[0083] In an embodiment, the comparison element CE2 is an inverter. The comparison element CE2 includes a TFT TI3 and a TFT TI4. The first terminal of the TFT TI3 is coupled to the high reference voltage VDD. The second terminal of the TFT TI3 is coupled to the node N4. The control terminal of the TFT TI3 is coupled to the node N3. The first terminal of the TFT TI4 is coupled to the node N4. The second terminal of the TFT TI4 is coupled to the low reference voltage VSS. The control terminal of the TFT TI4 is coupled to the node N3.

[0084] In an embodiment, the subtraction unit 222 comprises TFTs T7, T8, T9, T10 and an enable TFT Tem. The first terminal of TFT T7 receives the first comparison signal SC A. The control terminal of TFT T7 receives the emission enable signal EM. The first terminal of TFT T8 is coupled to the second terminal of TFT T7. The control terminal of TFT T8 receives the second comparison signal SC B. The first terminal of TFT T9 is coupled to the second terminal of TFT T8. The second terminal of TFT T9 is coupled to the low reference voltage VSS. The control terminal of TFT T9 receives the second comparison signal SC B. The first terminal of TFT T10 is coupled to the second terminal of TFT T8. The second terminal of TFT T10 is coupled to the low reference voltage VSS. The control terminal of TFT T10 receives the emission enable signal EM. The first terminal of the enable TFT Tem receives the emission current IE. The second terminal of the enable TFT Tem is coupled to the semiconductor element 210. The control terminal of the enable TFT Tem and the second terminal of TFT T8 are coupled to the node N5. The control terminal of the enable TFT Tem and the first terminal of TFT T9 are coupled to the node N5. The control terminal of the enable TFT Tem receives the subtraction signal SS.

[0085] In an embodiment, TFT T7 and TFT T8 are respectively TFTs of a first type. TFT T9, TFT T10 and the enable TFT Tem are respectively TFTs of a second type. For example, TFT T7 and T8 are respectively PMOS. TFT T9, T10 and the enable TFT Tem are NMOS.

[0086] In an embodiment, the subtraction unit 222 is a combined circuit of the subtraction unit 122 and the emission control unit 123 as shown in Figure 1

[0087] Referring to Figure 3 and Figure 4 In an embodiment, in the reset time interval TD1, the voltage value of the emission enable signal EM is high. When the first control signal SN1 has a first voltage value (e.g. a low voltage value), the comparator 221_A resets the voltage value of the first comparison signal SC A on the second terminal of the comparison element CE1 to the threshold value Vth. When the first control signal SN1 has the first voltage value, TFT T1 and T3 are turned on, while TFT T2 is turned off. Therefore, the voltage values on the nodes N1 and N2 are reset to the threshold value Vth. For example, the threshold value Vth can be the threshold value of TFT TIl and TFT TI2. In an embodiment, TFT T3 is a reset transistor of the comparator 221_A.

[0088] ​On the other hand, in the reset time interval TD1, when the first control signal SN1 has the second voltage value (e.g., a high voltage value), the comparator 221_A raises the voltage value on the first terminal (i.e., node N1) of the comparison element CE1 from the threshold value Vth according to the first data signal SD_A and the scan signal SWP, and pulls down the voltage value of the first comparison signal SC_A on the node N2 to a low voltage value. When the first control signal SN1 has the second voltage value, the TFT T2 is turned on, while the TFTs T1 and T3 are turned off. Based on the capacitor C1, the voltage value on the node N1 is pumped in response to the difference between the maximum voltage value VSWPH of the scan signal SWP and the voltage value of the first data signal SD_A. The comparison element CE1 inverts the voltage value on the node N1 to provide the first comparison signal SC_A on the node N2 with a low reference voltage.

[0089] In the reset time interval TD1, when the second control signal SN2 has the first voltage value, the comparator 221_B resets the voltage value of the second comparison signal SC_B on the second terminal of the comparison element CE2 to the threshold value Vth. When the second control signal SN2 has the first voltage value, the TFTs T4 and T6 are turned on, while the TFT T5 is turned off. Thus, the voltage values on the nodes N3 and N4 are reset to the threshold value Vth. In an embodiment, the TFT T6 is a reset transistor of the comparator 221_B.

[0090] On the other hand, in the reset time interval TD1, when the second control signal SN2 has the second voltage value, the comparator 221_B raises the voltage value on the first terminal (i.e., node N3) of the comparison element CE2 from the threshold value Vth according to the second data signal SD_B and the scan signal SWP, and pulls down the voltage value of the second comparison signal SC_B on the node N4 to a low voltage value. When the second control signal SN2 has the second voltage value, the TFT T5 is turned on, while the TFTs T4 and T6 are turned off. Based on the capacitor C2, the voltage value on the node N3 is pumped in response to the difference between the maximum voltage value VSWPH of the scan signal SWP and the voltage value of the second data signal SD_B. The comparison element CE2 inverts the voltage value on the node N3 to provide the second comparison signal SC_B on the node N4 with a low reference voltage. In an embodiment, the voltage value of the second data signal SD_B is lower than the voltage value of the first data signal SD_A.

[0091] Regarding the subtraction signal SS on the node N5, the TFT T10 pulls down the voltage value of the subtraction signal SS to a low reference voltage VSS based on the transmission enable signal EM having a high voltage value.

[0092] In an embodiment, the voltage value of the emission enable signal EM is low in the emission time interval TD2. When the first control signal SN1 has the second voltage value and the voltage value on the first terminal of the first comparison element CE1 is pulled down below the threshold value Vth, the comparator 221_A raises the voltage value of the first comparison signal SC_A to the high voltage value. When the voltage value on the node N1 is pulled down below the threshold value Vth, the comparison element CE1 inverts the voltage value on the node N1 to provide the first comparison signal SC_A on the node N2 having the high reference voltage VDD. When the second control signal SN2 has the second voltage value and the voltage value on the first terminal of the second comparison element CE2 is pulled down below the threshold value Vth, the comparator 221_B raises the voltage value of the second comparison signal SC_B to the high voltage value. When the voltage value on the node N3 is pulled down below the threshold value Vth, the comparison element CE2 inverts the voltage value on the node N3 to provide the second comparison signal SC_B on the node N4 having the high reference voltage VDD.

[0093] It is noted that the voltage value of the second data signal SD_B is lower than the voltage value of the first data signal SD_A. When the reset time interval TD1 ends, the voltage value on the node N1 is lower than the voltage value on the node N3. Therefore, in the emission time interval TD2, the transition point of the first comparison signal SC_A is earlier than the transition point of the second comparison signal SC_B. The subtraction unit 222 generates the subtraction signal SS having a high voltage (e.g., the high reference voltage VDD) according to the difference between the transition point of the first comparison signal SC_A and the transition point of the second comparison signal SC_B.

[0094] It is noted that, for example, the TFT T3 includes a parasitic capacitance CP1. The TFT T6 includes a parasitic capacitance CP2. The parasitic capacitances CP1 and CP2 can cause a timing shift of the first comparison signal SC_A and the second comparison signal SC_B. The subtraction unit 222 generates the subtraction signal SS having a high voltage (e.g., the high reference voltage VDD) according to the difference between the transition point of the first comparison signal SC_A and the transition point of the second comparison signal SC_B. Therefore, the timing shift can be eliminated.

[0095] Figure 5 A schematic diagram showing the relationship between the pulse widths of the subtraction signal, the first data signal and the second data signal according to the third embodiment of the present disclosure is shown. Referring to FIG. 6, the first data signal SD_A has a pulse width of T1. The second data signal SD_B has a pulse width of T2. The subtraction signal SS has a pulse width of T3. The pulse width T3 is equal to the difference between the pulse width T1 and the pulse width T2. Figure 5, assuming that the scan signal SWP is used for a down scan. The voltage value of the second data signal SD_B is designed to be lower than the voltage value of the first data signal SD_A. The pulse width PW of the subtraction signal is determined based on the rising edge of the first comparison signal SC_A and the rising edge of the second comparison signal SC_B. Therefore, if the pulse width of the subtraction signal increases from the pulse width PW2 to the pulse width PW3, the voltage value of the second data signal SD_B increases from the voltage value V2 to the voltage value VI, and the voltage value of the first data signal SD_A decreases from the voltage value V5 to the voltage value V6. If the pulse width of the subtraction signal decreases from the pulse width PW2 to the pulse width PW1, the voltage value of the second data signal SD_B decreases from the voltage value V2 to the voltage value V3, and the voltage value of the first data signal SD_A increases from the voltage value V5 to the voltage value V4.

[0096] Figure 6 A schematic diagram of an electronic device according to a third embodiment of the present disclosure is shown. In the embodiment, the electronic device 200’ includes a semiconductor element 210, a pixel circuit 220’, and a current source 230. The pixel circuit 220’ includes comparators 221_A, 221_B and a subtraction unit 222’. The semiconductor element 210, the current source 230, and the comparators 221_A, 221_B can be inferred by referring to the related descriptions of Figure 3 , which will not be repeated hereinafter. The subtraction unit 222’ includes TFTs T7, T8, T9, T10, and an enable TFT Tem. The first terminal of TFT T7 is coupled to a high reference voltage VDD. The control terminal of TFT T7 receives the first comparison signal SC_A. The first terminal of TFT T8 is coupled to the second terminal of TFT T7. The second terminal of TFT T8 receives the second comparison signal SC_B. The control terminal of TFT T8 receives the first comparison signal SC_A. The first terminal of TFT T9 is coupled to the second terminal of TFT T7. The control terminal of TFT T9 receives the emission enable signal EM. The first terminal of TFT T10 and the control terminal of TFT T10 receive the emission enable signal EM. The second terminal of TFT T10 is coupled to the second terminal of TFT T9. The first terminal of the enable TFT Tem receives the emission current IE. The second terminal of the enable TFT Tem is coupled to the semiconductor element 210. The control terminal of the enable TFT Tem is coupled to the second terminal of TFT T8 and receives the subtraction signal SS.

[0097] Figure 7 Another schematic diagram showing the relationship between the pulse widths of the subtraction signal, the first data signal, and the second data signal of Figure 6 is shown. Refer to Figure 6 and Figure 7, assuming that the scan signal SWP is used for up scan. The voltage value of the second data signal SD_B is designed to be lower than that of the first data signal SD_A. The pulse width PW of the subtraction signal is determined based on the falling edge of the first comparison signal SC_A and the falling edge of the second comparison signal SC_B. Thus, if the pulse width of the subtraction signal increases from the pulse width PW2 to the pulse width PW3, the voltage value of the second data signal SD_B decreases from the voltage value V2 to the voltage value V1, and the voltage value of the first data signal SD_A increases from the voltage value V5 to the voltage value V6. If the pulse width of the subtraction signal decreases from the pulse width PW2 to the pulse width PW1, the voltage value of the second data signal SD_B increases from the voltage value V2 to the voltage value V3, and the voltage value of the first data signal SD_A decreases from the voltage value V5 to the voltage value V4.

[0098] Figure 8 A schematic diagram of an electronic device according to a fourth embodiment of the present disclosure is shown. Figure 9 A timing diagram of the operation of Figure 8 is shown. With reference to Figure 8 and Figure 9 , in an embodiment, the electronic device 200” includes a semiconductor element 210, a pixel circuit 220”, and a current source 230. The pixel circuit 220” includes a comparator 221_A, a comparator 221_B’, and a subtraction unit 222. The semiconductor element 210, the current source 230, the comparator 221_A, and the subtraction unit 222 can be inferred with reference to the related descriptions of Figure 3 , which will not be repeated hereinafter.

[0099] In an embodiment, the comparator 221_B’ includes TFTs T4, T5, T6, a capacitor C2, and a comparison element CE2. A first terminal of the TFT T4 is coupled to the common line CL and receives the reference signal VL via the common line CL. A control terminal of the TFT T4 receives the second control signal SN2. A first terminal of the TFT T5 receives the scan signal SWP. A control terminal of the TFT T5 receives the second control signal SN2. A first terminal of the capacitor C2 is coupled to a second terminal of the TFT T4 and a second terminal of the TFT T5. A first terminal (i.e., node N3) of the comparison element CE2 is coupled to a second terminal of the capacitor C2, and a second terminal (i.e., node N4) of the comparison element CE2 is coupled to the subtraction unit 222. A first terminal of the TFT T6 is coupled to the first terminal of the comparison element CE2. A second terminal of the TFT T6 is coupled to the second terminal of the comparison element CE2. A control terminal of the TFT T6 receives the second control signal SN2. In an embodiment, the TFTs T4 and T6 are TFTs of a first type, respectively. The TFT T5 is a TFT of a second type. For example, the TFTs T4 and T6 are PMOS, respectively. The TFT T5 is NMOS. In an embodiment, the comparison element CE2 is an inverter.

[0100] In an embodiment, different from Figure 3 and Figure 4 , the second control signal SN2 is substantially the same as the first control signal SN1. In addition, the TFT T4 receives the reference signal VL. Thus, in the reset time interval TD1, when the first control signal SN1 and the second control signal SN2 have the first voltage value, the voltage values on the nodes N1, N2, N3 and N4 are substantially equal to the threshold value Vth.

[0101] When the first control signal SN1 and the second control signal SN2 have the second voltage value, the comparator 221_A raises the voltage value on the node N1 from the threshold value Vth according to the difference between the voltage value of the first data signal SD_A and the maximum voltage value VSWPH of the scan signal SWP, and pulls down the voltage value of the first comparison signal SC_A on the node N2 to a low voltage value. The comparator 221_B’ raises the voltage value on the first terminal of the comparison element CE2 (i.e. the node N3) from the threshold value Vth according to the difference between the voltage value of the reference signal VL and the maximum voltage value VSWPH of the scan signal SWP, and pulls down the voltage value of the reference signal VL on the node N4 to a low voltage value. The reference signal VL can be the minimum voltage value of the second data signal SD_B. Thus, in the emission time interval TD2, the comparator 221_B’ provides the second comparison signal SC_B with a fixed timing.

[0102] In an embodiment, the first control signal SN1 and the second control signal SN2 can be one control signal. The second data signal SD_B is replaced by the reference signal VL. Thus, the signal input manner of the pixel circuit 220” can be simplified.

[0103] Figure 10 A schematic diagram of an electronic device according to a fifth embodiment of the present disclosure is shown. Referring to Figure 10 , the electronic device 300 includes a semiconductor element 310, a pixel circuit 320 and a current source 330. The pixel circuit 320 includes comparators 321_A, 321_B, a subtraction unit 322, an emission control unit 323 and an enabling TFT Tem. The semiconductor element 310, the comparators 321_A, 321_B, the enabling TFT Tem and the current source 330 can be implemented by referring to the related descriptions of the semiconductor element 310, the comparators 221_A, 221_B, the enabling TFT Tem and the current source 330 in Figure 1 and Figure 3 , which will not be repeated hereinafter.

[0104] In an embodiment, the subtraction unit 322 comprises a first logic gate. The first logic gate performs a first logic operation on the first comparison signal SC_A and the second comparison signal SC_B to generate a subtraction signal SS. For example, the first logic gate is an XOR gate. A first input terminal of the first logic gate is coupled to the comparator 321_A and receives the first comparison signal SC_A. A second input terminal of the first logic gate is coupled to the comparator 321_B and receives the second comparison signal SC_B. An output terminal of the first logic gate is coupled to the emission control unit 323. The first logic gate performs an XOR logic operation on the first comparison signal SC_A and the second comparison signal SC_B to generate the subtraction signal SS and outputs the subtraction signal SS to the emission control unit 323.

[0105] In an embodiment, the emission control unit 323 comprises a second logic gate. The second logic gate controls the enable TFT Tem according to the subtraction signal SS and an emission enable signal EM. For example, the enable TFT Tem is a PMOS. Thus, the second logic gate is a NAND gate. A first input terminal of the second logic gate receives the emission enable signal EM. A second input terminal of the second logic gate is coupled to the subtraction unit 322 and receives the subtraction signal SS. An output terminal of the second logic gate is coupled to a control terminal of the enable TFT Tem. The second logic gate performs a NAND logic operation on the emission enable signal EM and the subtraction signal SS to generate a gate signal to control the enable TFT Tem.

[0106] In some embodiments, the enable TFT Tem is an NMOS. Thus, the second logic gate is an AND gate. The second logic gate performs an AND logic operation on the emission enable signal EM and the subtraction signal SS to generate a gate signal to control the enable TFT Tem.

[0107] Figure 11 A schematic diagram of an electronic device according to a sixth embodiment of the present disclosure is shown. Referring to FIG. 4, the electronic device 400 comprises a semiconductor element 410, a pixel circuit 420 and a current source 430. The pixel circuit 420 comprises comparators 421_A, 421_B, a subtraction unit 422 and an enable TFT Tem. The semiconductor element 410, the comparators 421_A, 421_B, the enable TFT Tem and the current source 430 can be inferred by referring to the related descriptions of the semiconductor element 310, the comparators 311_A, 311_B, the enable TFT Tem and the current source 330 of FIG. 3, which are not repeated hereinafter. Figure 11 In an embodiment, the electronic device 400 comprises a semiconductor element 410, a pixel circuit 420 and a current source 430. The pixel circuit 420 comprises comparators 421_A, 421_B, a subtraction unit 422 and an enable TFT Tem. The semiconductor element 410, the comparators 421_A, 421_B, the enable TFT Tem and the current source 430 can be inferred by referring to the related descriptions of the semiconductor element 310, the comparators 311_A, 311_B, the enable TFT Tem and the current source 330 of FIG. 3, which are not repeated hereinafter. Figure 1 、 Figure 3 、 Figure 8 and Figure 10 The related descriptions of the semiconductor element 310, the comparators 311_A, 311_B, the enable TFT Tem and the current source 330 of FIG. 3 are not repeated hereinafter.

[0108] In an embodiment, the subtraction unit 422 comprises TFTs T7, T8, T9, T10, T11 and an inverter IVT. The first terminal of TFT T7 is coupled to node N2 and receives the first comparison signal SC_A. The control terminal of TFT T7 receives the transmit enable signal EM. The first terminal of TFT T8 is coupled to the second terminal of TFT T7. The second terminal of TFT T8 is the output terminal (i.e. node N5) of the subtraction unit 422. The control terminal of TFT T8 is coupled to node N4 and receives the second comparison signal SC_B. The first terminal of TFT T9 is coupled to the output terminal and the second terminal of TFT T8. The second terminal of TFT T9 is coupled to the low reference voltage VSS. The control terminal of TFT T9 receives the second comparison signal SC_B. The first terminal of TFT T10 is coupled to the output terminal and the second terminal of TFT T8. The second terminal of TFT T10 is coupled to the low reference voltage VSS. The control terminal of TFT T10 receives the transmit enable signal EM. The input terminal of inverter IVT is coupled to node N2 and receives the first comparison signal SC_A. The first terminal of TFT T11 is coupled to the output terminal and the second terminal of TFT T8. The second terminal of TFT T11 is coupled to the low reference voltage VSS. The control terminal of TFT T11 is coupled to the output terminal of inverter IVT and receives the inversion of the first comparison signal SC_A. In an embodiment, TFTs T7 and T8 are of the first type of TFTs, respectively. TFTs T9, T10, T11 and the enable TFT Tem are of the second type of TFTs, respectively. For example, TFTs T7 and T8 are PMOS, respectively. TFTs T9, T10, T11 and the enable TFT Tem are NMOS. The subtraction unit 422 is Figure 10 an alternative of the logical operation of the fourth embodiment.

[0109] In some embodiments, the enable TFT Tem can be integrated in the subtraction unit 422.

[0110] Figure 12 A schematic diagram of an electronic device according to a seventh embodiment of the present disclosure is shown. Referring to FIG. 7, in an embodiment, the electronic device 700 comprises a semiconductor element 710, a pixel circuit 720 and a current source 730. The pixel circuit 720 comprises comparators 721_A, 721_B, a subtraction unit 722 and a transmit control unit 723. The semiconductor element 710, the comparators 721_A, 721_B and the current source 730 can be inferred by referring to the related descriptions of the semiconductor element 510, the comparators 521_A, 521_B, the subtraction unit 522 and the current source 530 of the electronic device 500 of the sixth embodiment of the present disclosure, which are not repeated hereinafter. Figure 12 Figure 1 Figure 3 Figure 8 Figure 10

[0111] ​​​​​In an embodiment, the subtraction unit 522 comprises TFTs T7, T8, T9 and inverters IVT1, IVT2. The first terminal of TFT T7 is coupled to node N2 and receives the first comparison signal SC A. The control terminal of TFT T7 is coupled to node N4 and receives the second comparison signal SC B. The first terminal of TFT T8 is coupled to the second terminal of TFT T7. The second terminal of TFT T8 is coupled to the low reference voltage VSS. The control terminal of TFT T8 receives the second comparison signal SC B. The input terminal of inverter IVT1 is coupled to node N2 and receives the first comparison signal SC A. The first terminal of TFT T9 is coupled to the second terminal of TFT T7. The second terminal of TFT T9 is coupled to the low reference voltage VSS. The control terminal of TFT T9 is coupled to the output terminal of inverter IVT1 and receives the inversion of the first comparison signal SC A. The input terminal of inverter IVT2 is coupled to the second terminal of TFT T7. The output terminal of inverter IVT2 is coupled to the emission control unit 523. In an embodiment, TFT T7 is a TFT of a first type. TFTs T8, T9 are respectively a TFT of a second type. For example, TFT T7 is a PMOS. TFTs T8, T9 are respectively a NMOS.

[0112] In an embodiment, the emission control unit 523 comprises TFTs T10, T11, T12, T13 and an enabling TFT Tem. A first terminal of the enabling TFT Tem receives an emission current from the current source 530. A second terminal of the enabling TFT Tem is coupled to the semiconductor element 510. A control terminal of the enabling TFT Tem receives a subtraction signal from the node N5. A first terminal of the TFT T10 is coupled to a high reference voltage VDD. A control terminal of the TFT T10 receives an emission enable signal EM. A first terminal of the TFT T11 is coupled to a second terminal of the TFT T10. A second terminal of the TFT T11 is coupled to the node N5 and the control terminal of the enabling TFT Tem. A control terminal of the TFT T11 is coupled to an output terminal of the inverter IVT2. A first terminal of the TFT T12 is coupled to the node N5 and the control terminal of the enabling TFT Tem. A second terminal of the TFT T12 is coupled to a low reference voltage VSS. A control terminal of the TFT T12 is coupled to the output terminal of the inverter IVT2. A first terminal of the TFT T13 is coupled to the node N5 and the control terminal of the enabling TFT Tem. A second terminal of the TFT T13 is coupled to the low reference voltage VSS. A control terminal of the TFT T13 is coupled to the emission enable signal EM. In an embodiment, the TFTs T10, T11 are of a first type, respectively. The TFTs T12, T13 and the enabling TFT Tem are of a second type, respectively. For example, the TFTs T10, T11 are PMOS, respectively. The TFTs T12, T13 and the enabling TFT Tem are NMOS, respectively.

[0113] Figure 13 A schematic diagram of a subtraction unit according to an eighth embodiment of the disclosure is shown. Reference is made to Figure 13 In an embodiment, the electronic device 600 comprises semiconductor elements 610_1, 610_2, pixel circuits 620, a current source 630 and emission enable lines EML1, EML2. The pixel circuits 620 comprise comparators 621_A, 621_B, a subtraction unit 622 and emission control units 623_1, 623_2. The comparators 621_A, 621_B and the current source 630 can be inferred by reference to the related description of Figure 1 , Figure 3 , Figure 8 and Figure 12 , which are not repeated hereinafter. In an embodiment, the subtraction unit 622 can be implemented by the subtraction unit 522 in Figure 12 . Each of the emission control units 623_1, 623_2 can be implemented by the emission control unit 523 in Figure 12 .

[0114] A subtraction unit 622 is coupled to the emission control units 623_1, 623_2. The subtraction unit 622 provides a subtraction signal SS to the emission control units 623_1, 623_2. The emission control unit 623_1 is coupled to the semiconductor element 610_1 and is operated to provide an emission current from the current source 630 to the semiconductor element 610_1 in the first operation control period. The emission control unit 623_2 is coupled to the semiconductor element 610_2 and is operated to provide an emission current from the current source 630 to the semiconductor element 610_2 in the second operation control period.

[0115] An emission enable line EML1 provides a first emission enable signal EM1 for operation in the first operation control period. For example, the emission enable line EML1 is coupled to the emission control unit 623_1. In the first operation control period, the emission enable line EML1 transmits the first emission enable signal EM1 to the emission control unit 623_1. Thus, in the first operation control period, the operation period of the semiconductor element 610_1 is determined by the subtraction signal SS.

[0116] An emission enable line EML2 provides a second emission enable signal EM2 for operation in the second operation control period. For example, the emission enable line EML2 is coupled to the emission control unit 623_2. In the second operation control period, the emission enable line EML2 transmits the second emission enable signal EM2 to the emission control unit 623_2. Thus, in the second operation control period, the operation period of the semiconductor element 610_2 is determined by the subtraction signal SS. In other words, the semiconductor elements 610_1, 610_2 are operated by the same subtraction signal SS in different operation control periods. In other words, the operation control periods of the plurality of semiconductor elements 610_1, 610_2 are specified by corresponding subtraction signals SS and emission enable signals EM1, EM2.

[0117] Figure 14 A schematic diagram of a subtraction unit according to a ninth embodiment of the disclosure is shown. Referring to FIG. 11, a subtraction unit 1122 is coupled to the emission control units 1123_1, 1123_2. The subtraction unit 1122 provides a subtraction signal SS to the emission control units 1123_1, 1123_2. The emission control unit 1123_1 is coupled to the semiconductor element 1110_1 and is operated to provide an emission current from the current source 1130 to the semiconductor element 1110_1 in the first operation control period. The emission control unit 1123_2 is coupled to the semiconductor element 1110_2 and is operated to provide an emission current from the current source 1130 to the semiconductor element 1110_2 in the second operation control period. Figure 14In an embodiment, the electronic device 700 includes semiconductor elements 710_1, 710_2, 710_3, a pixel circuit 720, current sources 730_1, 730_2, 730_3, and an emission enable line EML. The pixel circuit 720 includes comparators 721_B, 721_A1, 721_A2, 721_A3, subtraction units 722_1, 722_2, 722_3, and emission control units 723_1, 723_2, 723_3. The comparator 721_B generates a first comparison signal SC_B according to a first data signal REF and a scan signal SWP. The first data signal REF is a reference signal. The comparator 721_A1 generates a second comparison signal SC_A1 according to a second data signal SD_A1 and the scan signal SWP. The comparator 721_A2 generates a second comparison signal SC_A2 according to a second data signal SD_A2 and the scan signal SWP. The comparator 721_A3 generates a second comparison signal SC_A3 according to a second data signal SD_A3 and the scan signal SWP.

[0118] The subtraction unit 722_1 is coupled to the comparators 721_B, 721_A3, and the emission control unit 723_1. The subtraction unit 722_1 generates a subtraction signal SS1 according to the first comparison signal SC_B and the second comparison signal SC_A3, and provides the subtraction signal SS1 to the emission control unit 723_1. The subtraction unit 722_2 is coupled to the comparators 721_B, 721_A2, and the emission control unit 723_2. The subtraction unit 722_2 generates a subtraction signal SS2 according to the first comparison signal SC_B and the second comparison signal SC_A2, and provides the subtraction signal SS2 to the emission control unit 723_2. The subtraction unit 722_3 is coupled to the comparators 721_B, 721_A1, and the emission control unit 723_3. The subtraction unit 722_3 generates a subtraction signal SS3 according to the first comparison signal SC_B and the second comparison signal SC_A1, and provides the subtraction signal SS3 to the emission control unit 723_3. In an embodiment, the subtraction signals SS1, SS2, SS3 are generated based on the same first comparison signal SC_B from the comparator 721_B. Thus, the circuit area of the pixel circuit 720 can be reduced.

[0119] The emission enable line EML is coupled to the semiconductor elements 710_1, 710_2, 710_3. In an embodiment, the emission enable line EML is coupled to the emission control units 723_1, 723_2, 723_3. The emission enable line EML transmits an emission enable signal EM to the emission control units 723_1, 723_2, 723_3. The emission control unit 723_1 provides an emission current IE1 from the current source 730_1 to the semiconductor element 710_1 in response to the subtraction signal SS1 and the emission enable signal EM. The emission control unit 723_2 provides an emission current IE2 from the current source 730_2 to the semiconductor element 710_2 in response to the subtraction signal SS2 and the emission enable signal EM. The emission control unit 723_3 provides an emission current IE3 from the current source 730_3 to the semiconductor element 710_3 in response to the subtraction signal SS3 and the emission enable signal EM. Thus, the semiconductor elements 710_1, 710_2, 710_3 emit light based on different subtraction signals in the same operation control period. In an embodiment, each of the emission control units 723_1, 723_2, 723_3 can be implemented by the emission control unit 523 in FIG. 5. Figure 12

[0120] In an embodiment, the semiconductor element 710_1 emits light L1. The semiconductor element 710_2 emits light L2. The semiconductor element 710_3 emits light L3. For example, the semiconductor element 710_1 emits light L1 having a first color light. The semiconductor element 710_2 emits light L2 having a second color light. The semiconductor element 710_3 emits light L3 having a third color light. For example, the semiconductor element 710_1 emits blue light. The semiconductor element 710_2 emits light L2 having green light. The semiconductor element 710_3 emits light L3 having red light.

[0121] In summary, in the embodiments of the present disclosure, the subtraction unit generates a subtraction signal according to a first comparison signal from the first comparator and a second comparison signal from the second comparator. Voltage errors caused by the first comparator and the second comparator can be eliminated. Thus, voltage errors caused by transistors in the electronic device can be reduced.

[0122] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of the disclosed embodiments provided they fall within the scope of the appended claims and their equivalents.​

Claims

1. An electronic device, characterized in that, The electronic device includes: At least one semiconductor element; and Pixel circuitry, coupled to the at least one semiconductor element, includes: The first comparator is configured to generate a first comparison signal; The second comparator is configured to generate a second comparison signal; and At least one subtraction unit is coupled to the at least one semiconductor element and configured to receive the first comparison signal and the second comparison signal, and to generate a subtraction signal. One of the at least one subtraction unit includes: A first thin-film transistor, wherein a first terminal of the first thin-film transistor is configured to receive the first comparison signal, and a control terminal of the first thin-film transistor is configured to receive a transmit enable signal; A second thin-film transistor, wherein a first terminal of the second thin-film transistor is coupled to a second terminal of the first thin-film transistor, and a control terminal of the second thin-film transistor is configured to receive the second comparison signal; A third thin-film transistor, wherein a first terminal of the third thin-film transistor is coupled to a second terminal of the second thin-film transistor, the second terminal of the third thin-film transistor is coupled to a low reference voltage, and a control terminal of the third thin-film transistor is configured to receive the second comparison signal; A fourth thin-film transistor, wherein a first terminal of the fourth thin-film transistor is coupled to a second terminal of the second thin-film transistor, a second terminal of the fourth thin-film transistor is coupled to the low reference voltage, and a control terminal of the fourth thin-film transistor is configured to receive the transmit enable signal; and An enabling thin-film transistor, wherein a first terminal of the enabling thin-film transistor is configured to receive an emission current, a second terminal of the enabling thin-film transistor is coupled to the at least one semiconductor element, and a control terminal of the enabling thin-film transistor is coupled to the second terminal of the second thin-film transistor and configured to receive the subtraction signal.

2. The electronic device according to claim 1, characterized in that, One of the at least one semiconductor element includes at least one light-emitting diode.

3. The electronic device according to claim 1, characterized in that, The first comparator includes: A fourth thin-film transistor, wherein a first terminal of the fourth thin-film transistor is coupled to a first data line and configured to receive a first data signal; A fifth thin-film transistor, wherein a first terminal of the fifth thin-film transistor is configured to receive a scan signal; A first capacitor, wherein a first terminal of the first capacitor is coupled to a second terminal of the fourth thin-film transistor and a second terminal of the fifth thin-film transistor; A first comparator element, wherein a first terminal of the first comparator element is coupled to a second terminal of the first capacitor, and a second terminal of the first comparator element is coupled to the at least one subtraction unit; and A sixth thin-film transistor, wherein a first terminal of the sixth thin-film transistor is coupled to a first terminal of the first comparator element, and a second terminal of the sixth thin-film transistor is coupled to a second terminal of the first comparator element.

4. The electronic device according to claim 3, characterized in that: The control terminal of the fourth thin-film transistor is configured to receive a first control signal. The control terminal of the fifth thin-film transistor is configured to receive the first control signal, and The control terminal of the sixth thin-film transistor is configured to receive the first control signal.

5. The electronic device according to claim 3, characterized in that, The second comparator includes: The seventh thin-film transistor; An eighth thin-film transistor, wherein a first terminal of the eighth thin-film transistor is configured to receive the scan signal; A second capacitor, wherein the first terminal of the second capacitor is coupled to the second terminal of the seventh thin-film transistor and the second terminal of the eighth thin-film transistor; A second comparator element, wherein a first terminal of the second comparator element is coupled to a second terminal of the second capacitor, and a second terminal of the second comparator element is coupled to the at least one subtraction unit; and A ninth thin-film transistor, wherein a first terminal of the ninth thin-film transistor is coupled to the first terminal of the second comparator, and a second terminal of the ninth thin-film transistor is coupled to the second terminal of the second comparator.

6. The electronic device according to claim 5, characterized in that: The control terminal of the seventh thin-film transistor is configured to receive a second control signal. The control terminal of the eighth thin-film transistor is configured to receive the second control signal, and The control terminal of the ninth thin-film transistor is configured to receive the second control signal.

7. The electronic device according to claim 1, characterized in that, The pixel circuit also includes: A transmit control unit, coupled to the at least one subtraction unit and the at least one semiconductor element, is configured to transmit transmit current to the at least one semiconductor element in response to the subtraction signal and the transmit enable signal.

8. An electronic device, characterized in that, The electronic device includes: At least one semiconductor element; and Pixel circuitry, coupled to the at least one semiconductor element, includes: The first comparator is configured to generate a first comparison signal; The second comparator is configured to generate a second comparison signal; and At least one subtraction unit is coupled to the at least one semiconductor element and configured to receive the first comparison signal and the second comparison signal, and to generate a subtraction signal. One of the at least one subtraction unit includes: A first thin-film transistor, wherein a first terminal of the first thin-film transistor is coupled to a high reference voltage, and a control terminal of the first thin-film transistor is configured to receive the first comparison signal; A second thin-film transistor, wherein a first terminal of the second thin-film transistor is coupled to a second terminal of the first thin-film transistor, the second terminal of the second thin-film transistor is configured to receive the second comparison signal, and a control terminal of the second thin-film transistor is configured to receive the first comparison signal; A third thin-film transistor, wherein a first terminal of the third thin-film transistor is coupled to a second terminal of the first thin-film transistor, and a control terminal of the third thin-film transistor is configured to receive a transmit enable signal; A fourth thin-film transistor, wherein a first terminal and a control terminal of the fourth thin-film transistor are configured to receive the transmit enable signal, and a second terminal of the fourth thin-film transistor is coupled to a second terminal of the third thin-film transistor; and An enabling thin-film transistor, wherein a first terminal of the enabling thin-film transistor is configured to receive an emission current, a second terminal of the enabling thin-film transistor is coupled to the at least one semiconductor element, and a control terminal of the enabling thin-film transistor is coupled to the second terminal of the third thin-film transistor and configured to receive the subtraction signal.

9. An electronic device, characterized in that, The electronic device includes: At least one semiconductor element; and Pixel circuitry, coupled to the at least one semiconductor element, includes: The first comparator is configured to generate a first comparison signal; The second comparator is configured to generate a second comparison signal; and At least one subtraction unit is coupled to the at least one semiconductor element and configured to receive the first comparison signal and the second comparison signal, and to generate a subtraction signal. One of the at least one subtraction unit includes: A first thin-film transistor, wherein a first terminal of the first thin-film transistor is configured to receive the first comparison signal, and a control terminal of the first thin-film transistor is configured to receive a transmit enable signal; A second thin-film transistor, wherein a first terminal of the second thin-film transistor is coupled to a second terminal of the first thin-film transistor, and a control terminal of the second thin-film transistor is configured to receive the second comparison signal. A third thin-film transistor, wherein a first terminal of the third thin-film transistor is coupled to a second terminal of the second thin-film transistor, the second terminal of the third thin-film transistor is coupled to a low reference voltage, and a control terminal of the third thin-film transistor is configured to receive the second comparison signal; A fourth thin-film transistor, wherein a first terminal of the fourth thin-film transistor is coupled to a second terminal of the second thin-film transistor, a second terminal of the fourth thin-film transistor is coupled to the low reference voltage, and a control terminal of the fourth thin-film transistor is configured to receive the transmit enable signal; Inverter, wherein the input terminals of the inverter are configured to receive the first comparison signal; and A fifth thin-film transistor, wherein a first terminal of the fifth thin-film transistor is coupled to a second terminal of the second thin-film transistor, a second terminal of the fifth thin-film transistor is coupled to the low reference voltage, and a control terminal of the fifth thin-film transistor is coupled to the output terminal of the inverter.

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