Pixel circuit, driving method thereof and display panel

Abstract

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving module, a storage module, a data writing module, an initialization module and a light emitting module. The driving module comprises a double-gate transistor, the first electrode of the double-gate transistor is connected with a first power supply, the second electrode of the double-gate transistor is connected with the first end of the light emitting module, and the second end of the light emitting module is connected with a second power supply. The data writing module is connected between the first gate of the double-gate transistor and a data line. The storage module is connected with the first gate, the second gate and the second electrode of the double-gate transistor. The initialization module is connected with the first gate, the second gate, the second electrode of the double-gate transistor and an initialization signal line. The initialization module can control the storage module to store the associated information of the threshold voltage of the double-gate transistor. The technical scheme provided by the embodiment of the application can compensate the threshold voltage fluctuation in a large range, and is beneficial to improving the display effect.

Description

Technical Field

[0001] The present invention relates to display technology, and more particularly to a pixel circuit, a driving method thereof, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have become a research hotspot in the field due to their low power consumption, low production cost, and self-emissive characteristics.

[0003] Existing technologies typically improve the brightness uniformity of the entire display by compensating the threshold voltage of the pixel circuit. However, the existing technical solutions have a small threshold voltage compensation range, which cannot meet the requirements for uniform display brightness. Summary of the Invention

[0004] This invention provides a pixel circuit, its driving method, and a display panel to improve the threshold compensation capability of the pixel circuit and enhance the display effect.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a driving module, a storage module, a data writing module, an initialization module, and a light-emitting module;

[0006] The driving module includes a dual-gate transistor, the first terminal of which is connected to a first power supply, the second terminal of which is connected to a first terminal of the light-emitting module, and the second terminal of the light-emitting module is connected to a second power supply.

[0007] The data writing module is connected between the first gate of the dual-gate transistor and the data line, and is used to transmit the data voltage output by the data line to the first gate.

[0008] The storage module is connected to the first gate, the second gate, and the second electrode of the dual-gate transistor;

[0009] The initialization module is connected to the first gate, second gate, second electrode, and initialization signal line of the dual-gate transistor, and is used to transmit the voltage provided by the initialization signal line to the first gate, second gate, and second electrode of the dual-gate transistor, and control the storage module to store the threshold voltage association information of the dual-gate transistor.

[0010] Optionally, the initialization signal line includes a first initialization signal line and a second initialization signal line. The initialization module is used to transmit the first initialization voltage provided by the first initialization line to the second gate, and to transmit the second initialization voltage provided by the second initialization signal line to the first gate and the second gate of the dual-gate transistor.

[0011] Preferably, the data line is multiplexed as the first initialization signal line.

[0012] Optionally, the initialization module includes a first initialization module, a second initialization module, and a third initialization module;

[0013] The first initialization module is connected between the first initialization signal line and the second gate, and the control terminal of the first initialization module is connected to the first scan line; the second initialization module is connected between the second initialization signal line and the second electrode of the dual-gate transistor, and the control terminal of the second initialization module is connected to the second scan line; the third initialization module is connected between the first gate and the second electrode of the dual-gate transistor, and the control terminal of the third initialization module is connected to the first scan line.

[0014] Optionally, the first gate is a top gate and the second gate is a bottom gate; the data writing module includes a first transistor, the first initialization module includes a second transistor, the second initialization module includes a third transistor, and the third initialization module includes a fourth transistor; the storage module includes a first capacitor and a second capacitor.

[0015] The first terminal of the first transistor is connected to the data line, the second terminal of the first transistor is connected to the first gate, and the gate of the first transistor is connected to the second scan line;

[0016] The first terminal of the second transistor is connected to the first initialization signal line, the second terminal of the second transistor is connected to the second gate, and the gate of the second transistor is connected to the first scan line;

[0017] The first terminal of the third transistor is connected to the second initialization signal line, the second terminal of the third transistor is connected to the second terminal of the dual-gate transistor, and the gate of the third transistor is connected to the second scan line;

[0018] The first terminal of the fourth transistor is connected to the first gate, the second terminal of the fourth transistor is connected to the second terminal of the dual-gate transistor, and the gate of the fourth transistor is connected to the first scan line;

[0019] The first capacitor is connected between the first gate and the second terminal of the dual-gate transistor, and the second capacitor is connected between the second gate and the second terminal of the dual-gate transistor.

[0020] Preferably, the aspect ratio of the fourth transistor is smaller than that of the third transistor.

[0021] Optionally, within a frame, the signal transmitted by the second scan line includes a first pulse and a second pulse, wherein the interval of the first pulse overlaps with the rising edge of the pulse on the signal transmitted by the first scan line, and the second pulse follows the pulse on the signal transmitted by the first scan line.

[0022] Optionally, the first scan line and the second scan line, the first initialization signal line and the second initialization signal line are configured to transmit drive signals to satisfy:

[0023] During the initialization phase, the third transistor is turned on, and then the second transistor and the fourth transistor are turned on;

[0024] During the threshold detection phase, the second transistor and the fourth transistor are turned on, and the third transistor is turned off.

[0025] During the data writing phase, the first transistor and the third transistor are turned on, while the second transistor and the fourth transistor are turned off;

[0026] During the light-emitting phase, the first transistor, the second transistor, the third transistor, and the fourth transistor are all turned off.

[0027] Secondly, embodiments of the present invention also provide a driving method for a pixel circuit, the pixel circuit comprising: a driving module, a storage module, a data writing module, an initialization module, and a light-emitting module; the driving module includes a dual-gate transistor, the first terminal of the dual-gate transistor being connected to a first power supply, the second terminal of the dual-gate transistor being connected to a first terminal of the light-emitting module, and the second terminal of the light-emitting module being connected to a second power supply; the data writing module is connected between the first gate of the dual-gate transistor and a data line; the storage module is connected to the first gate, the second gate, and the second terminal of the dual-gate transistor; the initialization module is connected to the first gate, the second gate, the second terminal, and the initialization signal line of the dual-gate transistor.

[0028] The driving method includes:

[0029] During the initialization phase, the control module transmits the corresponding initialization voltage to the first gate, second gate, and second electrode of the dual-gate transistor;

[0030] During the threshold detection phase, the initialization module is controlled to cause the storage module to store the associated information of the threshold voltage of the dual-gate transistor;

[0031] During the data writing phase, the data writing module is controlled to transmit the data voltage provided by the data line to the first gate.

[0032] Optionally, the storage module includes a first capacitor and a second capacitor, and the initialization module includes a first initialization module, a second initialization module, and a third initialization module. The first initialization module is connected between the first initialization signal line and the second gate; the control terminal of the first initialization module is connected to the first scan line; the second initialization module is connected between the second initialization signal line and the second gate, and the control terminal of the second initialization module is connected to the second scan line; the third initialization module is connected between the first gate and the second gate, and the control terminal of the third initialization module is connected to the first scan line.

[0033] During the initialization phase, the second scan signal transmitted by the second scan line controls the second initialization module to turn on, and after a preset time, the first scan signal transmitted by the first scan line controls the first initialization module and the third initialization module to turn on.

[0034] During the threshold detection phase, the second scanning signal controls the second initialization module to turn off, and the first scanning signal controls the first initialization module and the third initialization module to turn on.

[0035] During the data writing phase, the second scan signal controls the data writing module and the second initialization module to be turned on, and the first scan signal controls the first initialization module and the third initialization module to be turned off.

[0036] During the light emission stage, the second scanning signal controls the data writing module and the second initialization module to shut down, and the first scanning signal controls the first initialization module and the third initialization module to shut down.

[0037] Optionally, the initialization phase and the threshold detection phase are executed within each frame or after at least two frames, and the data writing phase and the emission phase are executed within each frame;

[0038] Preferably, the initialization phase and the threshold detection phase occur during the blank period between frames.

[0039] Thirdly, embodiments of the present invention also provide a display panel, including the pixel circuit provided in any embodiment of the present invention.

[0040] The technical solution provided by this invention improves display performance by designing a novel pixel circuit. This pixel circuit includes a driving module, a storage module, a data writing module, an initialization module, and a light-emitting module. The driving module includes a dual-gate transistor. The data writing module is connected between the first gate of the dual-gate transistor and a data line. The storage module is connected to the first gate, second gate, and second electrode of the dual-gate transistor. The initialization module is connected to the first gate, second gate, second electrode, and initialization signal line of the dual-gate transistor. Compared to existing technologies, the technical solution provided by this invention controls the potentials of the first gate, second gate, and second electrode of the dual-gate transistor through the initialization module, and controls the first gate and second electrode of the dual-gate transistor to form a diode connection structure. This allows the threshold voltage of the dual-gate transistor to be determined by the potential difference between the second gate and the second electrode, thereby achieving a threshold voltage compensation effect. Furthermore, threshold compensation and data writing are implemented through two separate paths, without affecting each other. By controlling the conduction duration of the initialization module, the threshold voltage compensation duration can be controlled, thereby compensating for threshold voltage fluctuations over a larger range, ensuring complete threshold voltage compensation, and ultimately improving display performance. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0045] Figure 5 A control timing waveform diagram of a pixel circuit provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0049] Figure 9 A characteristic curve of a dual-gate transistor provided in an embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0051] Figure 11 A flowchart of a pixel circuit driving method provided in an embodiment of the present invention;

[0052] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0053] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0054] As described in the background section, existing pixel circuits cannot meet the requirements for uniform display brightness. The inventors have discovered that this problem arises because existing pixel circuits typically perform threshold voltage compensation simultaneously with data writing. By controlling the data writing module to conduct, the threshold voltage of the driving module is compensated. This compensation time is limited by the conduction time of the data writing module, resulting in a fixed threshold compensation time. Consequently, the threshold voltage is not fully compensated after data writing is completed, limiting the threshold voltage compensation range. At higher refresh rates, the frame time is compressed further, significantly reducing the threshold compensation time. Furthermore, differences still exist between the driving circuits of different pixels, leading to variations in the driving current generated, which in turn affects the uniformity of display brightness.

[0055] To address the aforementioned problems, embodiments of the present invention provide a novel pixel circuit structure to improve the uniformity of display brightness. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1The pixel circuit provided in this embodiment of the invention includes a driving module 110, a storage module 120, a data writing module 130, an initialization module 140, and a light-emitting module 150. The driving module 110 includes a dual-gate transistor T0, the first terminal D of the dual-gate transistor T0 is connected to a first power supply ELVDD, the second terminal S of the dual-gate transistor T0 is connected to a first terminal of the light-emitting module 150, and the second terminal of the light-emitting module 150 is connected to a second power supply ELVSS. The data writing module 130 is connected between the first gate G1 of the dual-gate transistor T0 and the data line Data, and is used to transmit the data voltage output by the data line Data to the first gate G1. The storage module 120 is connected to the first gate G1, the second gate G2, and the second terminal S of the dual-gate transistor T0. The initialization module 140 is connected to the first gate G1, the second gate G2, the second terminal S, and the initialization signal line Rest of the dual-gate transistor T0, and is used to transmit the voltage provided by the initialization signal line Rest to the first gate G1, the second gate G2, and the second terminal S of the dual-gate transistor T0, and control the storage module 120 to store the threshold voltage association information of the dual-gate transistor T0.

[0056] Specifically, the dual-gate transistor T0 serves as the driving transistor for the pixel circuit, driving the light-emitting module 150 to emit light. The dual-gate transistor T0 is typically a vertical dual-gate transistor, with the first gate G1 being the top gate and the second gate G2 being the bottom gate. The threshold voltage of the dual-gate transistor T0 is adjusted by setting the voltage between the second gate G2 and the second electrode S, thus completing the extraction and compensation of the threshold voltage.

[0057] The operation of the pixel circuit provided in this embodiment of the invention includes at least an initialization stage, a threshold detection stage, and a data writing stage, such as... Figure 1 As shown, during the initialization phase, the initialization module 140 is turned on, transmitting the voltage on the initialization signal line Rest to the first gate G1, second gate G2, and second terminal S of the dual-gate transistor T0, respectively, thereby initializing the potentials of the first gate G1, second gate G2, and second terminal S of the dual-gate transistor T0. The voltage difference between the voltage provided by the initialization signal line Rest and the second power supply ELVSS can be set to be less than the threshold voltage of the light-emitting module 150 to ensure that the light-emitting module 150 does not emit light during this phase. During this phase, the initialization module 140 controls the first gate G1 and second terminal S of the dual-gate transistor T0 to form a diode connection, making the potentials of the first gate G1 and second terminal S of the dual-gate transistor T0 equal, and configures the voltage of the second gate G2 of the dual-gate transistor T0 to adjust the threshold voltage of the dual-gate transistor T0 to be greater than 0V (the dual-gate transistor T0 is an N-type transistor), thus keeping the dual-gate transistor T0 in the off state.

[0058] During the threshold detection phase, since the initialization module 140 controls the potentials of the first gate G1 and the second terminal S of the dual-gate transistor T0 to be equal, that is, the voltage difference between the first gate G1 and the second terminal S of the dual-gate transistor T0 is 0V, the threshold voltage of the dual-gate transistor T0 is determined by the voltage difference between the second gate G2 and the second terminal S of the dual-gate transistor T0. Specifically, during the threshold detection phase, the initialization module 140 releases the control over the voltage of the second terminal S of the dual-gate transistor T0, and the voltage change of the second terminal S of the dual-gate transistor T0 becomes the sum of the second power supply ELVSS voltage and the threshold voltage of the light-emitting module 150. Furthermore, by controlling the potential of the second gate G2 of the dual-gate transistor T0 to remain constant and controlling the first gate G1 and the second terminal S of the dual-gate transistor T0 to maintain a diode connection, since the potential of the second gate G2 remains constant, the voltage difference between the second gate G2 and the second terminal S changes, that is, the threshold voltage of the dual-gate transistor T0 changes, causing the dual-gate transistor T0 to conduct. The above statement can be simply understood as follows: since the voltage difference between the first gate G1 and the second gate S of the dual-gate transistor T0 is 0V, and the voltage of the second gate G2 remains unchanged, by changing the voltage of the second gate S, the voltage difference between the second gate G2 and the second gate S changes, thereby making the threshold voltage of the dual-gate transistor T0 less than 0V, and controlling the dual-gate transistor T0 to conduct.

[0059] When the dual-gate transistor T0 is turned on, the voltage on the first power supply ELVDD charges the second terminal S through the dual-gate transistor T0, raising the potential of the second terminal S and the first gate G1, but the voltage difference between the second terminal S and the first gate G1 remains 0V. When the voltage of the second terminal S rises to the point that the threshold voltage of the dual-gate transistor T0 is equal to the voltage difference between the first gate G1 and the second terminal S, that is, when the threshold voltage of the dual-gate transistor T0 is 0V, the dual-gate transistor T0 is turned off, and the storage module 120 stores the voltage of the second terminal S. Thus, the detection of the threshold voltage of the dual-gate transistor T0 is completed. In other words, by controlling the voltage difference between the first gate G1 and the second terminal S of the dual-gate transistor T0 to be 0V, the information related to the threshold voltage of the dual-gate transistor T0 stored in the storage module 120 is the voltage difference between the second gate G2 and the second terminal S when the threshold voltage of the dual-gate transistor T0 is 0V.

[0060] During the data writing phase, the data writing module 130 is turned on, and the data voltage transmitted on the data line Data is written to the first gate G1 of the dual-gate transistor T0.

[0061] In this embodiment, since the threshold detection phase and the data writing phase are not performed simultaneously, the duration of the threshold detection phase can be determined by the conduction duration of the initialization module 140, and is independent of the data writing duration. That is, by controlling the storage module 120 to store the associated information of the threshold voltage of the dual-gate transistor T0 through the initialization module 140, the threshold voltage of the dual-gate transistor T0 can be extracted, ensuring that the data writing phase and the threshold detection phase do not interfere with each other. By controlling the conduction duration of the initialization module 140 to adjust the threshold detection duration, threshold compensation over a wide range can be achieved, adapting to applications with high refresh rates.

[0062] The pixel circuit provided in this embodiment of the invention includes a driving module, a storage module, a data writing module, an initialization module, and a light-emitting module. The driving module includes a dual-gate transistor. The data writing module is connected between the first gate of the dual-gate transistor and a data line. The storage module is connected to the first gate, second gate, and second electrode of the dual-gate transistor. The initialization module is connected to the first gate, second gate, second electrode, and initialization signal line of the dual-gate transistor. Compared with the prior art, the technical solution provided in this embodiment of the invention controls the potential of the first gate, second gate, and second electrode of the dual-gate transistor through the initialization module, and controls the first gate and second electrode of the dual-gate transistor to form a diode connection structure, so that the threshold voltage of the dual-gate transistor is determined by the potential difference between the second gate and the second electrode, thereby achieving the threshold voltage compensation effect of the dual-gate transistor. Moreover, threshold compensation and data writing are implemented through two separate paths, which do not affect each other. By controlling the conduction time of the initialization module, the compensation time of the threshold voltage can be controlled, thereby compensating for threshold voltage fluctuations over a large range, so that the threshold voltage can be fully compensated, which is beneficial to improving the display effect.

[0063] Optionally, Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 2 Based on the above technical solution, the initialization signal line Rest includes a first initialization signal line Vref and a second initialization signal line Vini. The initialization module 140 is used to transmit the first initialization voltage provided by the first initialization line Vref to the second gate G2, and to transmit the second initialization voltage provided by the second initialization signal line Vini to the first gate G1 and the second gate S of the dual-gate transistor T0.

[0064] Specifically, different initialization voltages can be transmitted to the first gate G1, second gate G2, and second terminal S of the dual-gate transistor T0 via the first initialization line Vref and the second initialization signal line Vini, respectively, to initialize the first gate G1, second gate G2, and second terminal S of the dual-gate transistor T0. By configuring the initialization voltages provided on the first initialization line Vref and the second initialization signal line Vini, it is beneficial to control the dual-gate transistor T0 to turn off during the initialization phase while ensuring that the voltage at the first terminal of the light-emitting module 150 is less than the voltage at its second terminal, preventing the light-emitting module 150 from emitting light during this phase. Optionally, the data line Data can be multiplexed as the first initialization signal line Vref. During the initialization phase, the initialization voltage is provided to the initialization module 140 via the data line Data, which can save the number of first initialization signal lines Vref and improve the PPI. During the data writing phase, the voltage transmitted on the data line Data jumps to the data voltage to complete the writing of the data voltage to the first gate of the dual-gate transistor T0.

[0065] Furthermore, during the threshold detection stage, since it is necessary to maintain the potential of the second gate G2 of the dual-gate transistor T0 stable, and the initialization module 140 no longer controls the potential of the second terminal S of the dual-gate transistor T0, the first gate G1, the second gate G2, and the second terminal S of the dual-gate transistor T0 can be controlled through different paths respectively. For ease of description, in this embodiment, the voltage on the signal line and the corresponding signal line are represented by the same symbol. Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 3 Based on the above technical solutions, the initialization module 140 includes a first initialization module 141, a second initialization module 142, and a third initialization module 143. The first initialization module 141 is connected between the first initialization signal line Vref and the second gate G2, and its control terminal is connected to the first scan line S1. The second initialization module 142 is connected between the second initialization signal line Vini and the second electrode S of the dual-gate transistor T0, and its control terminal is connected to the second scan line S2. The third initialization module 143 is connected between the first gate G1 and the second electrode S of the dual-gate transistor T0, and its control terminal is connected to the first scan line S1. In other embodiments provided by this invention, the first initialization signal line Vref and the second initialization signal line Vini can be combined into one line; in other words, the first initialization module 141 and the second initialization module 142 are connected to the same initialization signal line. This can save the number of initialization signal lines, improve PPI, and reduce costs.

[0066] Specifically, the first initialization module 141 and the third initialization module 143 are both controlled by the first scan line S1, and the second initialization module 142 is controlled by the second scan line S2. The first initialization module 141 is used to turn on or off in response to a signal on the first scan line S1. When the first initialization module 141 is turned on, it writes a first initialization voltage Vref to the second gate G2 of the dual-gate transistor T0. The second initialization module 142 is used to turn on or off in response to a signal on the second scan line S2. When the second initialization module 142 is turned on, it writes a second initialization voltage to the second gate S of the dual-gate transistor T0. The third initialization module 143 is used to write a second initialization voltage to the first gate G1 of the dual-gate transistor T0 in response to a signal on the first scan line S1.

[0067] Optionally, Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, and specifically illustrates the specific structure of the pixel circuit. (Refer to...) Figure 4 The data writing module 130 includes a first transistor T1, the first initialization module 141 includes a second transistor T2, the second initialization module 142 includes a third transistor T3, and the third initialization module 143 includes a fourth transistor T4; the storage module 120 includes a first capacitor C1 and a second capacitor C2.

[0068] The first transistor T1 has its first terminal connected to the data line Data, its second terminal connected to the first gate G1, and its gate connected to the second scan line S2; the second transistor T2 has its first terminal connected to the first initialization signal line Vref, its second terminal connected to the second gate G2, and its gate connected to the first scan line S1; the third transistor T3 has its first terminal connected to the second initialization signal line Vini, its second terminal connected to the second terminal S of the dual-gate transistor T0, and its gate connected to the second scan line S2; the fourth transistor T4 has its first terminal connected to the first gate G1, its second terminal connected to the second terminal S of the dual-gate transistor T0, and its gate connected to the first scan line S1; the first capacitor C1 is connected between the first gate G1 and the second terminal S of the dual-gate transistor T0, and the second capacitor C2 is connected between the second gate G2 and the second terminal S of the dual-gate transistor T0.

[0069] In this embodiment, the dual-gate transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type transistors. Figure 5 A control timing waveform diagram for a pixel circuit provided in this embodiment of the invention is applicable to... Figure 4 The pixel circuit shown. Combined with... Figure 4 and Figure 5The working process of the pixel circuit provided in this embodiment of the invention includes at least: initialization stage t1, threshold detection stage t2, data writing stage t3, and light emission stage t4.

[0070] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, corresponding to the initialization stage t1. In the initialization stage t1, the third transistor T3 is turned on in response to a high-level signal on the second scan line S2, and the second initialization voltage on the second initialization signal line Vini is transmitted to the second terminal S of the dual-gate transistor T0, initializing the potential of the second terminal S. Afterwards, the second transistor T2 and the fourth transistor T4 are turned on, respectively transmitting the first initialization voltage on the first initialization signal line Vref and the second initialization voltage on the second initialization signal line Vini to the second gate G2 and the first gate G1 of the dual-gate transistor T0, completing the initialization of the two gate potentials of the dual-gate transistor T0.

[0071] By configuring the second initialization signal line Vini to transmit the second initialization voltage, the voltage difference between the second initialization voltage and the second power supply ELVSS is less than the threshold voltage (light-up voltage) of the OLED, ensuring that the OLED does not emit light during the initialization phase t1.

[0072] At this time, since the fourth transistor T4 is turned on, a diode connection is formed between the first gate G1 and the second terminal S of the dual-gate transistor T0, and the voltage difference between the first gate G1 and the second terminal S of the dual-gate transistor T0 is 0V. Therefore, by configuring the voltage of the second gate G2 of the dual-gate transistor T0 (i.e., the first initialization voltage), the threshold voltage of the dual-gate transistor T0 is adjusted to be greater than 0V, thus putting the dual-gate transistor T0 in the off state.

[0073] During the initialization phase t1, since the gate of the first transistor T1 is connected to the second scan line S2, the first transistor T1 is also turned on. By sharing the second scan line S2, the number of scan lines can be saved, which is beneficial to reducing the number of gate drive units. However, since the data line Data also transmits data voltage to the first gate G1 at this time, in order to prevent the potential of the second terminal S of the dual-gate transistor T0 from being pulled high, the aspect ratio of the first transistor T1 and the fourth transistor T4 can be set to be smaller than that of the third transistor T3, so that the switching speed of the third transistor T3 is greater than that of the fourth transistor T4. The potential of the second terminal S of the dual-gate transistor T0 is controlled by the second initialization voltage Vini transmitted on the second initialization signal line, so as to avoid the data voltage and the second initialization voltage Vini from affecting the potential of the second terminal S of the dual-gate transistor T0 at the same time, thus maintaining the potential stability of the second terminal S of the dual-gate transistor T0. At the same time, the rising edge of the first pulse on the signal transmitted on the second scan line S2 can overlap with the rising edge of the pulse on the signal transmitted on the first scan line S1. That is to say, after the third transistor T3 is turned on, the second transistor T2 and the fourth transistor T4 are turned on. This reduces the conduction time of the fourth transistor T4 during the initialization phase t1, thereby further improving the stability of the S potential of the second electrode of the dual-gate transistor T0.

[0074] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, corresponding to the threshold detection stage t2. In the threshold detection stage t2, the signal transmitted on the first scan line S1 is at a high level, and the signal transmitted on the second scan line S2 is at a low level. Therefore, the first transistor T1 and the third transistor T3 are turned off, while the second transistor T2 and the fourth transistor T4 are turned on. Since the third transistor T3 is turned off, the second initialization voltage on the second initialization signal line Vini no longer controls the potential of the second terminal S of the dual-gate transistor T0. Therefore, the voltage change of the second terminal S of the dual-gate transistor T0 is the sum of the second power supply ELVSS voltage and the threshold voltage of the light-emitting device OLED, and the potential of the second terminal S increases. Since the fourth transistor T4 remains on, the potential of the first gate G1 of the dual-gate transistor T0 is equal to the potential of the second terminal S, and the potential of the first gate G1 increases synchronously.

[0075] However, since the potential of the second gate G2 of the dual-gate transistor T0 is clamped by the first initialization voltage Vref, the voltage difference between the second gate G2 and the second terminal S changes. The voltage difference between the second gate G2 and the second terminal S of the dual-gate transistor T0 can adjust the threshold voltage of the dual-gate transistor T0. By configuring the second power supply voltage ELVSS and the first initialization voltage Vref, the threshold voltage of the dual-gate transistor T0 can be made less than 0V, thereby controlling the dual-gate transistor T0 to be turned on.

[0076] When the dual-gate transistor T0 is turned on, the first power supply ELVDD charges the second terminal S of the dual-gate transistor T0, and the potential of the second terminal S continues to rise. When the potential of the second terminal S of the dual-gate transistor T0 rises to the point that the voltage difference between the second gate G2 and the second terminal S makes the threshold voltage of the dual-gate transistor T0 equal to the voltage difference between the first gate G1 and the second terminal S, that is, when the threshold voltage of the dual-gate transistor T0 is 0V, the dual-gate transistor T0 turns off again. The voltages of the second gate G2 and the second terminal S are stored across the second capacitor C2, and the voltage difference between the second gate G2 and the second terminal S determines the threshold voltage of the dual-gate transistor T0. Thus, the detection of the threshold voltage of the dual-gate transistor T0 is completed.

[0077] Since the voltage difference between the first gate G1 and the second terminal S is controlled to be 0V by the second transistor T4, the threshold voltage of the dual-gate transistor T0 is obtained by controlling the voltage difference between the second gate G2 and the second terminal S, and the obtained threshold voltage is also 0V. Therefore, regardless of whether the threshold voltage of the dual-gate transistor T0 is positive or negative, it can be corrected to 0V by controlling the voltage difference between the second gate G2 and the second terminal S, thus expanding the compensation range of the threshold voltage. For example, in this embodiment, the threshold voltage range of the dual-gate transistor T0 can be between -5V and 5V.

[0078] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, corresponding to the data writing stage t3. In the data writing stage t3, the rising edge of the second pulse of the second scan line S2 arrives, and simultaneously, the first scan line S1 outputs a low-level signal. Therefore, the first transistor T1 and the third transistor T3 are turned on, while the second transistor T2 and the fourth transistor T4 are turned off. The data voltage on the data line Data is transmitted to the first gate G1 of the dual-gate transistor T0 and stored in the first capacitor C1. To prevent the OLED from emitting light, a second initialization voltage Vini is written to the second terminal S of the dual-gate transistor T0. Exemplarily, Figure 9 A characteristic curve of a dual-gate transistor provided in an embodiment of the present invention is shown below. Figure 9 I DS V is the current between the first terminal D and the second terminal S of the dual-gate transistor T0. G1SThis represents the voltage difference between the first gate G1 and the second gate S. By configuring the voltage difference between the second gate G2 and the second gate S of the dual-gate transistor T0, the threshold voltage can be corrected to 0V. For example, when the threshold voltage of the dual-gate transistor T0 is negative, by configuring the second initialization voltage Vini written to the second gate S of the dual-gate transistor T0, the threshold voltage can be corrected to 0V, making the threshold voltage less than the data voltage written to the first gate G1 of the dual-gate transistor T0, thus ensuring that the dual-gate transistor T0 is turned off. Simultaneously, by configuring the voltage at the second gate S of the dual-gate transistor T0, the impact of the voltage drop of the second power supply ELVSS on OLED light emission can be reduced.

[0079] In this embodiment, since the threshold detection stage t2 and the data writing stage t3 are performed separately, they do not affect each other. Compared with the prior art scheme in which threshold compensation and data writing are performed simultaneously, the technical solution provided in this embodiment is not affected by data writing during threshold compensation. The threshold compensation time is sufficient, which allows the threshold voltage to be fully compensated, avoiding the phenomenon of insufficient compensation. This results in a larger compensation range for the threshold voltage, which is beneficial to improving the compensation effect.

[0080] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, corresponding to the light-emitting stage t4. In the light-emitting stage t4, the signal output by the first scan line S1 is at a low level, and the signal output by the second scan line S2 is at a low level. Therefore, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off. At this time, the potential of the second electrode S of the dual-gate transistor T0 changes. By controlling the voltage difference between the second gate G2 and the second electrode S, the threshold voltage of the dual-gate transistor T0 is adjusted, causing the dual-gate transistor T0 to conduct. A path is formed between the first power supply ELVDD and the second power supply ELVSS, and the OLED light-emitting device emits light under the drive of the dual-gate transistor T0. Since the second capacitor C2 stores a voltage that makes the threshold voltage of the dual-gate transistor T0 0V, the driving current generated by the dual-gate transistor T0 is independent of its threshold voltage, which is beneficial to improving the uniformity of display brightness.

[0081] The luminous current generated by the dual-gate transistor T0 can be expressed as:

[0082]

[0083] During the threshold detection phase t2, since the threshold voltage of the dual-gate transistor T0 has been corrected to 0V, the aforementioned luminous current is:

[0084]

[0085] Where μ is the electron mobility of the dual-gate transistor T0, Cox is the channel capacitance per unit area of ​​the dual-gate transistor T0, W / L is the width-to-length ratio of the dual-gate transistor T0, Vth is the threshold voltage of the dual-gate transistor T0, and Vdata is the data voltage provided by the data line Data.

[0086] As shown in the above formula, the luminous current of the OLED is related to the data voltage Vdata and the second initialization voltage Vini. Since the threshold voltage Vth of the dual-gate transistor T0 is 0V, it does not affect the magnitude of the luminous current. Furthermore, the luminous current is not affected by the second power supply voltage VSS, thus compensating for the IR drop of the second power supply VSS.

[0087] In this embodiment, because the dual-gate transistor T0 is more stable than the single-gate transistor, its threshold voltage changes less under prolonged electrical stress. Therefore, after one threshold voltage detection is completed, a longer interval can be allowed before the next threshold voltage detection. In other words, threshold detection is not required for every frame, which simplifies the control timing of the pixel circuit and allows for faster driving.

[0088] Optionally, the threshold detection stage t2 can be set in the blank stage between detection and frame, so that the threshold voltage acquisition time is more sufficient, thereby ensuring that the threshold voltage can be fully compensated even in a large fluctuation range, which is conducive to expanding the compensation range of the threshold voltage.

[0089] Furthermore, since threshold detection is not required for every frame, the conduction time of the second transistor T2 and the fourth transistor T4 can be reduced, which can minimize the electrical stress on the second transistor T2 and the fourth transistor T4 and help improve the lifespan of the pixel circuit.

[0090] Of course, in other embodiments, initialization should not be performed every frame. Therefore, the initialization phase t1 and the threshold detection phase t2 can be executed at least two frames later. The initialization phase t1 can also be set in the blank period between detection and frame. If the initialization phase t1 is set in the blank period, the data line Data can be reused as the first initialization signal line Vref, meaning the second transistor T2 is connected to the data line Data, saving the first initialization signal line Vref. During the initialization phase, providing the initialization voltage to the second transistor T2 through the data line Data can save the number of first initialization signal lines Vref, which is beneficial for improving PPI and simplifying the panel design.

[0091] In the pixel circuit provided in this embodiment, there is no need to set up a light-emitting control transistor. Therefore, in the pixel circuit, the light-emitting control transistor will not consume the voltage across the first power supply ELVDD and the second power supply ELVSS, which helps to reduce the voltage across the first power supply ELVDD and the second power supply ELVSS, thereby improving the voltage stability of the first power supply ELVDD and the second power supply ELVSS. Compared with the prior art, the pixel circuit provided in this embodiment of the invention does not need to set up a light-emitting control transistor, which greatly reduces the occupied area of ​​the pixel circuit and is conducive to achieving a higher pixel density.

[0092] In this embodiment, the voltage across the second capacitor C2 can remain constant during the threshold voltage compensation process. Therefore, after the pixel circuit is fabricated, the threshold voltage can be detected by an external compensation method to ensure the uniformity of the display brightness.

[0093] Optionally, embodiments of the present invention also provide a driving method for a pixel circuit, applicable to the pixel circuits provided in any embodiment of the present invention. (See reference) Figure 1 The pixel circuit includes: a driving module 110, a storage module 120, a data writing module 130, an initialization module 140, and a light-emitting module 150; the driving module 110 includes a dual-gate transistor T0, the first terminal of which is connected to a first power supply ELVDD, the second terminal of which is connected to a first terminal of the light-emitting module 150, and the second terminal of the light-emitting module 150 is connected to a second power supply ELVSS; the data writing module 130 is connected between the first gate G1 of the dual-gate transistor T0 and the data line Data; the storage module 120 is connected to the first gate G1, the second gate G2, and the second terminal S of the dual-gate transistor T0; the initialization module 140 is connected to the first gate G1, the second gate G2, the second terminal S, and the initialization signal line Rest of the dual-gate transistor T0.

[0094] Figure 11 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, with reference to... Figure 11 The driving method includes:

[0095] S110. During the initialization phase, the control initialization module transmits the corresponding initialization voltage to the first gate, second gate, and second electrode of the dual-gate transistor.

[0096] S120. During the threshold detection phase, the control initialization module is used to enable the storage module to store the associated information of the threshold voltage of the dual-gate transistor.

[0097] S130. During the data writing phase, the control data writing module transmits the data voltage provided by the data line to the first gate.

[0098] The pixel circuit control method provided in this invention initializes the potentials of the first gate, second gate, and second electrode of the dual-gate transistor by controlling the initialization module to transmit the corresponding initialization voltage to the first gate, second gate, and second electrode of the dual-gate transistor during the initialization phase. During the threshold detection phase, the initialization module is controlled to store the threshold voltage association information of the dual-gate transistor in the storage module, enabling the detection and compensation of the threshold voltage. During the data writing phase, the data writing module writes the data voltage to the first gate of the dual-gate transistor. Compared to existing technologies, the technical solution provided in this invention controls the potentials of the first gate, second gate, and second electrode of the dual-gate transistor through the initialization module, and controls the first gate and second electrode of the dual-gate transistor to form a diode connection structure, so that the threshold voltage of the dual-gate transistor is determined by the potential difference between the second gate and the second electrode, thereby achieving the threshold voltage compensation effect. Furthermore, threshold compensation and data writing are implemented through two separate paths, which do not affect each other. By controlling the conduction duration of the initialization module, the compensation duration of the threshold voltage can be controlled, thereby compensating for threshold voltage fluctuations over a large range, ensuring complete compensation of the threshold voltage, and thus improving the display effect.

[0099] Further, refer to Figure 4 The initialization signal line Rest includes a first initialization signal line Vref and a second initialization signal line Vini. The initialization module 140 includes a first initialization module 141, a second initialization module 142, and a third initialization module 143. The first initialization module 141 is connected between the first initialization signal line Vref and the second gate G2, and the control terminal of the first initialization module 141 is connected to the first scan line S1. The second initialization module 142 is connected between the second initialization signal line Vini and the second electrode S of the dual-gate transistor T0, and the control terminal of the second initialization module 142 is connected to the second scan line S2. The third initialization module 143 is connected between the first gate G1 and the second electrode S of the dual-gate transistor T0, and the control terminal of the third initialization module 143 is connected to the first scan line S1.

[0100] The data writing module 130 includes a first transistor T1, the first initialization module 141 includes a second transistor T2, the second initialization module 142 includes a third transistor T3, and the third initialization module 143 includes a fourth transistor T4; the storage module 120 includes a first capacitor C1 and a second capacitor C2. Combined Figure 5 The control timing shown in the diagram, the driving method also includes:

[0101] During the initialization phase t1, the second scan signal transmitted by the second scan line S2 controls the second initialization module 142 to turn on. After a preset time, the first scan signal transmitted by the first scan line S1 controls the first initialization module 141 and the third initialization module 143 to turn on.

[0102] Specifically, by configuring the second initialization voltage transmitted by the second initialization signal line Vini, the voltage difference between the second initialization voltage and the second power supply ELVSS is less than the threshold voltage (light-up voltage) of the OLED, ensuring that the OLED does not emit light during the initialization phase t1.

[0103] At this time, since the fourth transistor T4 is turned on, a diode connection is formed between the first gate G1 and the second terminal S of the dual-gate transistor T0, and the voltage difference between the first gate G1 and the second terminal S of the dual-gate transistor T0 is 0V. Therefore, by configuring the voltage of the second gate G2 of the dual-gate transistor T0 (i.e., the first initialization voltage), the threshold voltage of the dual-gate transistor T0 is adjusted to be greater than 0V, thus putting the dual-gate transistor T0 in the off state.

[0104] Furthermore, during the initialization phase t1, since the gate of the first transistor T1 is connected to the second scan line S2, the first transistor T1 is also turned on. By sharing the second scan line S2, the number of scan lines can be saved, which is beneficial to reducing the number of gate drive units. Since the data line Data also transmits data voltage to the first gate G1 at this time, to prevent the potential of the second terminal S of the dual-gate transistor T0 from being pulled high, the aspect ratio of the fourth transistor T4 can be set to be smaller than that of the third transistor T3, making the switching speed of the third transistor T3 greater than that of the fourth transistor T4. The potential of the second terminal S of the dual-gate transistor T0 is controlled by the second initialization voltage Vini transmitted on the second initialization signal line, preventing the data voltage and the second initialization voltage Vini from simultaneously affecting the potential of the second terminal S of the dual-gate transistor T0, thus maintaining the stability of the potential of the second terminal S of the dual-gate transistor T0. Simultaneously, it can be controlled that the second transistor T2 and the fourth transistor T4 are turned on after a preset time since the third transistor T3 was turned on. This reduces the conduction time of the fourth transistor T4 during the initialization phase t1, further improving the stability of the potential of the second terminal S of the dual-gate transistor T0.

[0105] During the threshold detection phase t2, the second scan signal S2 controls the second initialization module 142 to turn off, and the first scan signal S1 controls the first initialization module 141 and the third initialization module 143 to turn on.

[0106] Specifically, since the third transistor T3 is turned off, the second initialization voltage on the second initialization signal line Vini no longer controls the potential of the second terminal S of the dual-gate transistor T0. Therefore, the voltage change of the second terminal S of the dual-gate transistor T0 is the sum of the second power supply ELVSS voltage and the threshold voltage of the light-emitting device OLED, and the potential of the second terminal S increases. Since the fourth transistor T4 remains on, the potential of the first gate G1 of the dual-gate transistor T0 is equal to that of the second terminal S, and the potential of the first gate G1 increases synchronously.

[0107] However, since the potential of the second gate G2 of the dual-gate transistor T0 is clamped by the first initialization voltage Vref, the voltage change of the second terminal S causes the voltage difference between the second gate G2 and the second terminal S to change. The voltage difference between the second gate G2 and the second terminal S of the dual-gate transistor T0 can adjust the threshold voltage of the dual-gate transistor T0. By configuring the second power supply voltage ELVSS and the first initialization voltage Vref, the threshold voltage of the dual-gate transistor T0 can be made less than 0V, thereby controlling the dual-gate transistor T0 to be turned on.

[0108] When the dual-gate transistor T0 is turned on, the first power supply ELVDD charges the second terminal S of the dual-gate transistor T0, and the potential of the second terminal S continues to rise. When the potential of the second terminal S of the dual-gate transistor T0 rises to the point that the voltage difference between the second gate G2 and the second terminal S makes the threshold voltage of the dual-gate transistor T0 equal to the voltage difference between the first gate G1 and the second terminal S, that is, when the threshold voltage of the dual-gate transistor T0 is 0V, the dual-gate transistor T0 turns off again. The voltages of the second gate G2 and the second terminal S are stored across the second capacitor C2, and the voltage difference between the second gate G2 and the second terminal S determines the threshold voltage of the dual-gate transistor T0. Thus, the detection of the threshold voltage of the dual-gate transistor T0 is completed.

[0109] During the data writing phase t3, the second scan signal S2 controls the data writing module 130 and the second initialization module 142 to be turned on, and the first scan signal S1 controls the first initialization module 141 and the third initialization module 143 to be turned off.

[0110] Specifically, the data voltage on the data line Data is transmitted to the first gate G1 of the dual-gate transistor T0 and stored in the first capacitor C1. To prevent the OLED from emitting light, a second initialization voltage Vini is written to the second terminal S of the dual-gate transistor T0. By configuring the voltage at the second terminal S of the dual-gate transistor T0, the impact of the voltage drop of the second power supply ELVSS on the OLED's emission can be reduced.

[0111] During the light emission stage t4, the second scan signal S2 controls the data writing module 130 and the second initialization module 142 to turn off, and the first scan signal S1 controls the first initialization module 141 and the third initialization module 143 to turn off.

[0112] Specifically, when the third transistor T3 is turned off, the potential of the second terminal S of the dual-gate transistor T0 changes. By controlling the voltage difference between the second gate G2 and the second terminal S, the threshold voltage of the dual-gate transistor T0 is adjusted, causing the dual-gate transistor T0 to conduct. A path is formed between the first power supply ELVDD and the second power supply ELVSS, and the OLED emits light under the drive of the dual-gate transistor T0. Since the second capacitor C2 stores a voltage that makes the threshold voltage of the dual-gate transistor T0 0V, the driving current generated by the dual-gate transistor T0 is independent of its threshold voltage, which helps to improve the uniformity of display brightness.

[0113] In this embodiment, an initialization phase and a threshold detection phase are executed within each frame or at least after two frames, and a data writing phase and a light emission phase are executed within each frame.

[0114] Specifically, because dual-gate transistors (T0) are more stable than single-gate transistors, their threshold voltage changes less under prolonged electrical stress. Therefore, after one threshold voltage detection, a longer interval can be allowed before the next threshold voltage detection. In other words, threshold detection is not required for every frame, which simplifies the control timing of the pixel circuit and allows for faster driving. Similarly, initialization is not required for every frame.

[0115] Prioritizing the initialization and threshold detection phases within the frame-to-frame gaps allows for more time for initialization and threshold voltage acquisition. This ensures complete initialization of the potentials of the first gate G1, second gate G2, and second electrode S of the dual-gate transistor T0, and guarantees full compensation of the threshold voltage even with large fluctuations, thus expanding the threshold voltage compensation range. Furthermore, when the initialization and threshold detection phases occur within the frame-to-frame gaps, the data line Data can be multiplexed as the first initialization signal line to transmit the first initialization voltage Vref. This reduces the number of initialization signal lines, improves PPI, simplifies the display panel design, and lowers costs.

[0116] Optionally, embodiments of the present invention also provide a display panel, which includes the pixel circuit provided in any embodiment of the present invention. Therefore, the display panel provided in embodiments of the present invention also has the beneficial effects described in any of the above embodiments. Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 12 The display panel can be Figure 12The mobile phone panel shown can also be the panel of any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0117] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The module consists of a driver module, a storage module, a data writing module, an initialization module, and a light-emitting module. The driving module includes a dual-gate transistor, the first terminal of which is connected to a first power supply, the second terminal of which is connected to a first terminal of the light-emitting module, and the second terminal of the light-emitting module is connected to a second power supply. The data writing module is connected between the first gate of the dual-gate transistor and the data line, and is used to transmit the data voltage output by the data line to the first gate. The storage module is connected to the first gate, the second gate, and the second electrode of the dual-gate transistor; The initialization module is connected to the first gate, second gate, second electrode, and initialization signal line of the dual-gate transistor, and is used to transmit the voltage provided by the initialization signal line to the first gate, second gate, and second electrode of the dual-gate transistor, and control the storage module to store the threshold voltage association information of the dual-gate transistor.

2. The pixel circuit according to claim 1, characterized in that, The initialization signal line includes a first initialization signal line and a second initialization signal line. The initialization module is used to transmit a first initialization voltage provided by the first initialization signal line to the second gate, and to transmit a second initialization voltage provided by the second initialization signal line to the first gate and the second gate of the dual-gate transistor.

3. The pixel circuit according to claim 2, characterized in that, The data line is multiplexed as the first initialization signal line.

4. The pixel circuit according to claim 1, characterized in that, The initialization module includes a first initialization module, a second initialization module, and a third initialization module; The first initialization module is connected between the first initialization signal line and the second gate, and the control terminal of the first initialization module is connected to the first scan line; the second initialization module is connected between the second initialization signal line and the second electrode of the dual-gate transistor, and the control terminal of the second initialization module is connected to the second scan line; the third initialization module is connected between the first gate and the second electrode of the dual-gate transistor, and the control terminal of the third initialization module is connected to the first scan line.

5. The pixel circuit according to claim 4, characterized in that, The first gate is a top gate, and the second gate is a bottom gate; the data writing module includes a first transistor, the first initialization module includes a second transistor, the second initialization module includes a third transistor, and the third initialization module includes a fourth transistor; the storage module includes a first capacitor and a second capacitor; The first terminal of the first transistor is connected to the data line, the second terminal of the first transistor is connected to the first gate, and the gate of the first transistor is connected to the second scan line; The first terminal of the second transistor is connected to the first initialization signal line, the second terminal of the second transistor is connected to the second gate, and the gate of the second transistor is connected to the first scan line; The first terminal of the third transistor is connected to the second initialization signal line, the second terminal of the third transistor is connected to the second terminal of the dual-gate transistor, and the gate of the third transistor is connected to the second scan line; The first terminal of the fourth transistor is connected to the first gate, the second terminal of the fourth transistor is connected to the second terminal of the dual-gate transistor, and the gate of the fourth transistor is connected to the first scan line; The first capacitor is connected between the first gate and the second terminal of the dual-gate transistor, and the second capacitor is connected between the second gate and the second terminal of the dual-gate transistor.

6. The pixel circuit according to claim 5, characterized in that, The aspect ratio of the fourth transistor is smaller than that of the third transistor.

7. The pixel circuit according to claim 5, characterized in that, Within one frame, the signal transmitted by the second scan line includes a first pulse and a second pulse, wherein the interval of the first pulse overlaps with the rising edge of the pulse on the signal transmitted by the first scan line, and the second pulse follows the pulse on the signal transmitted by the first scan line.

8. The pixel circuit according to claim 5, characterized in that, The first scan line and the second scan line, the first initialization signal line and the second initialization signal line are configured to transmit drive signals to satisfy: During the initialization phase, the third transistor is turned on, and then the second transistor and the fourth transistor are turned on; During the threshold detection phase, the second transistor and the fourth transistor are turned on, and the third transistor is turned off. During the data writing phase, the first transistor and the third transistor are turned on, while the second transistor and the fourth transistor are turned off; During the light-emitting phase, the first transistor, the second transistor, the third transistor, and the fourth transistor are all turned off.

9. A driving method for a pixel circuit, characterized in that, The pixel circuit includes: a driving module, a storage module, a data writing module, an initialization module, and a light-emitting module; the driving module includes a dual-gate transistor, the first terminal of which is connected to a first power supply, the second terminal of which is connected to a first terminal of the light-emitting module, and the second terminal of which is connected to a second power supply; the data writing module is connected between the first gate of the dual-gate transistor and a data line; the storage module is connected to the first gate, second gate, and second terminal of the dual-gate transistor; the initialization module is connected to the first gate, second gate, second terminal, and initialization signal line of the dual-gate transistor. The driving method includes: During the initialization phase, the control module transmits the corresponding initialization voltage to the first gate, second gate, and second electrode of the dual-gate transistor; During the threshold detection phase, the initialization module is controlled to cause the storage module to store the associated information of the threshold voltage of the dual-gate transistor; During the data writing phase, the data writing module is controlled to transmit the data voltage provided by the data line to the first gate.

10. The method according to claim 9, characterized in that, The storage module includes a first capacitor and a second capacitor. The initialization module includes a first initialization module, a second initialization module, and a third initialization module. The first initialization module is connected between a first initialization signal line and a second gate. The control terminal of the first initialization module is connected to a first scan line. The second initialization module is connected between a second initialization signal line and a second gate. The control terminal of the second initialization module is connected to a second scan line. The third initialization module is connected between the first gate and the second gate. The control terminal of the third initialization module is connected to the first scan line. During the initialization phase, the second scan signal transmitted by the second scan line controls the second initialization module to turn on, and after a preset time, the first scan signal transmitted by the first scan line controls the first initialization module and the third initialization module to turn on. During the threshold detection phase, the second scanning signal controls the second initialization module to turn off, and the first scanning signal controls the first initialization module and the third initialization module to turn on. During the data writing phase, the second scan signal controls the data writing module and the second initialization module to be turned on, and the first scan signal controls the first initialization module and the third initialization module to be turned off. During the light emission stage, the second scanning signal controls the data writing module and the second initialization module to shut down, and the first scanning signal controls the first initialization module and the third initialization module to shut down.

11. The method according to claim 9 or 10, characterized in that, The initialization phase and the threshold detection phase are executed within each frame or at least after two frames, and the data writing phase and the emission phase are executed within each frame.

12. The method according to claim 11, characterized in that, The initialization phase and the threshold detection phase occur during the blank periods between frames.

13. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-8.

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