Testing method and testing system

Abstract

Embodiments of the present application relate to the field of semiconductor circuit testing, and particularly to a testing method and a testing system, including: directly writing first initial data and first check data into a storage module; directly writing second initial data and second check data into the same address of the storage module, where the second initial data stored in the storage module overwrites the first initial data, and the second check data overwrites the first check data; directly writing the first initial data into the same address of the storage module, where the first initial data stored in the storage module overwrites the second initial data; reading out first read data and second read data of the memory, and determining whether the function of the ECC module is abnormal based on the first read data or the second read data, so as to provide a simple and reliable testing method for the ECC function of the memory, and by directly storing data in the storage module, the encoding time of the ECC module is saved and the testing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit testing, and particularly to a testing method and a testing system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density, fast transmission speed, etc. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration degree of storage units is getting higher and higher; at the same time, various different applications also have higher and higher requirements for the performance, power consumption, reliability, etc. of DRAM.

[0003] In order to ensure that data storage does not make mistakes, an error correction code (ECC) function is introduced to perform data verification on the stored data, so as to improve the accuracy of DRAM data storage, that is, ensuring the correct operation of the ECC function can, to a certain extent, ensure that the stored data does not make mistakes.

[0004] However, the applicant finds that the current test environment for the ECC function in DRAM is relatively limited, and there is an urgent need to design a simple and reliable test method to test whether the ECC function in DRAM is normal. Summary of the Invention

[0005] Embodiments of this application provide a testing method and a testing system, which can also test whether the ECC function in a memory is normal after the memory is put into use.

[0006] Embodiments of this application provide a testing method, which is applied to a memory. The memory includes a storage module and an ECC module, and includes: directly writing a first initial data and a first check data into the storage module, where the first check data is encoded and obtained according to the first initial data based on the encoding method of the ECC module; directly writing a second initial data and a second check data into the same address of the storage module, the second initial data stored in the storage module overwrites the first initial data, the second check data overwrites the first check data, there are data differences between the first initial data and the second initial data, and there are data differences between the first check data and the second check data; directly writing the first initial data into the same address of the storage module, and the first initial data stored in the storage module overwrites the second initial data; reading out a first read data and a second read data of the memory, and based on the first read data or the second read data, judging whether the function of the ECC module is abnormal, where the first read data is the first initial data read out from the storage module and verified and corrected by the ECC module, and the second read data is the second check data read out from the storage module and verified and corrected by the ECC module.

[0007] An embodiment of the present application provides a test system, which is applied to the above test method and includes: a first data providing module configured to provide first initial data and first check data to a memory; a second data providing module configured to provide second initial data and second check data to the memory, where the first initial data and the second initial data have data differences, and the first check data and the second check data have data differences; a control module configured to control the opening or closing of the ECC module of the memory according to a control signal and control whether the ECC module enters a test mode; a data analysis module configured to obtain first read data and second read data output by the memory and determine whether the function of the ECC module is abnormal based on the first read data or the second read data, where the first read data is the first initial data read from the memory and verified and corrected, and the second read data is the second check data read from the memory and verified and corrected.

[0008] After calibrating the correct data by directly storing the first initial data and the first check data in the storage module, first directly store the second initial data and the second check data in the storage module, then store the first initial data in the storage module, that is, inject errors into the check data, and then determine whether the ECC function of the memory is normal through the first read data and the second read data read from the memory. That is, after the memory is put into use, a relatively simple method can still be used to check the ECC function. The test environment is real, and the obtained test data is more reliable. In addition, by directly storing data in the storage module, the encoding time of the ECC module is saved, and the test efficiency is improved. Description of the Drawings

[0009] Figure 1 It is a schematic structural diagram of a memory provided by an embodiment of the present application;

[0010] Figure 2 It is a schematic flowchart of a test method provided by an embodiment of the present application;

[0011] Figure 3 It is a schematic diagram of the specific data flow of a test method provided by an embodiment of the present application;

[0012] Figure 4 It is a schematic structural diagram of a test system provided by another embodiment of the present application. Detailed Embodiments

[0013] In order to ensure that data storage does not make mistakes, an error detection and correction function (Error Correction Code, ECC) is introduced to perform data verification on the stored data to improve the accuracy of DRAM data storage. That is, ensuring the correct operation of the ECC function can, to a certain extent, ensure that the stored data does not make mistakes.

[0014] The applicant has found that the current test environment for the ECC function in DRAM is relatively limited, and there is an urgent need to design a simple and reliable test method to test whether the ECC function in DRAM is normal.

[0015] An embodiment of the present application provides a test method, which is applied to a memory. The memory includes a storage module and an ECC module, and includes: directly writing first initial data and first check data into the storage module, where the first check data is obtained by encoding the first initial data according to the encoding method of the ECC module; directly writing second initial data and second check data into the same address of the storage module, the second initial data stored in the storage module overwrites the first initial data, the second check data overwrites the first check data, there are data differences between the first initial data and the second initial data, and there are data differences between the first check data and the second check data; directly writing the first initial data into the same address of the storage module, and the first initial data stored in the storage module overwrites the second initial data; reading out the first read data and the second read data of the memory, and judging whether the function of the ECC module is abnormal based on the first read data or the second read data, where the first read data is the first initial data read from the storage module and verified and corrected by the ECC module, and the second read data is the second check data read from the storage module and verified and corrected by the ECC module.

[0016] Those of ordinary skill in the art can understand that in various embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0017] Figure 1 A schematic structural diagram of a memory provided for this embodiment Figure 2 A schematic flowchart of a test method provided for this embodiment Figure 3 A specific data flow diagram of a test method provided for this embodiment. The following further describes the test method provided for this embodiment in detail with reference to the drawings, specifically as follows:

[0018] It should be noted that the test for ECC in the present application is specifically used to test whether the ECC will use incorrect check data to repair real data, and whether it repairs incorrect check data according to real data. Among them, real data represents the data to be stored, and check data is the verification data compiled by the ECC module according to the data to be stored. In addition, the solution mentioned in this embodiment is also applicable to testing whether the ECC repairs real data according to check data.

[0019] In one example, refer toFigure 1 , a testing method, is applied to a memory. The memory includes: an interface module (not shown), a storage module 300, and an ECC module 200. Among them, the ECC module 200 is used to detect and correct errors in the data stored in the storage module 300. The storage module 300 is used to store real data and parity data. The interface module (not shown) is used to obtain the real data and parity data to be stored in the storage module 300, and is used to output the read data of the memory. Specifically, the interface module (not shown) includes a first test pad 114 and a second test pad 124. Among them, the first test pad 114 is used to transmit real data, and the second test pad 124 is used to transmit parity data; the real data between the first test pad 114 and the ECC module 200 is transmitted through a first data path 115, and the parity data between the second test pad 124 and the ECC module 200 is transmitted through a second data path 125.

[0020] For Figure 1 , the real data includes a first initial data Data1 and a second initial data Data2. The read data of the memory includes a first read data Read1 and a second read data Read2. The parity data includes a first parity data Parity1 and a second parity data Parity2.

[0021] That is, the first initial data Data1 and the second initial data Data2 are transmitted through the first data channel 115, and the first parity data Parity1 and the second parity data Parity2 are transmitted through the second data channel 125; the first initial data Data1 and the second initial data Data2 are written into the first data channel 115 through the first test pad 114, and the first parity data Parity1 and the second parity data Parity2 are written into the second data channel 125 through the second test pad 124.

[0022] In an example, the first test pad 114 uses the data pad of the memory, and the second test pad uses the mask pad of the memory.

[0023] During the normal data reading and writing process of the memory, mask operations may be involved, and the memory mask operation is based on whether the control end sends a mask and whether the relevant mask function is enabled. For the mask operation, it is not used during the ECC test of the memory. That is, during the ECC test, the mask pad of the memory is equivalent to having no effect. Therefore, using the mask pad to output the second read data Read2 does not require adding new pads to the memory and will not change the external structure of the memory.

[0024] Reference Figure 2 , the testing method specifically includes steps 101 to 105.

[0025] Step 101, write the first initial data Data1 and the first parity data Parity1 into the storage module 300.

[0026] Specifically, directly write the first initial data Data1 and the first parity data Parity1 into the storage module 300. The first parity data Parity1 is obtained by encoding the first initial data Data1 according to the encoding method of the ECC module 200.

[0027] Among them, the first initial data Data1 and the first parity data Parity1 are used to indicate the correct data that the ECC module 200 needs to verify subsequently.

[0028] It should be noted that in this embodiment, the first initial data Data1 is exemplified by a 128-bit binary number, which does not limit this embodiment; in specific applications, the data length of the first initial data Data1 can be adjusted according to the data length required to be stored in the memory. Correspondingly, the first parity data Parity1 compiled and generated by the ECC module 200 according to the first initial data Data1 is an 8-bit binary number.

[0029] In an example, the first initial data Data1 is stored in the data storage area of the storage module 300, and the first parity data Parity1 is stored in the parity storage area of the storage module 300; further, the first initial data Data1 stored in the data storage area is divided into 16 groups in groups of 8 bits for storage to ensure that the storage space of each storage unit in the data storage area is the same as that of the storage unit in the parity storage area. It should be noted that the real data stored in the data storage area can be divided according to the division method of the storage unit storage space of the memory, and this embodiment does not limit the data division during data storage.

[0030] Combine Figure 1 and Figure 3 , input the first test command to make the ECC module 200 enter the test mode, input the second test command to turn off the ECC module 200. The first test pad 114 obtains the first initial data Data1 and transmits the first initial data Data1 to the storage module 300. The second test pad 124 obtains the first parity data Parity1 and transmits the first parity data Parity1 to the storage module 300.

[0031] In an example, turning off the ECC module 200 includes: turning off the encoding function of the ECC module 200; turning on the ECC module 200 includes: turning on the encoding function of the ECC module 200. That is, by turning off the encoding function of the ECC module 200, the ECC module 200 is prevented from encoding and generating parity data according to the real data.

[0032] In another example, turning off the ECC module 200 includes: turning off the data transmission channel for accessing and verifying data between the ECC module 200 and the storage module 300; turning on the ECC module 200 includes: turning on the data transmission channel for accessing and verifying data between the ECC module 200 and the storage module 300. That is, by turning off the data transmission channel for accessing and verifying data between the ECC module 200 and the storage module 300, it is ensured that the verification data generated by encoding the real data by the ECC module 200 cannot be stored in the storage module 300.

[0033] In addition, in one example, the second data channel 125 is turned on based on the first test command. For a memory in a normal operating state, its ECC function will not output verification data after verification and repair. In some embodiments, the second data path 125 is turned on based on the first test command, that is, it is further ensured that the memory will only input or output verification data when the ECC function is tested.

[0034] Step 102, write the second initial data Data2 and the second verification data Parity2 into the storage module 300.

[0035] Specifically, directly write the second initial data Data2 and the second verification data Parity2 into the same address of the storage module 300. The second initial data Data2 stored in the storage module 300 overwrites the first initial data Data1, and the second verification data Parity2 overwrites the first verification data Parity1. Among them, the first initial data Data1 and the second initial data Data2 have data differences, and the first verification data Parity1 and the second verification data Parity2 have data differences.

[0036] Specifically, since the first initial data Data1 and the second initial data Data2 have data differences, the first verification data Parity1 obtained by encoding according to the first initial data Data1 and the second verification data Parity2 obtained by encoding according to the second initial data Data2 also have data differences.

[0037] It should be noted that in this embodiment, the second initial data Data2 is exemplified by a 128-bit binary number, which does not limit this embodiment.

[0038] For the ECC function of a common memory, if only one bit of the check data in the memory changes in the storage module 300, the check data can be repaired according to the real data. If the number of bits of the check data that change is greater than 1, the ECC module 200 cannot repair the check data. Therefore, in this embodiment, there is exactly one bit difference between the first initial data Data1 and the second initial data Data2, that is, the first check data Parity1 obtained by encoding according to the first initial data Data1 and the second check data Parity2 obtained by encoding according to the second initial data Data2 also have exactly one bit difference, so as to ensure that the second check data Parity2 after error injection can be repaired by the ECC module.

[0039] Combined with Figure 1 and Figure 3 , the first test pad 114 obtains the second initial data Data2 and transmits the second initial data Data2 to the storage module 300. The second test pad 124 obtains the second check data Parity2 and transmits the second check data Parity2 to the storage module 300.

[0040] Step 103, write the first initial data Data1 into the storage module 300.

[0041] Specifically, directly write the first initial data Data1 into the same address of the storage module 300, and the first initial data Data1 stored in the storage module 300 overwrites the second initial data Data2.

[0042] Combined with Figure 1 and Figure 3 , the first test pad 114 obtains the first initial data Data1 and transmits the first initial data Data1 to the storage module 300. After the first initial data Data1 is stored in the storage module 300, input the second test command to turn on the ECC module 200.

[0043] Since the memory stores data in the form of electrical levels, and the data stored by electrical levels may be different between the written data and the read data due to the change of electrical levels, it is necessary to use ECC to detect and correct errors in the written data and the read data. In this embodiment, by controlling the on and off of the ECC module 200, directly store the real data and the check data in the storage module 300, saving the encoding time of the ECC module, improving the test efficiency, and realizing injecting errors into the check data, so as to simulate the occurrence of errors in the check data stored in the storage module 300. It should be noted that in other embodiments, step 103 can also be to input the first check data Parity1, so as to realize injecting errors into the real data, so as to simulate the occurrence of errors in the real data stored in the storage module 300.

[0044] Step 104, read out the first initial data Data1 and the second parity data Parity2 in the storage module 300.

[0045] Specifically, read out the first initial data Data1 and the second parity data Parity2 in the storage module 300. The ECC module 200 generates detection data corresponding to the first initial data Data1 based on the first initial data Data1, and checks and corrects the second parity data Parity2 based on the detection data.

[0046] Combine Figure 1 and Figure 3 , the storage module 300 reads the first initial data Data1 and the second parity data Parity2 to the ECC module 200. The ECC module 200 generates detection data corresponding to the first initial data Data1 based on the first initial data Data1. The ECC module 200 checks and corrects the second parity data Parity2 according to the detection data.

[0047] Step 105, obtain the first read data Read1 and the second read data Read2 of the memory, and determine whether the function of the ECC module is abnormal based on the first read data Read1 and the second read data Read2.

[0048] Wherein, the first read data Read1 is the first initial data Data1 read from the storage module 300 and checked and corrected by the ECC module 200, and the second read data Read2 is the second parity data Parity2 read from the storage module 300 and checked and corrected by the ECC module 200.

[0049] In one example, if the read first read data Read1 is the same as the first initial data Data1 to be written, it indicates that the miswritten parity data is repaired by the ECC module 200, the initial data remains unchanged, and the function of the ECC module 200 is normal; if the read first read data Read1 is different from the first initial data Data1 to be written, it indicates that the initial data is wrongly repaired by the ECC module 200, and the function of the ECC module 200 is abnormal.

[0050] In another example, if the read second read data Read2 is the same as the first parity data Parity1 to be written, it indicates that the miswritten parity data is repaired by the ECC module 200, and the function of the ECC module 200 is normal; if the read second read data Read2 is different from the first parity data Parity1 to be written, it indicates that the miswritten parity data is not repaired, the initial data is wrongly repaired by the ECC module 200, and the function of the ECC module 200 is abnormal.

[0051] It should be noted that in other embodiments, the above test methods for real data and check data can be combined to double guarantee and further ensure the accuracy of test results.

[0052] Since the memory stores data in the form of level storage, and the data stored by level may be different between the written data and the read data due to the change of the level, it is necessary to use ECC to detect and correct errors in the written data and the read data. In this embodiment, after directly storing the first initial data and the first check data in the storage module to calibrate the correct data, the second initial data and the second check data are first directly stored in the storage module, and then the first initial data is stored in the storage module, that is, an error is injected into the check data. Then, it is judged whether the ECC function of the memory is normal by the first read data and the second read data read out by the memory. That is, after the memory is put into use, the ECC function can still be verified in a relatively simple way. The test environment is real, and the obtained test data is more reliable. In addition, by directly storing data in the storage module, the encoding time of the ECC module is saved, and the test efficiency is improved.

[0053] The above various step divisions are only for clear description. When implemented, they can be combined into one step or some steps can be split into multiple steps; adding insignificant modifications or introducing insignificant designs to the process, but not changing the core design of the process are all within the protection scope of this patent.

[0054] Another embodiment of the present application provides a test system applied to the above test method, including: a first data providing module configured to provide the first initial data and the first check data to the memory; a second data providing module configured to provide the second initial data and the second check data to the memory, where the first initial data and the second initial data have data differences, and the first check data and the second check data have data differences; a control module configured to control the opening or closing of the ECC module of the memory according to a control signal and control whether the ECC module enters the test mode; a data analysis module configured to obtain the first read data and the second read data output by the memory and judge whether the function of the ECC module is abnormal based on the first read data or the second read data. The first read data is the first initial data read out from the memory and verified and corrected, and the second read data is the second initial data read out from the memory and verified and corrected.

[0055] Figure 4 The following is a schematic structural diagram of a test system provided in this embodiment. The test system provided in this embodiment will be further described in detail with reference to the accompanying drawings as follows:

[0056] Refer to Figure 4, a test system 400 for testing the ECC module of a memory, including:

[0057] A first data providing module 401, configured to provide a first initial data Data1 and a first parity data Parity1 to the memory.

[0058] It should be noted that, in this embodiment, the first initial data Data1 is exemplified by a 128-bit binary number, which does not constitute a limitation to this embodiment; in specific applications, the data length of the first initial data Data1 can be adjusted according to the data length required to be stored in the memory. Correspondingly, the first parity data Parity1 compiled and generated by the ECC module of the memory according to the first initial data Data1 is an 8-bit binary number.

[0059] A second data providing module 402, configured to provide a second initial data Data2 and a second parity data Parity2 to the memory, wherein the first initial data Data1 and the second initial data Data2 have data differences, and the first parity data Parity1 and the second parity data Parity2 have data differences.

[0060] Since the memory stores data in the form of electrical levels, and the data stored by electrical levels may be different between the written data and the read data due to the change of electrical levels, it is necessary to use ECC to detect and correct errors in the written data and the read data. In this embodiment, by controlling the opening and closing of the ECC module, real data and parity data are directly stored in the storage module, saving the encoding time of the ECC module, improving the test efficiency, and realizing injecting errors into the parity data, so as to simulate the occurrence of errors in the parity data stored in the storage module.

[0061] For the ECC function of common memories, if only one bit of the parity data in the storage module of the memory changes, the parity data can be repaired according to the real data. If the number of changed bits of the parity data is greater than 1, the ECC module cannot repair the parity data. Therefore, in this embodiment, there is and only one bit of data difference between the first initial data Data1 and the second initial data Data2, that is, there is also and only one bit of data difference between the first parity data Parity1 encoded according to the first initial data Data1 and the second parity data Parity2 encoded according to the second initial data Data2, so as to ensure that the second parity data Parity2 after error injection can be repaired by the ECC module.

[0062] In one example, the first data providing module 401 and the second data providing module 402 write the first initial data Data1 and the second initial data Data2 into the memory through the first test pad, and write the first parity data Parity1 and the second parity data Parity2 into the memory through the second test pad.

[0063] Furthermore, the first test pad 114 uses the data pad of the memory, and the second test pad uses the mask pad of the memory. Mask operations may be involved in the normal data reading and writing process of the memory, and the memory mask operation is based on whether the control terminal sends a mask and whether the relevant mask function is enabled. For mask operations, they are not used during the ECC test of the memory. That is, during the ECC test, the mask pad of the memory has no effect. Therefore, using the mask pad to output the second read data Read2 does not require adding new pads to the memory and does not change the external structure of the memory.

[0064] The control module 403 is configured to control the enabling or disabling of the ECC module of the memory according to a control signal, and control whether the ECC module enters the test mode.

[0065] Specifically, the ECC module of the memory is controlled to enter the test mode through the first test signal, and the enabling or disabling of the ECC module of the memory is controlled through the second test signal.

[0066] In one example, disabling the ECC module includes: disabling the encoding function of the ECC module; enabling the ECC module includes: enabling the encoding function of the ECC module. That is, by disabling the encoding function of the ECC module 200, the ECC module 200 is prevented from encoding real data to generate parity data.

[0067] In another example, disabling the ECC module includes: closing the data transmission channel for accessing parity data between the ECC module and the storage module; enabling the ECC module includes: opening the data transmission channel for accessing parity data between the ECC module and the storage module. That is, by closing the data transmission channel for accessing parity data between the ECC module 200 and the storage module 300, it is ensured that the parity data generated by the ECC module 200 according to real data cannot be stored in the storage module 300.

[0068] The data analysis module 404 is configured to obtain a first read data Read1 and a second read data Read2 output by the memory, and determine whether the function of the ECC module of the memory is abnormal based on the first read data Read1 and the second read data Read2. The first read data Read1 is the first initial data Data1 read, verified, and corrected by the memory, and the second read data Read2 is the second parity data Parity2 read, verified, and corrected by the memory.

[0069] In one example, the data analysis module 404 includes: an acquisition unit 414 configured to acquire a first read data Read1 of the memory data; a determination unit 424 connected to the first data providing module 401 and the acquisition unit 414, and determine whether the function of the memory ECC module is abnormal based on the first read data Read1 and the first initial data Data1.

[0070] For the determination unit 424, if the read first read data Read1 is the same as the to-be-written first initial data Data1, it indicates that the mis-injected parity data is repaired by the ECC module, the initial data remains unchanged, and the ECC module functions normally; if the read first read data Read1 is different from the to-be-written first initial data Data1, it indicates that the initial data is wrongly repaired by the ECC module, and the ECC module functions abnormally.

[0071] In another example, the data analysis module 404 includes: an acquisition unit 414 configured to acquire a second read data Read2 of the memory data; a determination unit 424 connected to the first data providing module 401 and the acquisition unit 414, and determine whether the function of the memory ECC module is abnormal based on the second read data Read2 and the first parity data Parity1.

[0072] For the determination unit 424, if the read second read data Read2 is the same as the to-be-written first parity data Parity1, it indicates that the mis-injected parity data is repaired by the ECC module 200, and the ECC module 200 functions normally; if the read second read data Read2 is different from the to-be-written first parity data Parity1, it indicates that the mis-injected parity data is not repaired, the initial data is wrongly repaired by the ECC module 200, and the ECC module 200 functions abnormally.

[0073] It should be noted that in other embodiments, the above test methods for real data and parity data can be combined to double guarantee and further ensure the accuracy of the test results.

[0074] Since the memory stores data in the form of electrical levels, and the data stored by electrical levels may be different between the written data and the read data due to the change of electrical levels, it is necessary to use ECC to detect and correct errors in the written data and the read data. In this embodiment, after directly storing the first initial data and the first check data in the storage module to calibrate the correct data, the second initial data and the second check data are first directly stored in the storage module, and then the first initial data is stored in the storage module, that is, errors are injected into the check data. Then, it is determined whether the ECC function of the memory is normal by the first read data and the second read data read out by the memory. That is, after the memory is put into use, the ECC function can still be verified in a relatively simple manner. The test environment is real, and the obtained test data is more reliable. In addition, by directly storing data in the storage module, the encoding time of the ECC module is saved, and the test efficiency is improved.

[0075] It is worth mentioning that each unit involved in this embodiment is a logical unit. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0076] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application. In practical applications, various changes can be made to them in form and details without departing from the spirit and scope of this application.

Claims

1. A testing method is applied to a memory, and the memory includes a storage module and an ECC module. Characterized in that, It includes: Directly write a first initial data and a first check data into the storage module, and the first check data is encoded and obtained according to the first initial data based on the encoding method of the ECC module; Directly write a second initial data and a second check data into the same address of the storage module. The second initial data stored in the storage module overwrites the first initial data, and the second check data overwrites the first check data. There are data differences between the first initial data and the second initial data, and there are data differences between the first check data and the second check data; Directly write the first initial data into the same address of the storage module, and the first initial data stored in the storage module overwrites the second initial data; Read out a first read data and a second read data of the memory, and based on the first read data or the second read data, judge whether the function of the ECC module is abnormal. The first read data is the first initial data read out from the storage module and verified and corrected by the ECC module, and the second read data is the second check data read out from the storage module and verified and corrected by the ECC module.

2. The testing method according to claim 1, Characterized in that, It includes: Before directly writing the first initial data and the first check data into the storage module, it further includes: inputting a first test command to make the ECC module enter the test mode, and inputting a second test command to turn off the ECC module; After directly writing the first initial data into the same address of the storage module and before reading out the first read data and the second read data of the memory, it further includes: inputting the second test command to turn on the ECC module.

3. The testing method according to claim 2, Characterized in that, The first initial data and the second initial data are transmitted through a first data channel, and the first check data and the second check data are transmitted through a second data channel, and the second data channel is opened based on the first test command.

4. The testing method according to claim 3, Characterized in that, Write the first initial data and the second initial data into the first data channel through a first test pad, and write the first check data and the second check data into the second data channel through a second test pad.

5. The testing method according to claim 4, Characterized in that, The first test pad uses the data pad of the memory, and the second test pad uses the mask pad of the memory.

6. The testing method according to claim 2, Characterized in that, It includes: Turning off the ECC module includes: turning off the encoding function of the ECC module; Turning on the ECC module includes: turning on the encoding function of the ECC module.

7. The testing method according to claim 2, Characterized in that, It includes: Closing the ECC module includes: closing the data channel for storing parity data between the ECC module and the storage module; Enabling the ECC module includes: enabling the data channel for storing parity data between the ECC module and the storage module.

8. The test method according to claim 1, wherein, there is exactly one bit difference between the first initial data and the second initial data, and there is exactly one bit difference between the first parity data and the second parity data.

9. The test method according to claim 1, wherein, judging whether the function of the ECC module is abnormal based on the first read data or the second read data includes: if the second read data is the same as the first parity data to be written, the function of the ECC module is normal; if the second read data is different from the first parity data to be written, the function of the ECC module is abnormal.

10. The test method according to claim 1, wherein, judging whether the function of the ECC module is abnormal based on the first read data or the second read data includes: if the first read data is the same as the first initial data to be written, the function of the ECC module is normal; if the first read data is different from the first initial data to be written, the function of the ECC module is abnormal.

11. A test system applied to the test method according to any one of claims 1 to 10, wherein, it includes: A first data providing module configured to provide first initial data and first parity data to the memory; A second data providing module configured to provide second initial data and second parity data to the memory, there is a data difference between the first initial data and the second initial data, and there is a data difference between the first parity data and the second parity data; A control module configured to control the enabling or disabling of the ECC module of the memory according to a control signal, and control whether the ECC module enters a test mode; A data analysis module configured to obtain first read data and second read data output by the memory, and judge whether the function of the ECC module is abnormal based on the first read data or the second read data, the first read data is the first initial data read from the memory and verified and corrected, and the second read data is the second initial data read from the memory and verified and corrected.

12. The test system according to claim 11, wherein, there is exactly one bit difference between the first initial data and the second initial data, and there is exactly one bit difference between the first parity data and the second parity data.

13. The test system according to claim 11, wherein, the data analysis module includes: An acquisition unit configured to acquire first read data output by the memory; A judgment unit connected to the first data providing module and the acquisition unit, and judge whether the function of the ECC module is abnormal based on the first read data and the first initial data.

14. The test system according to claim 11, wherein: it includes: an acquisition unit configured to acquire second read data output by the memory; a judgment unit connected to the first data providing module and the acquisition unit, and configured to judge whether the function of the ECC module is abnormal based on the second read data and the first check data.

15. The test system according to claim 11, wherein: the first data providing module writes the first initial data and the first check data into the memory through a first test pad; the second data providing module writes the second initial data and the second check data into the memory through a second test pad.

16. The test system according to claim 15, wherein: the first test pad uses a data pad of the memory, and the second test pad uses a mask pad of the memory.

Images