Etching method of semiconductor structure

Abstract

The application discloses an etching method of a semiconductor structure, which comprises the following steps: providing a material layer to be etched, and forming a plurality of discrete core layers on the material layer to be etched; forming a mask layer on the material layer to be etched exposed between the core layers and on the top and sidewall of the core layers; forming a protection layer on the mask layer; performing anisotropic etching on the protection layer and part of the mask layer until the protection layer is completely removed and the top of the core layer and part of the material layer to be etched between the adjacent core layer interval regions are exposed; removing the core layer; and etching the material layer to be etched by taking the remaining mask layer as a mask to form a target pattern in the material layer to be etched. The application can improve the CD odd-even loading problem and the depth loading problem of the target pattern.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor device manufacturing, and more particularly to an etching method of a semiconductor structure. BACKGROUND

[0002] With the continuous development of ultra-large integrated circuits, the critical dimension (CD) of semiconductor devices is continuously reduced, and the manufacturing process also faces many restrictions and challenges. In the case of smaller and smaller critical dimensions, how to improve the accuracy and stability of small size patterns has become a research hotspot in the industry.

[0003] Self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) methods are favored patterning methods in recent years. The density of the pattern formed on the substrate by the self-aligned double patterning method is twice the density of the pattern formed on the substrate by the photolithography process, i.e., 1 / 2 minimum pitch can be obtained. The density of the pattern formed on the substrate by the self-aligned quadruple patterning method is four times the density of the pattern formed on the substrate by the photolithography process without changing the current photolithography technology (i.e., the photolithography window size remains unchanged), i.e., 1 / 4 minimum pitch can be obtained. This can greatly improve the density of semiconductor integrated circuits, reduce the feature size of the pattern, and thus be beneficial to the improvement of device performance.

[0004] However, the introduction of self-aligned double and quadruple patterning processes results in different etch species collection angles during the manufacture of the mask, leading to different etch rates and micro-loading effects (also known as depth loading), which cause the problem of pitch walking on the etched substrate surface, or the CD of adjacent openings of the mask pattern has a difference, resulting in CD odd-even loading, which leads to poor quality of the target pattern formed after etching. SUMMARY

[0005] The purpose of the present application is to provide an etching method of a semiconductor structure to improve the CD odd-even loading problem and the depth loading problem of the target pattern.

[0006] To achieve the above purpose, the present application provides an etching method of a semiconductor structure, comprising:

[0007] providing a layer of material to be etched, the layer of material to be etched having a plurality of discrete core layers formed thereon;

[0008] forming a mask layer on the layer of material to be etched exposed between the core layers and on top of and sidewalls of the core layers;

[0009] forming a protective layer on the mask layer;

[0010] anisotropically etching the protective layer and part of the mask layer until the protective layer is completely removed and the top of the core layers and part of the layer of material to be etched between adjacent core layers are exposed;

[0011] removing the core layers;

[0012] etching the layer of material to be etched to form a target pattern in the layer of material to be etched using the remaining mask layer as a mask.

[0013] Optionally, the mask layer and the protective layer on the sidewalls of the core layers form side walls, and a lateral spacing between outer walls of adjacent side walls is less than a width dimension of the core layers.

[0014] Optionally, the forming of the protective layer on the mask layer comprises:

[0015] depositing a protective layer of a set thickness on the mask layer by a first process gas, the first process gas being one or more of CH3F, CH2F2, HBr, CH4, SiCl4 and O2;

[0016] the protective layer is silicon oxide, a CF-based polymer or a Si-O-Br-based polymer.

[0017] Optionally, the set thickness is

[0018] Optionally, the first process gas comprises SiCl4 and O2.

[0019] The process parameters used for the depositing of the protective layer of the set thickness on the mask layer by the first process gas comprise:

[0020] the upper radio frequency power ranges from 100 W to 2000 W;

[0021] the lower radio frequency power ranges from 10 W to 1500 W;

[0022] the process chamber pressure ranges from 3 mT to 100 mT;

[0023] the process chamber temperature ranges from 10 °C to 90 °C;

[0024] The flow rate of SiCl4 ranges from 1sccm to 100sccm.

[0025] The flow rate of O2 ranges from 1sccm to 100sccm.

[0026] Optionally, the anisotropic etching of the protective layer and part of the mask layer comprises:

[0027] The upper radio frequency power and the lower radio frequency power are turned on, and the first etching gas is used to remove the protective layer and part of the mask layer above the core layer and part of the material layer to be etched.

[0028] The upper radio frequency power ranges from 100W to 3000W, and the lower radio frequency power ranges from 50W to 1000W.

[0029] Optionally, the first etching gas comprises CF4 and CHF3.

[0030] Optionally, the process parameters for the anisotropic etching of the protective layer and part of the mask layer further comprise:

[0031] The process chamber pressure ranges from 3mT to 100mT.

[0032] The process chamber temperature ranges from 10℃ to 90℃.

[0033] The flow rate of CF4 ranges from 10sccm to 200sccm.

[0034] The flow rate of CHF3 ranges from 10sccm to 200sccm.

[0035] Optionally, in the step of removing the core layer, only the upper radio frequency power is turned on.

[0036] The upper radio frequency power ranges from 100W to 6000W.

[0037] Optionally, the etching of the material layer to be etched with the remaining mask layer as a mask comprises:

[0038] The upper radio frequency power and the lower radio frequency power are turned on, and the second etching gas is used to etch the material layer to be etched with the remaining mask layer as a mask.

[0039] The upper radio frequency power ranges from 100W to 6000W, and the lower radio frequency power ranges from 10W to 2000W.

[0040] The present application has the following advantages:

[0041] The application firstly forms a mask layer covering the core layer, then forms a protective layer on the mask layer, adjusts the CD between the side walls through the protective layer, avoids the lateral etching of the outer wall of the mask layer through the effect of the protective layer when etching opens the top of the core layer, reduces the CD loss between the side walls, makes the CD between the side walls after the top of the core layer is etched smaller than the CD of the core layer, and when the target pattern is etched after the core layer is removed, the area with small CD between the side walls cannot timely remove the product of the plasma etching, so that the etching rate is lower than that of the area with large CD of the original core layer, so as to compensate for the loss of the material to be etched between the two side walls in the side wall opening step, effectively improve the depth loading problem, and further improve the pitch walking problem. Also, since the protective layer protects the side wall, the CD of the side wall can be effectively reduced during the target pattern etching process, so that the CD of the original core layer position is equal to the CD between the side walls after the final etching pattern is completed, thereby effectively solving the CD odd-even loading problem, and greatly improving the device performance.

[0042] The system of the application has other characteristics and advantages that will become apparent from and / or will be described and illustrated in connection with the accompanying drawings and the following detailed description, and it is in the drawings and the detailed description that particular preferred embodiments of the application are fully described. The drawings provided herein are meant to be explanatory only and do not limit the application in any way. BRIEF DESCRIPTION OF DRAWINGS

[0043] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout and in which:

[0044] Figure 1 A structure corresponding to each step in a semiconductor structure forming method of a related art 1 is shown.

[0045] Figure 2 A structure corresponding to each step in a self-aligned double patterning structure forming method of a related art 2 is shown.

[0046] Figures 3-7 A structure corresponding to each step in a semiconductor structure forming method of an embodiment of the application is shown.

[0047] Figure 8a An etching topography diagram obtained by using a conventional self-aligned double patterning method is shown.

[0048] Figure 8b An etching topography diagram obtained by using a semiconductor structure forming method of an embodiment of the application is shown. DETAILED DESCRIPTION

[0049] As shown in Figure 1 The related technical solution one provides a semiconductor structure forming method, which comprises the following steps: forming a patterned core layer 200 on a material layer 100 to be etched; forming a side wall film 300 on the top of the core layer 200 and the side wall surface, and on the material layer 100 to be etched; performing at least one top treatment on the side wall film 300, removing the side wall film 300 above the top of the core layer 200, and retaining the side wall film 300 on the side wall of the core layer 200 as a first part mask layer 320, and retaining the side wall film 300 on the material layer 100 to be etched as a second part mask layer 330; wherein the step of top treatment comprises the following steps: forming a sacrificial layer 400 on the side wall film 300, the sacrificial layer 400 covering the surface of the side wall film 300 on the side wall of the core layer 200 and the top; etching to remove the sacrificial layer 400 above the top of the core layer 200 and part or all thickness of the side wall film 300; removing the remaining sacrificial layer 400; after forming the first part mask layer 320 and the second part mask layer 330, removing the core layer 200; after removing the core layer 200, removing the second part mask layer 330; after removing the second part mask layer 330, etching the material layer 100 to be etched with the first part mask layer 320 as a mask.

[0050] Compared with the solution of not forming a sacrificial layer and etching the side wall film by a maskless etching process, the related technical solution one can avoid the problem that the top surface of the formed first part mask layer is an inclined surface, that is, the top surface of the formed first part mask layer is a flat surface; after removing the core layer, the second part mask layer is removed, and accordingly, the etching environment at the two top corners of the first part mask layer is the same when the second part mask layer is removed, so that after removing the second part mask layer, the morphology of the first part mask layer is symmetrical; thus, when etching the material layer to be etched with the first part mask layer as a mask, the problem of different etching gas collection angles can be avoided, and accordingly, the pitch walking problem of the formed target pattern is improved or eliminated, a target pattern with good morphology is obtained, and thus the performance and yield of the semiconductor device are improved.

[0051] However, the related technical solution one has the following disadvantages:

[0052] 1. The process is complex, and multiple sacrificial layer forming and side wall etching processes are required, so that the WPH (wafers per hour) is low, and the cost is increased.

[0053] 2. In the process of top side sacrificial layer and partial side wall etching, the bottom of the side wall film and the sacrificial layer are also etched at the same time, resulting in that part of the material to be etched has been etched before the core layer is removed. Finally, the etching depth of the material to be etched between the mask layers is greater than the depth of the material to be etched in the core layer, that is, depth loading; this scheme can only improve the depth loading problem of the material to be etched in the etching process (also known as micro-loading mentioned above). It has no effect on the CD odd loading formed in the process.

[0054] 3. The related technology can only be used for the process after the mask of the core layer is removed, and is not suitable for the core layer mask residue, increases the process processing steps, and increases the cost.

[0055] As shown in Figure 2 , the related technology two provides a method for forming a self-aligned double patterning structure, comprising: providing a substrate 100, forming a bottom core material layer 103 on the substrate, and forming a discrete first core layer 102 on the bottom core material layer. The mask residue is formed when the core layer 103 is formed. Form a side wall 101 on the surface of the core layer 103. After the etching of the side wall 101 is completed, the core layer 103 is removed, and the target pattern is formed by patterning the substrate with the side wall head 101 as a mask.

[0056] The related technology two has the following disadvantages:

[0057] Before the core layer 103 is removed, the top of the core layer needs to be completely exposed, otherwise the core layer will not be completely removed, which will affect the formation of the target pattern. Therefore, when etching the side wall, in order to ensure that the core layer top mask residue 102 is completely removed, the over-etching amount will be increased, which will cause the loss of the material to be etched 101. And due to the lateral etching effect of plasma, the CD loss of the side wall away from the core layer, causing the CD a between the core layers to be less than the space CD b1 between the adjacent side walls. (Note: The core layer CD a is equal to the CD b between the adjacent side walls at the beginning). Similarly, after the core layer is removed, the space CD b2 is greater than a1, and after the etched pattern is formed, the space CD b3 is greater than a2. The difference between b3 and a2 is the CD odd loading in the self-aligned multiple patterning process. (Note: The difference between b3 and a2 is the CD odd loading)

[0058] The present application provides an etching method of a semiconductor structure, which deposits a certain thickness of protective layer on the pattern surface before the current pattern etching, so as to adjust the CD between the side walls, thereby improving the CD odd loading and depth loading problems.

[0059] The application will be described in greater detail below with reference to the drawings. While the application is illustrated and described in preferred embodiments, it is understood that the application can be practiced with modification and alteration, and that the application should not be limited to the details as illustrated. Rather, the application is to cover all such modifications and alterations as they come within the true scope and spirit of the application. In order to assist clarity of understanding as to how the application can be practiced, the application will be described with reference to the attached figures, a brief description of which is as follows:

[0060] Figures 3-7 Fig. 1 shows a schematic diagram of a semiconductor structure corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the application.

[0061] Reference will now be made to Figure 1 A material to be etched 1 is provided, and a plurality of discrete core layers 2 are formed on the material to be etched 1.

[0062] The material to be etched 1 is used to form a target pattern after a subsequent patterning process. The material to be etched 1 can be silicon, silicon dioxide, silicon nitride, photoresist or amorphous carbon, etc. In this embodiment, the material to be etched 1 is polysilicon.

[0063] The core layer 2 provides a process basis for forming an etching mask for patterning the material to be etched 1. The material of the core layer 2 is a material that is easy to remove, and the material of the core layer 2 is different from the material of the material to be etched 1, so that damage to the material to be etched 1 caused by the process of removing the core layer 2 can be reduced. Therefore, the material of the core layer 2 can be amorphous carbon, polysilicon, ODL (organic dielectric layer) material, BARC (bottom anti-reflective coating) material, DARC (dielectric anti-reflective coating) material or Si-ARC (selective silicon anti-reflective coating) material. In this embodiment, the material of the core layer 2 is amorphous carbon.

[0064] Specifically, the step of forming the patterned core layer 2 includes: forming a core material layer on the material to be etched 1; forming a patterned photoresist layer (not shown) on the core material layer; etching the core material layer using the photoresist layer as a mask, and the remaining core material layer forms a plurality of discrete core layers 2; and removing the photoresist layer after the core layer 2 is formed.

[0065] In this embodiment, a self-aligned double patterning process is used to form an etching mask for patterning the material to be etched 1; therefore, the CD (width dimension) of the core layer 2 is determined according to the CD required by the subsequent target pattern.

[0066] In other embodiments, a self-aligned quadruple patterning process can also be used to form an etching mask for patterning the material to be etched 1; accordingly, the CD of the core layer is determined according to the CD required by the subsequent etching target pattern.

[0067] Continuing to refer to Figure 3A mask layer 3 is formed on the material layer 2 exposed between the core layers 2 and on the top and sidewalls of the core layers 2; Figure 3 The top of the core layer 2 is the residual mask layer 4 formed during the formation of the core layer 2.

[0068] Since the mask layer 3 located on the sidewall of the core layer 2 needs to be retained as an etching mask for patterning the material layer 1 to be etched, the material of the mask layer 3 needs to be different from the materials of the core layer 2 and the material layer 1 to be etched. This can reduce the impact of the subsequent process of removing the core layer 2 on the remaining mask layer 3, and enable the mask layer 3 located on the sidewall of the core layer 2 to serve as an etching mask for the subsequent etching of the material layer 1 to be etched.

[0069] The mask layer can be made of SiN or SiO2; in this embodiment, the mask layer is made of SiN.

[0070] The process for forming mask layer 3 can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form mask layer 3, which results in good step coverage of mask layer 3 and good coverage of the corner between the material layer 1 to be etched and the core layer 2.

[0071] The mask layer 3 located on the sidewall of the core layer 2 is used as an etching mask for subsequent etching of the material layer 1 to be etched in order to form the target pattern. Therefore, the thickness of the mask layer 3 on the sidewall of the core layer 2 is determined according to the CD of the target pattern to be formed.

[0072] Furthermore, after forming the mask layer 3, it is preferable that the CD between the vertical mask layers 3 on the sidewalls of two adjacent core layers 2 can be substantially consistent with the CD of the core layer 2, that is... Figure 3 In this case, a = b.

[0073] refer to Figure 4 A protective layer 5 is formed on the mask layer 3;

[0074] Preferably, the mask layer 3 and the protective layer 5 on the sidewall of the core layer 2 form a sidewall, and the lateral spacing between the outer walls of adjacent sidewalls is smaller than the width of the core layer 2.

[0075] Specifically, before removing the core layer 2, the top of the core layer 2 needs to be completely exposed, otherwise the core layer 2 will not be removed cleanly, affecting the formation of the target pattern. Therefore, when performing the etching of the top of the core layer 2, in order to ensure that the residual mask 4 on the top of the core layer is completely removed, the over-etching amount will be increased, which will cause the loss of the exposed to-be-etched material 1 in the spacing area between the core layers 2. At the same time, the bottom of the side wall, the sidewall, and the to-be-etched material are also etched when the top of the core layer is opened, which will cause depth loading and CD odd-even loading in subsequent removal of the core layer for target material etching.

[0076] Therefore, in order to avoid the problems of depth loading and CD odd-even loading in subsequent removal of the core layer for target material etching, the step deposits a certain thickness of a protection layer 104 on the mask layer 3. The mask layer 3 on the sidewall of the core layer 2 and the protection layer 5 together form a side wall. Through the action of the protection layer, the mask layer 3 at the sidewall of the core layer 3 can be effectively protected from lateral etching by the plasma. At the same time, in order to solve and improve the problems of CD odd-even loading and depth loading, the CD between the side walls of the adjacent two core layers 2 needs to be less than the CD (width) of the core layer 2 after the formation of the protection layer 5, so that the space CD between the adjacent two side walls is reduced (i.e., the lateral distance of the spacing area between the adjacent two side walls is changed from b to b1, b1

[0077] The thickness of the protection layer 5 is determined by the initial core layer CD and the CD of the adjacent side wall, and the thickness can be The embodiment preferably is A high upper radio frequency source power (SRF) and a low lower radio frequency source power (BRF) can be used to perform plasma deposition at a relatively low temperature.

[0078] The method for forming the protection layer 5 includes:

[0079] The first process gas is used to deposit a protection layer with a set thickness on the mask layer.

[0080] The first process gas is one or more of CH3F, CH2F2, HBr, CH4, SiCl4, and O2. The corresponding protection layer 5 can be silicon oxide, a CF-based polymer, or a Si-O-Br-based polymer.

[0081] In the embodiment, the first process gas is SiCl4 and O2, and the protection layer 5 formed is SiO2.

[0082] The process parameters used in the step of depositing the protection layer 5 include:

[0083] The frequency of the upper and lower radio frequency power sources is 13.56 MHz;

[0084] The upper radio frequency power range is 100-2000 W;

[0085] The lower radio frequency power range is 10-1500 W;

[0086] The process chamber pressure range is 3-100 mT;

[0087] The process chamber temperature range is 10-90℃;

[0088] The flow rate of SiCl4 is 1-100 sccm;

[0089] The flow rate of O2 is 1-100 sccm.

[0090] Reference Figure 5 Anisotropic etching is performed on the protective layer 5 and part of the mask layer 3 until the protective layer is completely removed and part of the material layer 1 to be etched between adjacent core layers 2 is exposed;

[0091] The etching method of this step includes:

[0092] The upper and lower radio frequency powers are turned on, and the first etching gas is used to remove the protective layer 5 and part of the mask layer 3 above the material layer 1 to be etched between adjacent core layers 2;

[0093] Preferably, the upper radio frequency power range is 100-3000 W, and the lower radio frequency power range is 50-1000 W. The first etching gas includes CF4 and CHF3.

[0094] The process parameters for etching the protective layer and the mask layer using the first etching gas also include:

[0095] The process chamber pressure range is 3-100 mT;

[0096] The process chamber temperature range is 10-90℃;

[0097] The flow rate of CF4 is 10-200 sccm;

[0098] The flow rate of CHF3 is 10-200 sccm.

[0099] The step is to open the top of the core layer 2. In the etching process, CF gas with high etching rate is usually used as the main etching gas, and high upper and lower radio frequency powers are used to improve the etching rate. The upper radio frequency power is used to generate plasma, and the high lower radio frequency power is used to provide energy and direction for the plasma, enhance anisotropic etching, and reduce lateral etching on the outside of the side wall to ensure that the core layer 2 top is completely exposed while the outside of the side wall is less lost.

[0100] In the etching process of the step, the mask layer 3 has little lateral loss due to the protection layer 5 (the mask layer 3 on the side wall of the core layer 2 is not etched, and the protection layer on the side wall is completely removed). At the same time, during the etching process, due to the addition of the protection layer 3, the area with small CD between adjacent side walls cannot timely remove the plasma etching product, thereby reducing the etching rate of the area with small CD between the side walls, and further ensuring that the material layer 1 to be etched in the step is not etched and lost. Compared with the scheme of the related art 2, the loss of the material to be etched between the two side walls in the step of opening the core layer top can be avoided, thereby effectively improving the pithwalking problem in the subsequent etching of the material to be etched. After the etching of the step is completed, the protection layer 5 is completely removed, and only the mask layer 3 remains as part of the side wall. The CD between the two adjacent side walls is substantially equal to the CD of the core layer, that is, b=a.

[0101] Reference Figure 6 Remove the core layer;

[0102] The method for removing the core layer comprises:

[0103] The second process gas is used to remove the core layer, and the second process gas comprises O2. That is, the core layer 2 is removed by oxidation treatment, and the material layer 1 to be etched at the bottom of the core layer 2 is exposed.

[0104] The process parameters used for removing the core layer by the second process gas comprise:

[0105] The frequency of the upper radio frequency power source and the lower radio frequency power source is 13.56 MHz;

[0106] The upper radio frequency power ranges from 100 W to 6000 W;

[0107] The lower radio frequency power is 0;

[0108] The process chamber pressure ranges from 5 mT to 100 mT;

[0109] The process chamber temperature ranges from 10℃ to 90℃;

[0110] The O2 flow rate ranges from 500 sccm to 1000 sccm.

[0111] Since the material of the core layer 2 in the embodiment is amorphous carbon, the core layer 2 is removed mainly by using high flow rate O2 under high pressure condition. Meanwhile, in order to ensure that the core layer can be removed completely and the damage to other film layers is reduced, the upper RF power is not turned on in this step.

[0112] In addition, since O2 does not react with the material of the side wall layer 3 during the removal of the core layer 2, the outer wall and the inner wall of the side wall have no lateral loss (i.e. the thickness of the side wall is basically unchanged) after the core layer 2 is removed, so the CD between adjacent side walls is still equal to the CD at the position of the original core layer, i.e. Figure 6 b=a in the formula.

[0113] Referring to Figure 7 The remaining mask layer 3 is used as a mask to etch the target pattern in the material layer 1 to be etched.

[0114] In this step, the remaining mask layer 3 (side wall) is used as a mask to etch the material layer 1 to be etched, including:

[0115] The upper RF power and the lower RF power are turned on, the remaining mask layer 3 is used as a mask, and the material layer 1 to be etched is etched by using the second etching gas.

[0116] Preferably, the upper RF power used in this step ranges from 100 W to 6000 W, and the lower RF power ranges from 10 W to 2000 W. The second etching gas includes O2 and SO2.

[0117] The process parameters for etching the material layer to be etched by using the second etching gas in this step further include:

[0118] The process chamber pressure ranges from 2 mT to 100 mT;

[0119] The process chamber pressure ranges from 10 °C to 90 °C;

[0120] The flow rate of O2 ranges from 10 sccm to 200 sccm;

[0121] The flow rate of SO2 ranges from 10 sccm to 300 sccm.

[0122] In this step, the remaining mask layer 3 (side wall) is used as a mask to perform patterning etching of the material to be etched. In this step, the upper radio frequency power is 100 W to 6000 W to generate plasma, and the lower radio frequency power is 10 W to 2000 W to provide energy and direction for the plasma, thereby enhancing anisotropic etching. When the target pattern is etched, the CD of the region between the side walls is basically the same as the CD of the region where the original core layer 2 is located, i.e., b=a, so the etching rate of the region between the side walls is basically the same as the etching rate of the region where the original core layer 2 is located. Therefore, the pith walking problem can be effectively avoided, and the lateral damage of the inner side and the outer side of the side wall is basically the same during the etching process, so that the CD of the original core layer position is equal to the CD between the side walls after the final etching target pattern is completed, i.e., a2=b2. Thus, the CD odd-even loading problem is effectively solved, and the device performance is greatly improved.

[0123] The method of the embodiment takes a self-aligned double patterning process as an example, and the preferred process recipe of each step is as follows:

[0124]

[0125] Figure 8a For the etching pattern formed by using the traditional process method, Figure 8b For the etching pattern obtained by using the method of the embodiment, it is found that the CD odd-even loading problem is obviously improved after etching by using the method of the embodiment.

[0126] Further, the method of the embodiment can not only solve the CD odd-even loading problem formed during etching, but also improve the depth loading problem, and the process only needs to perform deposition of the side wall protection film once, the requirements for photolithography and etching are not high, the process flow is simple, the controllability is good, the cost is reduced, and the device performance is improved. Moreover, the etching method of the embodiment is not limited to the self-aligned double patterning process, but can also be applied to the self-aligned quadruple patterning process and other all processes involving patterning etching.

[0127] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for etching a semiconductor structure, characterized in that, include: A material layer to be etched is provided, on which a plurality of discrete core layers are formed; Mask layers are formed on the material layers to be etched exposed between the core layers, as well as on the top and sidewalls of the core layers. The lateral dimension between the vertical mask layers at the sidewalls of two adjacent core layers is equal to the width dimension of the core layer. A protective layer is formed on the mask layer, and the mask layer and the protective layer on the sidewall of the core layer form a sidewall, wherein the lateral spacing between adjacent outer walls of the sidewall is smaller than the width of the core layer; Anisotropic etching is performed on the protective layer and part of the mask layer until the protective layer is completely removed and the top of the core layer and part of the material layer to be etched between adjacent core layers are exposed; Remove the core layer; The remaining mask layer is used as a mask to etch the material layer to be etched, forming a target pattern in the material layer to be etched.

2. The etching method according to claim 1, characterized in that, The formation of a protective layer on the mask layer includes: A protective layer of a predetermined thickness is deposited on the mask layer using a first process gas, wherein the first process gas is one or more of CH3F, CH2F2, HBr, CH4, SiCl4, and O2. The protective layer is made of silicon oxide, CF-type polymers, or Si-O-Br-type polymers.

3. The etching method according to claim 2, characterized in that, The set thickness is 4. The etching method according to claim 2, characterized in that, The first process gas includes SiCl4 and O2; The process parameters used to deposit a protective layer of a predetermined thickness on the mask layer using a first process gas include: The RF power range is 100W to 2000W; The lower radio frequency power range is 10W to 1500W; The pressure range of the process chamber is 3mT to 100mT; The temperature range of the process chamber is 10℃~90℃; The flow rate range of SiCl4 is 1 sccm to 100 sccm; The flow rate range for O2 is 1 sccm to 100 sccm.

5. The etching method according to claim 1, characterized in that, The anisotropic etching of the protective layer and a portion of the mask layer includes: Turn on the upper and lower radio frequency power, and use the first etching gas to remove the protective layer and the portion of the mask layer above the material layer to be etched located above the top of the core layer and between the adjacent core layers; The upper RF power range is 100W to 3000W; the lower RF power range is 50W to 1000W.

6. The etching method according to claim 5, characterized in that, The first etching gas includes CF4 and CHF3.

7. The etching method according to claim 6, characterized in that, The process parameters used for anisotropic etching of the protective layer and part of the mask layer also include: The pressure range of the process chamber is 3mT to 100mT; The temperature range of the process chamber is 10℃~90℃; The flow rate range of CF4 is 10 sccm to 200 sccm; The flow rate range for CHF3 is 10 sccm to 200 sccm.

8. The etching method according to claim 1, characterized in that, In the step of removing the core layer, only the upper radio frequency power is turned on; The upper radio frequency power range is 100W to 6000W.

9. The etching method according to claim 1, characterized in that, The etching of the material layer to be etched using the remaining mask layer as a mask includes: Turn on the upper and lower radio frequency power, use the remaining mask layer as a mask, and use the second etching gas to etch the material layer to be etched; The upper RF power range is 100W to 6000W; the lower RF power range is 10W to 2000W.

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