Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, wherein the ion implantation concentration of the drift region formed in the N-type deep well region in the PLDMOS device is reduced and then increased in the direction away from the top surface of the substrate. Thus, the breakdown voltage of the PLDMOS device is improved, the on-resistance is reduced, and the performance of the PLDMOS device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] LDMOS is widely used in power management circuit due to its advantages of high voltage resistance, large current driving capability, extremely low power consumption and CMOS integration. The breakdown voltage and on-resistance of the middle-high voltage PLDMOS are important electrical indicators of the device.

[0003] Figure 1 A schematic diagram of a middle-high voltage PLDMOS device structure in the prior art is shown in FIG. 1, in which a substrate 1 is a P-type substrate, a deep well region 11 is formed in the substrate 1, the deep well region 11 is an N-type deep well, and each structure of the middle-high voltage PLDMOS device is formed in the deep well region 11 to be isolated from the P-type substrate. Figure 1 The drift region 12 adopts a P-type deep well to achieve a higher breakdown voltage, and the deep well region 11 is used as a device channel region, and its depth is greater than that of the drift region 12. If the ion implantation concentration of the drift region 12 formed by the P-type deep well is low, the deep well region 11 formed by the N-type deep well below is not easy to be depleted, thereby resulting in a low breakdown voltage of the middle-high voltage PLDMOS device. If the ion implantation concentration of the drift region 12 formed by the P-type deep well is high, although the deep well region 11 formed by the N-type deep well below is depleted, the drift region 12 formed by the P-type deep well cannot be completely depleted, which still results in a low breakdown voltage of the middle-high voltage PLDMOS device. Therefore, improving the breakdown voltage of the middle-high voltage PLDMOS device is a long-term research topic for technical personnel. SUMMARY

[0004] The present application aims to provide a semiconductor structure and a manufacturing method thereof to solve the problem of low performance of the PLDMOS device caused by the fact that the breakdown voltage and on-resistance of the PLDMOS device in the prior art cannot meet the requirements at the same time.

[0005] To solve the above problem, the present application provides a semiconductor structure, wherein,

[0006] a substrate is provided;

[0007] a first ion implantation process is performed on the substrate to form a deep well region in the substrate;

[0008] a field oxide layer is formed on the substrate, the field oxide layer comprising first and second field oxide structures arranged at intervals;

[0009] performing a second ion implantation process on the substrate to form a drift region within the deep well region and to position the second field oxide structure in the drift region, wherein the drift region has a depth less than the deep well region and an ion implantation concentration that decreases and then increases in a direction away from a top surface of the substrate;

[0010] forming a gate polysilicon layer on the substrate, the gate polysilicon layer being formed within the drift region.

[0011] Optionally, the drift region is divided into a first drift region, a second drift region and a third drift region in a direction away from a top surface of the substrate, wherein the first drift region has an ion implantation concentration greater than an ion implantation concentration of the third drift region, and the third drift region has an ion implantation concentration greater than an ion implantation concentration of the second drift region.

[0012] Optionally, the first drift region has an ion implantation amount greater than an ion implantation amount of the third drift region, and the third drift region has an ion implantation amount greater than an ion implantation amount of the second drift region.

[0013] Optionally, the ion implantation amount of the first drift region is at least 2el l cm -2 .

[0014] Optionally, the ion implantation amount of the third drift region is at least 3el l cm -2 .

[0015] Optionally, the third drift region has an ion implantation energy greater than an ion implantation energy of the second drift region, and the second drift region has an ion implantation energy greater than an ion implantation energy of the first drift region.

[0016] Optionally, the ion implantation energy of the third drift region is at least 300 kev greater than an ion implantation energy of the second drift region.

[0017] Optionally, an ion implantation concentration of an adjacent region of the first drift region and the second drift region changes slowly, and / or an ion implantation concentration of an adjacent region of the second drift region and the third drift region changes slowly.

[0018] Optionally, after the gate polysilicon layer is formed, the method further comprises:

[0019] performing a third ion implantation process to form a first heavily doped region and a second heavily doped region in the substrate, the first heavily doped region being formed in the deep well region and positioned between the first field oxide structure and the gate polysilicon layer, and the second heavily doped region being formed in the drift region and positioned on a side of the second field oxide structure away from the gate polysilicon layer.

[0020] performing a fourth ion implantation process to form a third heavily doped region in the substrate, the third heavily doped region being formed in the deep well region and located at a side of the first field oxide structure away from the polysilicon gate.

[0021] Furthermore, to solve the above problems, the application also provides a semiconductor structure prepared according to the manufacturing method of the semiconductor structure according to any one of the above.

[0022] In the semiconductor structure and the manufacturing method thereof, the ion implantation concentration of the drift region formed in the N-type deep well region in the PLDMOS device is reduced and then increased in the direction away from the top surface of the substrate. In this way, the breakdown voltage of the PLDMOS device can be improved and the on-resistance can be reduced, and thus the performance of the PLDMOS device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structure schematic diagram of a PLDMOS device in the prior art;

[0024] Figure 2 is a flow chart of the manufacturing method of the semiconductor structure in an embodiment of the application;

[0025] Figures 3 to 7 is a process schematic diagram of the manufacturing method of the semiconductor structure in an embodiment of the application.

[0026] In the drawings, the reference signs are as follows:

[0027] 1 - substrate;

[0028] 11 - deep well region;

[0029] 12 - drift region; 121 - first drift region;

[0030] 122 - second drift region; 123 - third drift region;

[0031] 13 - first heavily doped region; 14 - second heavily doped region;

[0032] 15 - third heavily doped region;

[0033] 2 - field oxide layer;

[0034] 21 - first field oxide structure; 22 - second field oxide structure;

[0035] 3 - gate oxide layer;

[0036] 4 - gate polysilicon layer;

[0037] 5 - metal plug layer; 51 - metal plug;

[0038] 6-metal electrode layer; 61-metal electrode. DETAILED DESCRIPTION

[0039] The semiconductor structure and the manufacturing method thereof according to the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are all simplified and use non-precise proportions, only for the purpose of facilitating and clarifying the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, different proportions are sometimes used in the drawings to show different focuses.

[0040] Figure 2 is a flow chart of the manufacturing method of the semiconductor structure in an embodiment of the present application; Figures 3 to 7 is a process schematic diagram of the manufacturing method of the semiconductor structure in an embodiment of the present application. The manufacturing method of the semiconductor structure in the embodiment will be described below in conjunction with Figures 2 to 7

[0041] In step S10, referring to Figure 2 and in conjunction with Figure 3 , a substrate 1 is provided.

[0042] In the embodiment, the material forming the substrate 1 can include semiconductor material, conductor material or any combination thereof; and the substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors; or can include a layered substrate such as, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-on-silicon germanium.

[0043] In step S20, referring to Figure 2 and in conjunction with Figure 3 , a first ion implantation process is performed on the substrate 1 to form a deep well region 11 in the substrate 1.

[0044] In the embodiment, the deep well region 11 is formed on the top surface of the entire substrate 1 and extends away from the top surface of the substrate 1, and the depth of the deep well region 11 is less than the thickness of the substrate 1. In addition, in the embodiment, the ions implanted by the first ion implantation process are N-type ions, and the deep well region 11 is an N-type deep well. In addition, in the embodiment, the substrate 1 is a P-type substrate.

[0045] In step S30, referring to Figure 2 and in conjunction with Figure 4 ​As shown, a field oxide layer 2 is formed on the substrate 1, wherein the field oxide layer 2 comprises a first field oxide structure 21 and a second field oxide structure 22. In the present embodiment, the field oxide layer 2 is formed by forming a mask layer on the substrate 1, etching to open the field oxide region, and then growing the field oxide layer 2.

[0046] In step S40, the process continues with Figure 2 In combination with Figure 5 As shown, a second ion implantation process is performed on the substrate 1 to form a drift region 12 in the deep well region 11 and to position the second field oxide structure 22 in the drift region 12, wherein the depth of the drift region 12 is less than the depth of the deep well region 11, and the ion implantation concentration of the drift region 12 decreases and then increases in a direction away from the top surface of the substrate 1.

[0047] In the present embodiment, the drift region 12 formed in the N-type deep well region 11 in the PLDMOS device has an ion implantation concentration that decreases and then increases in a direction away from the top surface of the substrate 1. This can improve the breakdown voltage and reduce the on-resistance of the PLDMOS device, thereby improving the performance of the PLDMOS device.

[0048] Further, in the present embodiment, the second ion implantation process implants P-type ions, and the drift region is formed by P-type deep wells. In addition, in the present embodiment, the ion implantation concentration of the drift region 12 decreases and then increases in a direction away from the top surface of the substrate 1. It can be understood that the ion implantation concentration of the drift region 12 has a trend of being high at both ends and low in the middle in a direction away from the top surface of the substrate 1. In the present embodiment, the N-type ions include phosphorus, arsenic, or antimony ions. The P-type ions include boron, gallium, or indium ions.

[0049] Further, the process continues with Figure 5 In combination with Figure 6 As shown, the drift region 12 is divided into a first drift region 121, a second drift region 122, and a third drift region 123 in a direction away from the top surface of the substrate 1, wherein the ion implantation concentration of the first drift region 121 is greater than that of the third drift region 123, and the ion implantation concentration of the third drift region 123 is greater than that of the second drift region 122.

[0050] In the present embodiment, the ion implantation amount of the first drift region 121 is greater than that of the third drift region 123, and the ion implantation amount of the third drift region 123 is greater than that of the second drift region 122. In addition, the ion implantation amount of the first drift region 121 is at least 2e11 cm-2 greater than that of the third drift region 123.-2 The ion implantation amount in the third drift region 123 is at least 3e11 cm greater than the ion implantation amount in the second drift region 122. -2 .

[0051] Furthermore, the ion implantation energy of the third drift region 123 is greater than that of the second drift region 122, and the ion implantation energy of the second drift region 122 is greater than that of the first drift region 121. In addition, the ion implantation energy of the third drift region 123 is at least 300 keV greater than that of the second drift region 122.

[0052] Furthermore, in this embodiment, the ion implantation concentration in the region adjacent to the first drift region 121 and the second drift region 123 changes slowly, and / or the ion implantation concentration in the region adjacent to the second drift region 122 and the third drift region 123 changes slowly.

[0053] In step S50, as Figure 5 As shown, a gate polysilicon layer 4 is formed on the substrate 1, and the gate polysilicon layer 4 is formed within the drift region 12.

[0054] In this embodiment, polycrystalline silicon material is deposited using physical vapor deposition (PVD) to form the gate polycrystalline silicon layer 4. Furthermore, in this embodiment, before forming the gate polycrystalline silicon layer 4, the method further includes: forming a gate dielectric layer 3 on the substrate 1, and ensuring that the gate oxide layer 3 is at least below the gate polycrystalline silicon gate layer 4. The material forming the gate dielectric layer 3 is silicon oxide.

[0055] Further, continue to participate Figure 5 and combined Figure 7 As shown, after forming the gate polysilicon layer 4, the method further includes the following first and second steps.

[0056] In the first step, a third ion implantation process is performed to form a first heavily doped region 13 and a second heavily doped region 14 in the substrate 1. The first heavily doped region 13 is formed in the deep well region 11 and is located between the first field oxygen structure 21 and the gate polysilicon layer 4. The second heavily doped region 14 is formed in the drift region 12 and is located on the side of the second field oxygen structure 22 away from the gate polysilicon layer 4.

[0057] The ions implanted in the first heavily doped region 13 and the second heavily doped region 14 are P-type ions. Furthermore, the first heavily doped region 13 forms the source of the PLDMOS, and the second heavily doped region 14 forms the drain of the PLDMOS.

[0058] In the second step, a fourth ion implantation process is performed to form a third heavily doped region 15 in the substrate 1, the third heavily doped region 15 is formed in the deep well region 11 and located at the side of the first field oxide structure 21 away from the gate polysilicon gate 4. In the embodiment, the third heavily doped region 15 constitutes the body contact region of the PLDMOS.

[0059] Further, continuing to refer to Figure 7 As shown, after the fourth ion implantation process is performed, the method further comprises the following steps.

[0060] First, a metal plug layer 5 is formed, the metal plug layer 5 comprises a plurality of metal plugs 51, wherein the first heavily doped region 14, the second heavily doped region 15 and the third heavily doped region 16 are respectively provided with one metal plug 51.

[0061] Second, a metal electrode layer 6 is formed on the metal plug layer 5, the metal electrode layer 6 comprises a plurality of metal electrodes 61, the metal electrodes 61 and the metal plugs 51 are one-to-one corresponding electrically connected. In the embodiment, the material of the metal plug layer 5 and the metal electrode 6 is copper.

[0062] Further, in the embodiment, a semiconductor structure is also provided, the semiconductor structure is prepared by the manufacturing method of the semiconductor structure provided above.

[0063] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way, any modification or change made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises: providing a substrate; performing a first ion implantation process on the substrate to form a deep well region in the substrate; forming a field oxide layer on the substrate, the field oxide layer comprising a first field oxide structure and a second field oxide structure arranged at intervals; performing a second ion implantation process on the substrate to form a drift region within the deep well region and to position the second field oxide structure in the drift region, wherein a depth of the drift region is less than a depth of the deep well region, and an ion implantation concentration of the drift region decreases and then increases in a direction away from a top surface of the substrate, wherein the drift region is divided into a first drift region, a second drift region, and a third drift region in the direction away from the top surface of the substrate, wherein the ion implantation concentration of the first drift region is greater than the ion implantation concentration of the third drift region, and the ion implantation concentration of the third drift region is greater than the ion implantation concentration of the second drift region; forming a gate polysilicon layer on the substrate, the gate polysilicon layer being formed within the drift region.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The ion implantation amount of the first drift region is greater than the ion implantation amount of the third drift region, and the ion implantation amount of the third drift region is greater than the ion implantation amount of the second drift region.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein the first drift region has an ion implantation amount that is at least 2e11 cm greater than an ion implantation amount of the third drift region -2 .

4. The method of manufacturing a semiconductor structure according to claim 2, wherein the third drift region has an ion implantation amount that is at least 3e11 cm greater than the ion implantation amount of the second drift region -2 .

5. The method of manufacturing a semiconductor structure of claim 1, wherein, The ion implantation energy of the third drift region is greater than the ion implantation energy of the second drift region, and the ion implantation energy of the second drift region is greater than the ion implantation energy of the first drift region.

6. The method of manufacturing a semiconductor structure of claim 1, wherein, The ion implantation energy of the third drift region is at least 300 keV greater than the ion implantation energy of the second drift region.

7. The method of manufacturing a semiconductor structure of claim 1, wherein, The ion implantation concentration of a region adjacent to the first drift region and the second drift region changes slowly, and / or the ion implantation concentration of a region adjacent to the second drift region and the third drift region changes slowly.

8. The method of manufacturing a semiconductor structure of claim 1, wherein, The method further comprises, after forming the gate polysilicon layer: performing a third ion implantation process to form a first heavily doped region and a second heavily doped region in the substrate, the first heavily doped region being formed in the deep well region and positioned between the first field oxide structure and the gate polysilicon layer, and the second heavily doped region being formed in the drift region and positioned on a side of the second field oxide structure away from the gate polysilicon layer; performing a fourth ion implantation process to form a third heavily doped region in the substrate, the third heavily doped region being formed in the deep well region and positioned on a side of the first field oxide structure away from the gate polysilicon layer.

9. A semiconductor structure, characterized by The semiconductor structure is prepared according to the method for manufacturing a semiconductor structure according to any one of claims 1-8.

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