Pad structure and online monitoring method for photolithography splicing process

Abstract

The application provides a kind of pad structure and photolithography splicing process online monitoring method. Specifically, the application provides a new type of pad structure, including a plurality of side-by-side arrangement of large pads (main pads), and a plurality of square small pads (secondary pads) embedded in each large pad (main pad), so as to propose a nested way of large and small pads, forming a set of pad structure for testing some parameters of splicing chip in all directions without dead angle; then, based on the above-mentioned new structure of the pad structure provided by the application, the pad structure with the special structure is used, and combined with manual measurement of chip size, manual dicing and other manual operation methods, thereby solving the problem that the thickness of the splicing chip layout in the layout of the image sensor containing super large pixel unit manufactured by using the super splicing process cannot be directly monitored and measured in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an online monitoring method for pad structure and photolithography splicing process. Background Technology

[0002] In recent years, image sensors (CMOS image sensors, CIS) have been used more and more widely and deeply in consumer electronics, security, medical, autonomous driving, 3D sensing and other fields. However, from the current market structure, the market, especially the high-end market, has long been monopolized by overseas manufacturers, while Chinese manufacturers are mainly involved in the low-end and mid-range mobile application fields.

[0003] To break the monopoly of foreign manufacturers in the high-end CIS product market, researchers in this field have focused on developing ultra-high pixel count, ultra-high frame rate, and all-weather ultra-high definition scientific application CIS products in recent years. They have pioneered the introduction of a super-splitting process (dividing the photomask into multiple exposure areas and exposing each area multiple times on the wafer), successfully manufacturing a CIS chip with ultra-large pixel units (7.5µm), ultra-high pixel count (225 million pixels), and ultra-large area (>10µm*10µm). This is currently the world's highest pixel count and largest area product, with only two chips produced per 12-inch wafer. The splicing technology, as the name suggests, involves dividing the involved pattern areas during chip manufacturing, exposing them sequentially, and ultimately splicing them together to form a large-size pattern sensor.

[0004] Currently, for traditional chips, the online process can be monitored normally through a monitorpad. Recipesetup only needs to perform alignment, then draw the die, and finally find the measurement pad based on the coordinates to accurately measure the film thickness. However, for spliced ​​products using super-splitter technology, the number of effective chip dies in the wafer is far less than the number of chip dies contained in a normal wafer wafer, which makes it impossible to draw dies, i.e., film thickness measurement cannot be performed. Summary of the Invention

[0005] The purpose of this invention is to provide an online monitoring method for pad structure and photolithography splicing process, so as to solve the problem in the prior art that the thickness of the splicing chip layout in the layout of an image sensor containing ultra-large pixel units manufactured using super splicing process cannot be directly monitored and measured.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a pad structure, which may specifically include: a plurality of main pads and a plurality of sub-pads located in each of the main pads; wherein, the plurality of main pads are arranged side by side with intervals along the X direction or the Y direction, while the plurality of sub-pads located in each main pad are arranged symmetrically with intervals along the X direction and the Y direction.

[0007] Furthermore, the main pad can be a regular quadrilateral, and the side length of the main pad can be in the range of 400μm to 600μm.

[0008] Furthermore, the sub-pad can be in the positive direction, and the side length of the sub-pad can be in the range of 50μm to 70μm.

[0009] Furthermore, the sizes of the multiple main pads may be the same or different, while the sizes of the multiple sub-pads are all the same.

[0010] Secondly, based on the pad structure described above, the present invention also provides an online monitoring method for photolithography splicing processes, which may specifically include the following steps:

[0011] A splicing chip layout is determined, the splicing chip layout being used to manufacture an image sensor containing ultra-large pixel units using a super splicing process, and based on the pad structure of any one of claims 1-3, at least one of the pad structures is provided on the periphery of the splicing chip in the splicing chip layout;

[0012] A photolithography splicing process, including multiple regional exposures, is performed on the spliced ​​chip layout containing the pad structure to form an actual layout on the target wafer containing multiple spliced ​​chips corresponding to the spliced ​​chip layout.

[0013] The actual layout of the splicing chip is measured to determine the size of the splicing chip. After aligning and dicing the splicing chip, a preset pad structure is found, and the film thickness of the splicing chip is measured using the preset pad structure.

[0014] Furthermore, the number of splicing chips contained in the target wafer can be less than 16.

[0015] Furthermore, the number of splicing chips contained in the target wafer can specifically be 2.

[0016] Furthermore, the actual layout size of the splicing chip can be greater than 26mm × 33mm.

[0017] Furthermore, the size of the splicing chip can be determined by manual measurement.

[0018] Furthermore, the target wafer is diced manually.

[0019] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0020] 1. This invention provides a novel pad structure, including multiple large pads (main pads) arranged side by side, and multiple small square pads (sub-pads) embedded in each large pad (main pad), thereby proposing a method of nesting large and small pads to form a set of pad structures for testing certain parameters of spliced ​​chips from all directions without blind spots.

[0021] 2. Based on the novel pad structure provided by the present invention, the present invention also provides an online monitoring method for photolithography splicing process. This method utilizes the special pad structure and combines it with manual operations such as manual chip size measurement and manual dicing to solve the problem in the prior art that the thickness of the spliced ​​chip layout in the layout of an image sensor containing ultra-large pixel units manufactured using super splicing process cannot be directly monitored and measured. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the main pad structure in a pad structure according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of any main pad and its sub-pad in a pad structure according to an embodiment of the present invention;

[0024] Figure 3 This is a flowchart illustrating an online monitoring method for photolithography splicing process according to an embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, to break the monopoly of foreign manufacturers in the high-end CIS product market, researchers in this field have recently focused on the development of scientific-grade CIS products with ultra-high pixel counts, ultra-high frame rates, and all-weather ultra-high definition. They have pioneered the introduction of a super-splitting process (dividing the photomask into multiple exposure areas and exposing each area multiple times on the wafer), successfully manufacturing a CIS chip with ultra-large pixel units (7.5µm), ultra-high pixel counts (225 million pixels), and ultra-large area (>10µm*10µm). This is currently the world's highest-pixel and largest-area product, with only two chips produced per 12-inch wafer. The splicing technology, as the name suggests, involves dividing the involved pattern areas during chip manufacturing, exposing them sequentially, and ultimately splicing them together to form a large-size pattern sensor.

[0026] Currently, for traditional chips, online processes can be monitored normally via a monitorpad. Recipe setup only requires alignment, die drawing, and finally locating the measurement pad based on the coordinates to accurately measure the film thickness. However, for spliced ​​products using super-splitter technology, the number of effective chip dies in the wafer is far less than the number of chip dies contained in a normal wafer wafer, making die drawing impossible, and thus preventing film thickness measurement.

[0027] To address this issue, the present invention provides an online monitoring method for pad structure and photolithography splicing process, thereby solving the problem in the prior art that the thickness of the spliced ​​chip layout in the layout of an image sensor containing ultra-large pixel units manufactured using super splicing technology cannot be directly monitored and measured.

[0028] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the online monitoring method for pad structure and photolithography splicing process proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention can also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0029] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0030] The pad structure provided in the embodiments of the present invention will be described below. See details below. Figure 1 and Figure 2 ,in, Figure 1 This is a schematic diagram of the main pad structure in a pad structure according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of any main pad and its sub-pad in a pad structure according to an embodiment of the present invention. (In conjunction with the above...) Figure 1 and Figure 2As can be seen, the pad structure provided by the present invention may specifically include: a plurality of main pads 11 and a plurality of sub-pads 22 located in each of the main pads; wherein, the plurality of main pads 11 may be arranged side by side with intervals along the X direction or the Y direction, while the plurality of sub-pads 22 located in each of the main pads 11 are arranged symmetrically with intervals along the X direction and the Y direction.

[0032] As an example, in this embodiment of the invention, the shape of the main pad 11 can specifically be a regular quadrilateral, that is, it can be as follows: Figure 1 The aforementioned square shape, when the main pad is square, its side length can specifically range from 400μm to 600μm. That is, the main pad provided by this invention can be a square with a side length of 400μm, a square with a side length of 500μm, or a square with a side length of 600μm, such as... Figure 1 As shown. Furthermore, exemplarily, the patterns of the multiple sub-pads located within the main pad 11, which is square in shape, can all be in a positive orientation. When the sub-pad is square, its side length can specifically range from 50μm to 70μm. That is, the sub-pad provided by this invention can be a square with a side length of 50μm, a square with a side length of 60μm, or a square with a side length of 70μm, such as... Figure 2 As shown.

[0033] In this embodiment, the novel pad structure provided includes multiple large pads (main pads) arranged side by side, and multiple small square pads (sub-pads) embedded in each large pad (main pad), thereby proposing a method of nesting large and small pads to form a set of pad structures for testing certain parameters of spliced ​​chips from all directions without blind spots.

[0034] It should be noted that, in the embodiments of the present invention, it can be as follows: Figure 1 The three different sizes of main pads are arranged sequentially along one direction, such as the X or Y direction. In other embodiments, multiple main pads of the same size can also be arranged sequentially along one direction, such as the X or Y direction. Regardless of which of the above situations applies to the main pads, the multiple sub-pads embedded in each of the main pads provided by the present invention have the same size, and preferably are 60μm*60μm squares.

[0035] Based on the above Figure 1 The aforementioned pad structure, in this embodiment of the invention, also provides an online monitoring method for the photolithography splicing process. See details... Figure 3 , Figure 3 This is a flowchart illustrating an online monitoring method for a photolithography splicing process provided by the present invention. The online monitoring method for the photolithography splicing process specifically includes the following steps:

[0036] Step S100: Determine the layout of the splicing chip. The splicing chip layout is used to manufacture an image sensor containing ultra-large pixel units using a super-slicing process. Based on the pad structure described above, at least one of the pad structures is disposed around the periphery of the splicing chip in the splicing chip layout. The actual layout size of the splicing chip is greater than 26mm × 33mm.

[0037] In this embodiment, when the chip size exceeds the maximum exposure size of the chip layout (26mm × 33mm), it cannot be obtained using conventional single-step photolithography. Therefore, multiple regional photolithography stitching processes (i.e., zoned exposure and pattern stitching) are required. Specifically, according to the design method of the stitched chip layout provided in this invention, a large-size chip stitched chip layout can be designed. Then, using the designed stitched chip layout as a mask, the target wafer is exposed multiple times in a zoned manner through photolithography, thereby forming the actual layout of the stitched chip on the target wafer. In the photolithography stitching process, the alignment marks located on both sides of the same main light-shielding zone of the stitched chip layout are aligned one-to-one, so that the actual layout of the stitched chip forms seams of the corresponding alignment marks at the corresponding positions.

[0038] In this embodiment, in order to develop scientific-grade CIS products with ultra-high pixel count, ultra-high frame rate, and all-weather ultra-high definition, the inventors pioneered the introduction of a super-splitting process (dividing the photomask into multiple exposure areas and exposing each area multiple times on the wafer). This successfully manufactured a CIS chip with ultra-large pixel units (7.5µm), ultra-high pixel count (225 million pixels), and ultra-large array size (>10µm*10µm), making it the world's highest-pixel and largest-array product. However, each 12-inch wafer in this chip product can only produce two chips. Since the effective number of chip dies in the wafer is far less than the number of chip dies contained in a normal wafer wafer, die dicing is impossible, meaning film thickness measurement is not possible.

[0039] Therefore, the present invention proposes a method utilizing such Figure 1 , Figure 2 The method for measuring film thickness using the novel pad structure shown is then used. By utilizing this special pad structure and combining it with manual operations such as manually measuring chip size and manually dicing, the problem in the prior art of not being able to directly monitor and measure the thickness of the spliced ​​chip layout in the layout of an image sensor containing ultra-large pixel units manufactured using super splicing technology is solved.

[0040] Step S200 involves performing a photolithography splicing process, including multiple regional exposures, on the spliced ​​chip layout containing the pad structure, to form an actual layout on the target wafer containing multiple spliced ​​chips corresponding to the spliced ​​chip layout. The number of spliced ​​chips contained in the target wafer is less than 16, but in this embodiment of the invention, the number of spliced ​​chips contained in the target wafer is 2.

[0041] Step S300: Measure the actual layout of the splicing chip to determine the size of the splicing chip, and after aligning and dicing the splicing chip, find the preset pad structure and use the preset pad structure to measure the film thickness of the splicing chip.

[0042] In this embodiment, the inventors propose a method to first determine the size of the splicing chip by manual measurement, then manually dicing the target wafer, and finally finding one or more pads for specifying the film thickness for splicing the chips on both sides, and then using the pads for measurement to determine the parameters to be tested.

[0043] In summary, this invention provides a novel pad structure, comprising multiple large pads (main pads) arranged side by side, and multiple small square pads (sub-pads) embedded in each large pad (main pad), thereby proposing a method of nesting large and small pads to form a set of pad structures for omnidirectional, blind-angle testing of certain parameters of spliced ​​chips.

[0044] Furthermore, based on the novel pad structure provided by this invention, this invention also provides an online monitoring method for photolithography splicing process. This method utilizes the special pad structure and combines it with manual operations such as manual chip size measurement and manual dicing to solve the problem in the prior art that the thickness of the spliced ​​chip layout in the layout of an image sensor containing ultra-large pixel units manufactured using super splicing technology cannot be directly monitored and measured.

[0045] It should be noted that the embodiments of the present invention also provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0046] Memory, used to store computer programs;

[0047] The processor, when executing the program stored in the memory, implements the online monitoring method for photolithography splicing process provided in this embodiment of the invention.

[0048] In addition, other implementations of the online monitoring method for photolithography splicing process implemented by the processor executing the program stored in the memory are the same as those mentioned in the aforementioned method embodiment section, and will not be repeated here.

[0049] The communication bus mentioned in the control terminal above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0050] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0051] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0052] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0053] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform the online monitoring method for the photolithography splicing process described in any of the above embodiments.

[0054] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0055] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. An in-line monitoring method of a photolithography stitching process, implemented by a pad structure, the pad structure comprising: A plurality of main pads and a plurality of sub-pads in each of the main pads; wherein the plurality of main pads are arranged in sequence and side by side in the X direction or the Y direction, and the plurality of sub-pads in each main pad are arranged in sequence and symmetrically in the X direction and the Y direction, characterized in that the method comprises the following steps: determining a tiled chip layout for an image sensor containing super-large pixel units manufactured by using a super tiling process, and setting at least one pad structure in the periphery of a tiled chip in the tiled chip layout based on the pad structure; performing a photolithography tiling process including multiple sub-regional exposures on the tiled chip layout containing the pad structure to form an actual layout containing a plurality of tiled chips corresponding to the tiled chip layout on a target wafer; measuring the actual layout of the tiled chip to determine the size of the tiled chip, and finding a preset pad structure after aligning and dicing the tiled chip, and measuring the film thickness of the tiled chip by using the preset pad structure.

2. The method for on-line monitoring of a photolithography stitching process according to claim 1, wherein, The main pad is a regular quadrilateral, and the side length of the main pad ranges from 400µm to 600µm.

3. The method of on-line monitoring of a photolithographic stepper process as claimed in claim 1, characterized in that, The sub-pad is a square, and the side length of the sub-pad ranges from 50µm to 70µm.

4. The method of on-line monitoring of a photolithographic stepper process as claimed in claim 1, characterized in that, The sizes of the plurality of main pads are the same or different, and the sizes of the plurality of sub-pads are the same.

5. The method of on-line monitoring of a photolithographic stepper process as claimed in claim 1, characterized in that, The number of tiled chips contained in the target wafer is less than 16.

6. The method of on-line monitoring of a photolithographic stepper process as recited in claim 5, wherein, The number of tiled chips contained in the target wafer is 2.

7. The method for on-line monitoring of a photolithography stitching process according to claim 1, wherein, The size of the actual layout of the tiled chip is greater than 26mm×33mm.

8. The method for on-line monitoring of a photolithography stitching process according to claim 1, wherein, The size of the tiled chip is determined by manual measurement.

9. The method for on-line monitoring of a photolithography stitching process according to claim 8, wherein, The target wafer is diced by manual operation.

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