Semiconductor structure and manufacturing method

Abstract

This invention provides a semiconductor structure and its manufacturing method. The manufacturing method includes the following steps: providing a substrate wafer having a first surface and a second surface disposed opposite to each other, the first surface of the substrate wafer having a via extending into the interior of the substrate wafer; forming a void structure within the substrate wafer using a laser focusing method; forming a through-silicon via (TSV) structure within the via, at least a portion of the TSV structure being surrounded by the void structure; and fabricating a device on the first surface of the substrate wafer. The advantage of this invention is that it can naturally form a closed void structure using a laser focusing method during the formation of the void structure, thus maintaining the design pattern of the void structure, ensuring the stress release effect of the TSV structure, increasing the area of ​​the region around the TSV structure unaffected by internal stress, thereby increasing the number of transistors and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] Through-Silicon Via (TSV) technology is a novel technical solution for interconnecting stacked chips in three-dimensional integrated circuits. TSVs enable maximum chip stacking density in the vertical direction, minimize interconnect lines between chips, and reduce overall form factor. Compared to two-dimensional integrated packaging, TSV-based three-dimensional integration technology can further reduce chip integration area and volume, increase integration density, and significantly improve chip speed and low-power performance. It has become one of the most compelling technologies in electronic packaging and is considered capable of extending Moore's Law in the post-Moore's Law era.

[0003] However, in traditional through-silicon via (TSV) structures, the internal stress generated when the TSV structure contracts or expands can be transmitted to adjacent transistors, affecting their electrical performance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can effectively block the propagation of internal stress generated during the contraction / expansion of the through-silicon via structure to the surrounding transistors, thereby increasing the area of ​​the region around the through-silicon via structure that is not affected by internal stress, so as to increase the number of transistors.

[0005] To address the aforementioned problems, the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate wafer having a first surface and a second surface disposed opposite to each other, the first surface of the substrate wafer having a via extending into the interior of the substrate wafer; forming a void structure within the substrate wafer using a laser focusing method; forming a through-silicon via (TSV) structure within the via, at least a portion of the TSV structure being surrounded by the void structure; and fabricating a device on the first surface of the substrate wafer.

[0006] Optionally, the step of forming a void structure in the substrate wafer using a laser focusing method further includes: applying a laser focusing method to the substrate wafer once or multiple times from the second surface of the substrate wafer to form one or more void structures in the substrate wafer.

[0007] Optionally, the void structure is a closed structure and is located at a predetermined distance from the first surface of the substrate wafer.

[0008] Optionally, the step of forming a through-silicon via structure within the via, wherein at least a portion of the sides of the through-silicon via structure are surrounded by the void structure, further includes: forming an isolation layer within the via, the isolation layer covering the inner wall of the via and a first surface of the substrate wafer; forming a conductive filling layer filling the via; and removing a portion of the substrate wafer from a second surface of the substrate wafer to expose the bottom of the conductive filling layer, thereby forming the through-silicon via structure.

[0009] Optionally, the step of forming a conductive fill layer, wherein the conductive fill layer fills the via, further includes: forming a barrier layer, wherein the barrier layer covers the isolation layer; forming a seed layer, wherein the seed layer covers the barrier layer; and forming an electroplated layer on the seed layer, wherein the electroplated layer fills the via.

[0010] Optionally, after the step of forming an electroplated layer on the seed layer and filling the via with the electroplated layer, the method further includes: removing the barrier layer, seed layer and electroplated layer corresponding to the first surface of the substrate wafer, leaving only the barrier layer, seed layer and electroplated layer located in the via.

[0011] Optionally, the first surface of the substrate wafer is provided with an insulating layer and a top silicon layer, and the via penetrates the insulating layer and the top silicon layer. In the step of fabricating a device on the first surface of the substrate wafer, the device is formed on the top silicon layer.

[0012] The present invention also provides a semiconductor structure comprising: a substrate having a first surface and a second surface disposed opposite to each other, and a void structure formed by laser focusing method disposed within the substrate; a device disposed on the first surface of the substrate; and a through-silicon via structure penetrating the substrate, wherein at least a portion of the sides of the through-silicon via structure are surrounded by the void structure.

[0013] Optionally, the void structure is a ring surrounding the through-silicon via structure, and the cross-section of the ring is elliptical in the direction perpendicular to the substrate.

[0014] Optionally, the void structure is composed of multiple rings.

[0015] Optionally, multiple rings are arranged in an array along a direction perpendicular to and / or parallel to the substrate.

[0016] Optionally, the through-silicon via structure is coaxial with the annulus.

[0017] Optionally, the device is disposed corresponding to the void structure in a direction perpendicular to the substrate.

[0018] Optionally, the device is misaligned with the void structure in a direction perpendicular to the substrate.

[0019] Optionally, the through-silicon via structure includes: a via penetrating the substrate; an isolation layer covering the inner wall of the via, the first surface of the substrate, and the device; and a conductive filling layer filling the via.

[0020] Optionally, the conductive filling layer includes: a barrier layer covering the isolation layer; a seed layer covering the barrier layer; and an electroplated layer covering the seed layer and filling the via.

[0021] Optionally, the first surface of the substrate is further provided with an insulating layer and a top silicon layer, the through-silicon via structure penetrates the insulating layer and the top silicon layer, and the device is formed on the top silicon layer.

[0022] The advantage of this invention is that it can naturally form a closed structure by using a laser focusing method when forming the void structure, so as to maintain the design pattern of the void structure, thereby ensuring the stress release effect of the through-silicon via structure, increasing the area of ​​the region around the through-silicon via structure that is not affected by internal stress, thereby increasing the number of transistors and improving the performance of the semiconductor structure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the steps in the manufacturing method of the semiconductor structure provided in the first embodiment of the present invention;

[0025] Figures 2A to 2G This is a schematic cross-sectional view of the semiconductor structure prepared by the manufacturing method provided in the first embodiment of the present invention;

[0026] Figure 3A This is a cross-sectional schematic diagram of the semiconductor structure after the device is formed by the manufacturing method provided in the second embodiment of the present invention;

[0027] Figure 3B yes Figure 3A A top view of the semiconductor structure;

[0028] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the device is formed by the manufacturing method provided in the third embodiment of the present invention;

[0029] Figure 5A This is a cross-sectional schematic diagram of the semiconductor structure provided in the fourth embodiment of the present invention;

[0030] Figure 5B For is Figure 5A A top view of the semiconductor structure shown. Detailed Implementation

[0031] To make the objectives, technical means, and effects of this application clearer, the following description, in conjunction with the accompanying drawings, will further illustrate this application. It should be understood that the embodiments described herein are merely some embodiments of this application, not all embodiments, and are not intended to limit this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] Figure 1 This is a schematic diagram illustrating the steps of a semiconductor structure manufacturing method provided in the first embodiment of the present invention. Please refer to [link / reference]. Figure 1 The manufacturing method includes the following steps: Step S10, providing a substrate wafer having a first surface and a second surface disposed opposite to each other, the first surface of the substrate wafer having a via extending into the interior of the substrate wafer; Step S11, forming a void structure in the substrate wafer using a laser focusing method; Step S12, forming a through-silicon via structure in the via, at least a portion of the sides of the through-silicon via structure being surrounded by the void structure; Step S13, fabricating a device on the first surface of the substrate wafer.

[0033] Figures 2A to 2G This is a schematic cross-sectional view of the semiconductor structure prepared by the manufacturing method provided in the first embodiment of the present invention.

[0034] Please refer to step S10 and Figure 2A A substrate wafer 200 is provided, the substrate wafer 200 having a first surface 200A and a second surface 200B disposed opposite to each other, the first surface 200A of the substrate wafer having a via 201 extending into the interior of the substrate wafer 200.

[0035] exist Figure 2A Only one via 201 is schematically shown. In practice, the first surface 200A of the substrate wafer 200 may have multiple vias 201, which are arranged according to a predetermined pattern. In this step, the via 201 extends into the interior of the substrate wafer 200, but does not penetrate the substrate wafer 200, so as to provide a basis for the subsequent formation of a through-silicon via (TSV) structure.

[0036] Please refer to step S11 and Figure 2B A void structure 210 is formed within the substrate wafer 200 using a laser focusing method.

[0037] In this step, the depth of the void structure 210 in the substrate wafer 200 is less than the depth of the via 201 extending into the substrate wafer 200, such that at least a portion of the sidewalls of the via 201 are surrounded by the void structure 210.

[0038] In this step, a laser is used as an energy source, which can be focused at a set position inside the substrate wafer 200 to generate high temperature, thereby decomposing and evaporating the substrate wafer at the set position to form a void structure 210.

[0039] Furthermore, in order to avoid the laser affecting the first surface 200 of the substrate 200 and thus affecting the performance of the subsequently formed device, in this embodiment, a laser focusing method is used to act on the second surface 200B of the substrate wafer 200 to form the void structure 210 within the substrate wafer 200.

[0040] Furthermore, the void structure 210 is a closed structure and is located at a predetermined distance from the first surface 200A of the substrate wafer 200. That is, the void structure 210 is naturally formed during its formation, eliminating the need for additional sealing operations. In semiconductor manufacturing processes, if the void structure 210 has an opening during its formation, an insulating layer needs to be deposited using processes such as chemical vapor deposition to seal the opening. This deposited insulating layer would extend into the void structure 210, causing the pattern of the void structure 210 to deviate from its original design, reducing the stress relief effect of the subsequently formed through-silicon via (TSV) structure. However, the manufacturing method of this invention forms a naturally closed structure during the formation of the void structure 210, eliminating the possibility of an insulating layer extending into the void structure 210. This maintains the original design pattern of the void structure 210, preventing its destruction and ensuring the stress relief effect of the subsequently formed TSV structure, thus improving the performance of the semiconductor structure.

[0041] Furthermore, the depth of the void structure 210 inside the substrate wafer 200 (i.e., adjusting the set distance between the void structure 210 and the first surface 200A of the substrate wafer 200) and the lateral and longitudinal dimensions of the void structure 210 can be adjusted by adjusting the energy level, focal position and other related parameters of the laser.

[0042] Please see Figure 2C ,in, Figure 2C For along Figure 2BThe diagram shows a top view of the plane containing the AA line of the semiconductor structure. The gap structure 210 is a closed structure surrounding the via 201, such as a closed ring structure, to effectively prevent the propagation of internal stress generated during the contraction / expansion of the silicon via structure to surrounding devices. Further details can be found in the following sections. Figure 2B In the direction perpendicular to the substrate wafer 200 (as shown by the Y direction in the figure), the cross-section of the annular structure is elliptical.

[0043] Please refer to step S12 and Figures 2D to 2F A through-silicon via (TSV) structure 220 is formed within the via 201, and at least a portion of the sides of the TSV structure 220 are surrounded by the void structure 210.

[0044] After this step, the through-silicon via (TSV) structure 220 penetrates the substrate wafer 200. In this step, the TSV structure 220 is formed within the via 201 such that at least a portion of the sides of the TSV structure 220 are surrounded by the void structure 210.

[0045] This embodiment provides a method for forming the through-silicon via structure 220. The method includes the following steps:

[0046] Please see Figure 2D ,exist Figure 2B Based on the semiconductor structure shown, an isolation layer 221 is formed within the via 201, the isolation layer 221 covering the inner wall of the via 201 and the first surface of the substrate wafer 200. In this step, the isolation layer 221 can be formed using processes such as chemical vapor deposition. The isolation layer 221 can be an insulating layer, for example, silicon oxide or silicon nitride.

[0047] Please see Figure 2E A conductive filling layer is formed, which fills the via 201.

[0048] The conductive filling layer includes a barrier layer 222, a seed layer 223, and an electroplated layer 224 disposed within the via 201.

[0049] Further, in this step, the method for forming the conductive filling layer may include the following steps: forming a barrier layer 222, the barrier layer 222 covering the isolation layer 221; forming a seed layer 223, the seed layer 223 covering the barrier layer 222; forming an electroplated layer 224 on the seed layer 223, the electroplated layer 224 filling the via 201. In actual processes, the formed barrier layer 222, seed layer 223, and electroplated layer 224, in addition to filling the via 201, also cover the first surface of the substrate wafer 200. Therefore, after the above steps, the method further includes removing the barrier layer, seed layer, and electroplated layer corresponding to the first surface of the substrate wafer 200, retaining only the barrier layer 222, seed layer 223, and electroplated layer 224 located within the via 201 to form the conductive filling layer.

[0050] Furthermore, the barrier layer 222 is made of a material containing tantalum or titanium, and the seed layer 223 and the electroplating layer 224 are made of a material containing copper or tungsten.

[0051] Please see Figure 2F A portion of the substrate wafer 200 is removed from its lower surface to expose the bottom of the conductive filling layer, forming the through-silicon via (TSV) structure 220. In this step, a grinding process is used to remove a portion of the substrate wafer 200 from its lower surface. After the bottom of the conductive filling layer is exposed, the bottoms of the barrier layer 222, seed layer 223, and electroplated layer 224 are also removed, forming a TSV structure 220 composed of an insulating layer 221, a barrier layer 222, a seed layer 223, and an electroplated layer 224 arranged sequentially in a horizontal direction. The TSV structure 220 is used for subsequent electrical connections with other semiconductor structures.

[0052] Please refer to step S13 and Figure 2G A device 230 is fabricated on the first surface 200A of the substrate wafer 200. The device 230 may be a MOS transistor or the like.

[0053] Furthermore, the device 230 can be disposed directly opposite the gap structure 210, or it can be disposed on one side of the gap structure 210 and away from the through-silicon via structure 220. As shown in the figure, in this embodiment, the device 230 is disposed on one side of the gap structure 210 and away from the through-silicon via structure 220.

[0054] The semiconductor structure manufacturing method of the present invention can naturally form a closed structure when forming the gap structure 210 to maintain the design pattern of the gap structure 210, thereby ensuring the stress release effect of the through-silicon via structure 220, increasing the area of ​​the region around the through-silicon via structure 220 that is not affected by internal stress, thereby increasing the number of transistors and improving the performance of the semiconductor structure.

[0055] In the first embodiment, the void structure 210 is a single-layer structure, while in other embodiments of the present invention, the void structure 201 may also be a multi-layer structure. For example, multiple rings arranged sequentially. Figure 3A and Figure 3B As shown, Figure 3A This is a cross-sectional schematic diagram of the semiconductor structure after the device 230 is formed by the manufacturing method provided in the second embodiment of the present invention. Figure 3B for Figure 3A A top-down view, in which... Figure 3B In the second embodiment, the void structure 2210 and the device 230 are obscured and are therefore shown as dashed lines. In the second embodiment, the void structure 2210 is a multi-layered structure, consisting of multiple sequentially arranged concentric rings, with the through-silicon via (TSV) structure 220 located at the center of each ring. Only three rings are schematically shown in this embodiment; in other embodiments of the invention, the number of rings can be adjusted according to actual needs. In the second embodiment, the second surface 200B of the substrate wafer 200 can be repeatedly treated with a laser focusing method to form a multi-layered void structure 210 within the substrate wafer 200.

[0056] Furthermore, in the second embodiment, the device 230 is disposed above the gap structure 210, which can reduce the impact of stress while increasing the number of devices 230 that can be placed and improving the integration of the semiconductor structure.

[0057] In the first embodiment, the device 230 is directly formed on the first surface 200A of the substrate wafer 200. However, in other embodiments of the present invention, the device 230 is not directly disposed on the first surface 200A of the substrate wafer 200. For example, please refer to... Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after device 230 is formed by the manufacturing method provided in the third embodiment of the present invention. In the third embodiment of the present invention, an insulating layer 202 and a top silicon layer 203 are disposed on the first surface 200A of the substrate wafer 200. The via 201 penetrates the insulating layer 202 and the top silicon layer 203. In the step of fabricating the device on the first surface 200A of the substrate wafer 200, the device 230 is formed in the top silicon layer 203. Since the device 230 is formed on the insulating layer 202, the parasitic capacitance can be greatly reduced, the leakage current of the device 230 can be reduced, and the performance of the semiconductor structure can be improved.

[0058] The present invention also provides a semiconductor structure manufactured using the above-described manufacturing method. Please refer to [link / reference]. Figure 5A and Figure 5B , Figure 5A This is a cross-sectional schematic diagram of the semiconductor structure provided in the fourth embodiment of the present invention. Figure 5B for Figure 5A The diagram shows a top view of the semiconductor structure, wherein... Figure 5B In the diagram, the void structure 510 and device 530 are obscured and are therefore shown as dashed lines. The semiconductor structure includes a substrate 500, device 530, and through-silicon via (TSV) structure 520.

[0059] The substrate 500 has a first surface 500A and a second surface 500B disposed opposite to each other, and a void structure 510 formed by laser focusing is disposed in the substrate 500.

[0060] exist Figure 5A and Figure 5B Only one void structure 510 is schematically shown. In actual semiconductor processes, the first surface 500A of the substrate 500 may have multiple void structures 510, and the multiple void structures 510 are arranged according to a predetermined pattern. Furthermore, the number of void structures 510 is the same as the number of through-silicon via structures 520.

[0061] The semiconductor structure of this invention uses a laser as an energy source, which can be focused at a predetermined position inside the substrate 500 to generate high temperatures, thereby decomposing and evaporating the substrate at that predetermined position to form a void structure 510. Furthermore, the depth of the void structure 510 inside the substrate 500 (i.e., adjusting the predetermined distance between the void structure 510 and the first surface 500A of the substrate 500) and the lateral and longitudinal dimensions of the void structure 510 can be adjusted by modifying parameters such as the laser's energy level and focal point position.

[0062] Furthermore, the void structure 510 is a closed structure and is located at a predetermined distance from the first surface 500A of the substrate 500. That is, the void structure 510 is naturally formed during its formation, eliminating the need for additional sealing. In semiconductor manufacturing processes, if the void structure 510 has an opening during its formation, an insulating layer needs to be deposited using processes such as chemical vapor deposition to seal the opening. This deposited insulating layer would extend into the void structure 510, causing the pattern of the void structure 510 to deviate from its original design, reducing the stress relief effect of the subsequently formed through-silicon via (TSV) structure. However, the manufacturing method of this invention forms a naturally closed structure during the formation of the void structure 510, preventing the insulating layer from extending into the void structure 510. This maintains the original design pattern of the void structure 510, avoids damage to the design pattern, ensures the stress relief effect of the subsequently formed TSV structure, and improves the performance of the semiconductor structure.

[0063] The void structure 510 is a closed structure surrounding the through hole 501, for example, a closed annular structure. Further details can be found in the following sections. Figure 5A In the direction perpendicular to the substrate 500 (e.g. Figure 5A In the Y direction, the cross-section of the annular structure is elliptical.

[0064] Furthermore, in this embodiment, the void structure 510 is a closed ring surrounding the through-silicon via structure 520, along the direction perpendicular to the substrate 500 (e.g., Figure 5A In the Y-direction, the annular cross-section is elliptical to effectively block the propagation of internal stress generated during the contraction / expansion of the through-silicon via (TSV) structure to surrounding devices. Furthermore, in this embodiment, the annular structure is coaxial with the TSV structure 520, thereby allowing the void structure 510 to be uniformly distributed around the TSV structure 520, further effectively blocking the propagation of internal stress generated during the contraction / expansion of the TSV structure 520 to surrounding devices.

[0065] Furthermore, in another embodiment of the present invention, please refer to... Figure 3A and Figure 3B The void structure (reference numeral 210 in the figure) is composed of multiple rings. These rings are concentric and arranged in an array along a direction perpendicular to and / or parallel to the substrate (reference numeral 200 in the figure). The through-silicon via (TSV) structure (reference numeral 220 in the figure) is coaxial with the multiple rings, allowing the void structure to be uniformly distributed around the TSV structure, further effectively preventing the propagation of internal stress generated during the contraction / expansion of the TSV structure to surrounding devices.

[0066] Furthermore, in this embodiment, the device 530 is disposed on the first surface 500A of the substrate 500. The device 530 may be a MOS transistor or the like. In other embodiments of the present invention, the device 230 is not directly disposed on the first surface 500A of the substrate 500. For example, please refer to... Figure 4 The substrate (reference numeral 200) has an insulating layer (reference numeral 202) and a top silicon layer (reference numeral 203) on its first surface (reference numeral 200A). A through-silicon via (reference numeral 220) penetrates both the insulating layer and the top silicon layer. The device (reference numeral 230) is formed within the top silicon layer. Because the device 230 is formed on the insulating layer, parasitic capacitance is significantly reduced, leakage current is decreased, and the performance of the semiconductor structure is improved.

[0067] Furthermore, in the direction perpendicular to the substrate 500 (e.g.) Figure 5AIn the Y direction, the device 530 is offset from the gap structure 510, that is, the device 530 is disposed on one side of the gap structure 510. However, in other embodiments of the present invention, the device 530 may also be disposed correspondingly to the gap structure 510. For example, please refer to... Figure 3A and Figure 3B In the direction perpendicular to the substrate (refer to reference numeral 200 in the figure) (e.g.) Figure 3A In the Y direction, the device (reference number 230 in the figure) is arranged correspondingly to the gap structure (reference number 210 in the figure), which can increase the number of devices that can be placed while reducing the influence of stress and improving the integration of the semiconductor structure.

[0068] Further, the through-silicon via (TSV) structure 520 includes a via 501, an isolation layer 521, and a conductive filling layer. The via 501 penetrates the substrate 500. The isolation layer 521 covers the inner wall of the via 501, the first surface 500A of the substrate 500, and the device 530. The isolation layer 521 may be an insulating layer, such as a silicon oxide layer or a silicon nitride layer. The conductive filling layer fills the via 501. Optionally, the conductive filling layer includes a barrier layer 522, a seed layer 523, and an electroplated layer 524. The barrier layer 522 covers the isolation layer 521 and may be made of a material containing tantalum or titanium; the seed layer 523 covers the barrier layer 522, and the electroplated layer 524 covers the seed layer 523 and fills the via 501; the seed layer 523 and the electroplated layer 524 may be made of a material containing copper or tungsten.

[0069] The semiconductor structure of this invention utilizes laser focusing to form a gap structure, which allows the gap structure to close naturally and maintain the design pattern of the gap structure. This ensures the stress release effect of the through-silicon via (TSV) structure, increases the area of ​​the region around the TSV structure that is not affected by internal stress, thereby increasing the number of transistors and improving the performance of the semiconductor structure.

[0070] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate wafer is provided, the substrate wafer having a first surface and a second surface disposed opposite to each other, the first surface of the substrate wafer having a via extending into the interior of the substrate wafer; A void structure is formed in the substrate wafer using a laser focusing method, and the distance between the void structure and the first surface of the substrate wafer is adjusted by adjusting the laser parameters. A through-silicon via structure is formed within the via, and at least a portion of the sides of the through-silicon via structure are surrounded by the void structure. Devices are fabricated on the first surface of the substrate wafer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming a void structure in the substrate wafer using a laser focusing method further includes: applying a laser focusing method to the substrate wafer once or multiple times from the second surface of the substrate wafer to form one or more void structures in the substrate wafer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The void structure is a closed structure and is located at a predetermined distance from the first surface of the substrate wafer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming a through-silicon via structure within the via, wherein at least a portion of the sides of the through-silicon via structure are surrounded by the void structure, further includes: An isolation layer is formed within the via, the isolation layer covering the inner wall of the via and the first surface of the substrate wafer; A conductive filler layer is formed, which fills the via. A portion of the substrate wafer is removed from its second surface to expose the bottom of the conductive fill layer, forming the through-silicon via (TSV) structure.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The step of forming a conductive fill layer, wherein the conductive fill layer fills the via, further includes: A barrier layer is formed, which covers the isolation layer; A seed layer is formed, which covers the barrier layer; An electroplated layer is formed on the seed layer, and the electroplated layer fills the via.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The step of forming an electroplated layer on the seed layer and filling the via with the electroplated layer further includes: Remove the barrier layer, seed layer and electroplating layer corresponding to the first surface of the substrate wafer, and retain only the barrier layer, seed layer and electroplating layer located in the via.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, An insulating layer and a top silicon layer are disposed on the first surface of the substrate wafer. The via penetrates the insulating layer and the top silicon layer. In the step of fabricating a device on the first surface of the substrate wafer, the device is formed in the top silicon layer.

8. A semiconductor structure, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other, and a void structure formed by laser focusing is disposed in the substrate, wherein a set distance between the void structure and the first surface of the substrate is adjusted by adjusting the parameters of the laser. The device is disposed on the first surface of the substrate; A through-silicon via (TSV) structure extends through the substrate, and at least a portion of the sides of the TSV structure are surrounded by the void structure.

9. The semiconductor structure according to claim 8, characterized in that, The void structure is a ring surrounding the through-silicon via structure, and the cross-section of the ring is elliptical in the direction perpendicular to the substrate.

10. The semiconductor structure according to claim 8, characterized in that, The void structure is composed of multiple rings.

11. The semiconductor structure according to claim 10, characterized in that, Multiple rings are arranged in an array along a direction perpendicular to and / or parallel to the substrate.

12. The semiconductor structure according to claim 10, characterized in that, The through-silicon via structure is coaxial with the annulus.

13. The semiconductor structure according to claim 8, characterized in that, The device is positioned in a direction perpendicular to the substrate, corresponding to the void structure.

14. The semiconductor structure according to claim 8, characterized in that, The device is misaligned with the void structure in a direction perpendicular to the substrate.

15. The semiconductor structure according to claim 8, characterized in that, The through-silicon via structure includes: Through-holes penetrate the substrate; An isolation layer covers the inner wall of the via, the first surface of the substrate, and the device; A conductive filler layer fills the via.

16. The semiconductor structure according to claim 15, characterized in that, The conductive filling layer includes: A barrier layer, covering the isolation layer; Seed layer, covering the barrier layer; An electroplated layer covers the seed layer and fills the via.

17. The semiconductor structure according to claim 8, characterized in that, The first surface of the substrate is further provided with an insulating layer and a top silicon layer, the through-silicon via structure penetrates the insulating layer and the top silicon layer, and the device is formed on the top silicon layer.

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