Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a device region and an isolation region, an etching stop layer being formed in the substrate of the isolation region, the etching stop layer being buried in the substrate; performing a patterning process on the substrate higher than the top of the etching stop layer, forming a fin standing on the remaining substrate in the device region and the isolation region, the remaining substrate after the patterning process serving as a substrate, the top surface of the substrate being flush with the top surface of the etching stop layer; removing the fin in the isolation region with the top of the etching stop layer as a stop position. The etching stop layer can protect the top of the substrate in the isolation region, reducing the probability of damage to the top of the substrate in the isolation region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices.

[0004] In the semiconductor industry, depending on process requirements, it is often necessary to remove parts of the fins (e.g., pseudo-fins). One current approach is to remove these parts using a fin-cutting process. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a device region and an isolation region; a doped layer located in the substrate within the isolation region, wherein the top surface of the doped layer is flush with the top surface of the substrate; a fin protruding from the substrate in the device region and exposing the top of the doped layer; an opening located in the isolation region and the device region, the opening being formed by the sidewalls of the fin and the top of the substrate, and by the top of the substrate, the top of the doped layer, and the sidewalls of the fin; and an isolation dielectric layer located in the opening, wherein the isolation dielectric layer covers a portion of the sidewalls of the fin.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a device region and an isolation region, wherein an etch stop layer is formed in the substrate in the isolation region, the etch stop layer being buried in the substrate; patterning the substrate above the top of the etch stop layer to form fins protruding from the remaining substrate in the device region and the isolation region, the patterned remaining substrate serving as a substrate, the top surface of the substrate being flush with the top surface of the etch stop layer; and removing the fins in the isolation region with the top of the etch stop layer as the stop position.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a method for forming a semiconductor structure. An etch stop layer is formed in the substrate of an isolation region, and the etch stop layer is buried within the substrate. The substrate above the top of the etch stop layer is patterned, forming fins protruding from the remaining substrate in the device region and the isolation region. The patterned remaining substrate serves as a substrate, with its top surface flush with the top surface of the etch stop layer. The fins in the isolation region are removed using the top of the etch stop layer as the stop position. During the removal of the fins in the isolation region, the top of the etch stop layer defines the etch stop position, thus protecting the top of the substrate in the isolation region and reducing the probability of damage to the top of the substrate. Consequently, the probability of fin breakage in the device region is reduced. Furthermore, it helps ensure complete removal of the fins in the isolation region, thereby reducing the risk of short circuits between conductive plugs formed in subsequent processes, and ultimately improving the performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1-2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 4-17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one semiconductor structure formation method as an example.

[0014] Figures 1-2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a device region 10A and an isolation region 10B, a fin 19 protruding on the substrate 10, and a fin mask layer 18 formed on the top of the fin 19.

[0016] refer to Figure 2 Remove the fin 19 on the isolation zone 10B.

[0017] Research has revealed that, taking the direction perpendicular to the extension direction of the fin 19 as the lateral direction, the lateral dimensions of the isolation area 10B are inconsistent, resulting in different pattern densities of the fin 19 in each region.

[0018] Correspondingly, due to the influence of the etching process window size and etching rate, during the etching process of removing the fins 19 of the isolation region 10B, if the etching amount is too large, the top of the substrate 10 in the isolation region 10B is easily damaged. Consequently, this increases the probability of the fins 19 in the device region 10A breaking. Alternatively, if the etching amount is insufficient, the remaining part of the fins 19 is not completely removed, thereby increasing the risk of short circuits between conductive plugs formed in subsequent processes. All of the above problems reduce the performance of the semiconductor structure.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a device region and an isolation region, wherein an etch stop layer is formed in the substrate within the isolation region, the etch stop layer being buried in the substrate; patterning the substrate above the top of the etch stop layer to form fins protruding from the remaining substrate in the device region and the isolation region, the patterned remaining substrate serving as a substrate, the top surface of the substrate being flush with the top surface of the etch stop layer; and removing the fins in the isolation region at the top of the etch stop layer as a stop position.

[0020] In the solution disclosed in the embodiments of the present invention, during the process of removing the fins in the isolation region, the top of the etching stop layer can define the etching stop position, which can protect the top of the substrate in the isolation region, reduce the probability of damage to the top of the substrate in the isolation region, and correspondingly reduce the probability of fin breakage in the device region. At the same time, it is beneficial to ensure that the fins in the isolation region are completely removed, thereby reducing the risk of short circuits between conductive plugs formed in subsequent processes, thereby improving the performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0023] The semiconductor structure includes: a substrate 260, which includes a device region 200A and an isolation region 200B; a doped layer 206 located in the isolation region 200B of the substrate 260, with the top surface of the doped layer 206 flush with the top surface of the substrate 260; a fin 219 protruding from the device region 200A of the substrate 260 and exposing the top of the doped layer 206; an opening (not shown) located in the isolation region 200B and the device region 200A, the opening being formed by the sidewall of the fin 219 and the top of the substrate 260, and by the top of the substrate 260, the top of the doped layer 206, and the sidewall of the fin 219; and an isolation dielectric layer 270 located in the opening, the isolation dielectric layer 270 covering a portion of the sidewall of the fin 219.

[0024] In this embodiment, by forming a doped layer 206 in the substrate 260 in the isolation region 200B, the doped layer 206 can protect the top of the substrate in the isolation region 200B during the semiconductor structure formation process of removing the fins 219 in the isolation region 200B. This reduces the probability of the fins 219 in the device region 200A breaking. At the same time, it helps to ensure that the fins 219 in the isolation region 200B are completely removed, thereby reducing the risk of short circuits between conductive plugs formed by the semiconductor manufacturing process, and thus improving the performance of the semiconductor structure.

[0025] The substrate 260 includes a device region 200A and an isolation region 200B. The device region 200A is the working area of ​​the semiconductor device, and the isolation region 200B is used to isolate adjacent semiconductor devices.

[0026] The substrate 160 is made of one or more of Si, SiGe, and SiC. In this embodiment, the substrate 260 is a silicon substrate.

[0027] The doped layer 206 protects the top of the substrate 260 in the isolation region 200B, reducing the probability of damage to the top of the substrate 260 in the isolation region 200B.

[0028] It should be noted that the thickness of the doped layer 206 should not be too large or too small. If the thickness of the doped layer 206 is too large, it will generate significant stress on the substrate 260 in the device region 200A, thereby affecting the performance of the semiconductor structure. If the thickness of the doped layer 206 is too small, it will easily reduce the protective effect of the doped layer 206 on the top of the substrate 260 in the isolation region 200B, increasing the probability of damage to the substrate 260 in the isolation region 200B, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the doped layer 206 is 100 angstroms to 600 angstroms.

[0029] There is an etching selectivity between the materials of the fin 219 and the doped layer 206, so that the top of the doped layer 206 can define the etching stop position during the etching process of removing the fin 219 in the isolation region 200B.

[0030] In this embodiment, the material of the doped layer 206 is one or more of boron-doped silicon, carbon-doped silicon, phosphorus-doped silicon, and arsenic-doped silicon.

[0031] It should be noted that, compared with fin 219, boron-doped silicon, carbon-doped silicon, phosphorus-doped silicon, and arsenic-doped silicon have lower etching rates.

[0032] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the discrete fins 219 on the substrate 260 are used to provide the channel of the fin field-effect transistor.

[0033] Therefore, in this embodiment, the material of the fin 219 is the same as the material of the substrate 260, and the material of the fin 260 is silicon. In other embodiments, the material of the fin may also be one or more of semiconductor materials suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium phosphate, and the material of the fin may also be different from the material of the substrate.

[0034] The opening provides space for the isolation medium layer 270.

[0035] The isolation dielectric layer 270 is used to isolate adjacent devices. The material of the isolation dielectric layer 270 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the isolation dielectric layer 270 is silicon oxide.

[0036] Figures 4-17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0037] refer to Figures 4-7 A substrate is provided, the substrate including a device region 100A and an isolation region 100B, wherein an etch stop layer 106 is formed in the substrate in the isolation region 100B, and the etch stop layer 106 is buried in the substrate.

[0038] The substrate provides a process platform for subsequent process manufacturing.

[0039] Specifically, the base is used to form the fin.

[0040] The substrate includes a device region 100A and an isolation region 100B. The device region 100A is the working area of ​​the semiconductor device, and the isolation region 100B is used to isolate adjacent semiconductor devices.

[0041] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0042] The etching rate of the etching stop layer 106 is less than that of the substrate. Accordingly, during the subsequent removal of the fin portion of the isolation region 100B, the top of the etching stop layer 106 can define the position where the etching stops.

[0043] In this embodiment, the etching stop layer 106 being buried in the substrate means that the etching stop layer 106 is located in the substrate, and the top of the etching stop layer 106 is at a predetermined distance H from the top of the substrate.

[0044] Specifically, the top of the etch stop layer 106 is spaced at a predetermined distance H from the top of the substrate. This predetermined distance H should not be too large or too small. Subsequently, the substrate above the top of the etch stop layer 106 is patterned to form fins. If the predetermined distance H is too large, the etching depth may be too large during the subsequent fin formation process, easily reducing the etching effect. This, in turn, may lead to an excessively large aspect ratio between the subsequently formed fins, affecting the filling effect of subsequent film layers and thus the performance of the semiconductor structure. If the predetermined distance H is too small, the effective height of the subsequently formed fins may be too small, affecting the carrier mobility in the fins and thus the performance of the semiconductor structure. Therefore, in this embodiment, the predetermined distance H from the top of the etch stop layer 106 to the top of the substrate is 900 angstroms to 1300 angstroms.

[0045] In this embodiment, the top of the etching stop layer 106 and the top of the substrate have a preset distance H equal to the preset height of the fin.

[0046] It should be noted that the thickness of the etch stop layer 106 should not be too large or too small. If the thickness of the etch stop layer 106 is too large, it will generate significant stress on the substrate subsequently formed in the device region 100A, thereby affecting the performance of the semiconductor structure. If the thickness of the etch stop layer 106 is too small, it will easily reduce the protective effect of the etch stop layer 106 on the top of the substrate 160 in the isolation region 100B, increasing the probability of damage to the substrate 160 in the isolation region 100B, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the etch stop layer 106 is 100 angstroms to 600 angstroms.

[0047] In this embodiment, the step of providing the substrate includes: as follows Figure 4 As shown, a first substrate 100 is provided, the first substrate 100 including a device region 100A and an isolation region 100B; as Figures 5-6 As shown, an etch stop layer 106 is formed in the first substrate 100 of the isolation region 100B; as Figure 7 As shown, after the etching stop layer 106 is formed, a second substrate 107 is formed on top of the etching stop layer 106 and the first substrate 100, and the second substrate 107 and the first substrate 100 constitute a substrate.

[0048] Specifically, by first forming an etch stop layer 106 in the first substrate 100, and then forming a second substrate 107 on top of the etch stop layer 106 and the first substrate 100, it is easier to precisely control the thickness and position of the etch stop layer 106 in the substrate, thus reducing the process difficulty. Furthermore, it avoids the process of forming the etch stop layer 106 affecting the second substrate 107, which helps ensure the quality of the second substrate 107.

[0049] The material of the first substrate includes one or more of Si, SiGe, and SiC. In this embodiment, the material of the first substrate is silicon (Si).

[0050] In this embodiment, the step of forming an etch stop layer 106 in the first substrate 100 of the isolation region 100B includes: performing a surface modification treatment on the first substrate 100 of the isolation region 100B to transform a portion of the thickness of the first substrate 100 into an etch stop layer 106.

[0051] By performing surface modification treatment on the first substrate 100, the process steps for forming the etch stop layer 106 are simplified.

[0052] refer to Figures 5-6 The step of performing surface modification treatment on the top of the first substrate 100 of the isolation region 100B includes: forming a mask layer 104 with a mask opening 105 on the top of the first substrate 100, the mask opening 105 being located on the top of the first substrate 100 of the isolation region 100B; and performing doping treatment on the top of the first substrate 100 exposed by the mask opening 105 using the mask layer 104 as a mask.

[0053] By doping the top of the first substrate 100 in the isolation region 100B, an etch selectivity ratio is created between the ion-doped first substrate 100 in the isolation region 100B and the first substrate 100 in the device region 100A. In the isolation region 100B, the ion-doped first substrate 100 serves as an etch stop layer 106.

[0054] In this embodiment, the step of doping the first substrate 100 of the isolation region 100B includes one or more of N, Ge, P, B and As.

[0055] After the N, Ge, P, B and As ions are used to dope the first substrate 100 of the isolation region 100B, the etching rate of the first substrate 100 doped with ions is reduced, and the performance of the first substrate 100 is less affected.

[0056] In this embodiment, the doping process includes ion implantation.

[0057] The ion implantation process is a process of implanting ions accelerated to a certain high energy into the surface layer of a solid material to change the physical and chemical properties of the surface layer. It has the characteristics of high efficiency and strong modified layer. The first substrate 100 of the isolation region 100B is doped, which changes the etching rate of the first substrate 100 of the isolation region 100B.

[0058] It should be noted that the implantation dose should not be too large or too small. If the implantation dose is too large, the ion implantation range will be too large, making the process difficult to control, and consequently, the depth of the etch stop layer 106 will be too large. If the implantation dose is too small, the ion implantation reaction time will be too long, reducing the efficiency of the process and affecting the depth of the etch stop layer 106, failing to achieve the desired process effect. Furthermore, the etch stop layer 106 and the first substrate 100 may have similar etching rates, increasing the probability of damage to the first substrate 100 in the isolation region 100B during subsequent removal of the fins in the isolation region 100B. Therefore, in this embodiment, the implantation dose range is 10E15 atom / cm². 3 Up to 10E21atom / cm 3 .

[0059] It should also be noted that the implantation energy should not be too high or too low. If the implantation energy is too high, the ion implantation range will be too large, making the process difficult to control, and consequently, the depth of the etch stop layer 106 will be too large. If the implantation energy is too low, the ion implantation reaction time will be too long, reducing the efficiency of the process and affecting the depth of the etch stop layer 106, thus failing to achieve the desired process effect. Therefore, in this embodiment, the implantation energy ranges from 1 keV to 600 keV.

[0060] Continue to refer to Figure 5 In this embodiment, the mask layer 104 includes a first organic material layer 103, a first anti-reflective coating 102 located on the first organic material layer 103, and a first photoresist layer 101 located on the first anti-reflective coating 102.

[0061] The first organic material layer 103 is made of organic materials. In this embodiment, the material of the first organic material layer 103 is spin-on carbon (SOC). In other embodiments, the material of the first organic material layer may also be other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0062] The material of the first anti-reflective coating 102 includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0063] In this embodiment, during the formation of the mask layer 104, the first photoresist layer 101 is used as a mask to sequentially etch the first anti-reflective coating 102 and the organic material layer 103.

[0064] In this embodiment, after forming an etch stop layer 106 in the first substrate 100 of the isolation region 100B, the method further includes removing the remaining mask layer 104.

[0065] The second substrate 107 provides the technological basis for the subsequent formation of the fin.

[0066] In this embodiment, the process of forming the second substrate 107 on top of the etch stop layer 106 and the first substrate 100 includes an epitaxial process.

[0067] The epitaxial process is characterized by low cost and simple process, can grow in specific regions and has regional selectivity, and the formation quality of the second substrate 107 is high.

[0068] It should be noted that after the second substrate 107 is formed, it can also be planarized using a planarization process. When the epitaxial growth rate of the material of the second substrate 107 on the first substrate 100 and the etch stop layer 106 is inconsistent, planarization helps to make the top surface of the second substrate 107 have a higher flatness, thereby providing a good process foundation for the subsequent formation of fins.

[0069] The thickness of the second substrate 107 should not be too large or too small. If the thickness of the second substrate 107 is too large, the etching depth may be too large during the subsequent formation of the fins, which may reduce the etching effect and lead to an excessive aspect ratio between the subsequently formed fins, thus affecting the filling effect of each film layer in the semiconductor formation process and consequently affecting the performance of the semiconductor structure. If the thickness of the second substrate 107 is too small, the effective height of the subsequently formed fins may be too low, which may affect the carrier mobility in the fins and consequently affect the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the second substrate 107 is 900 angstroms to 1300 angstroms.

[0070] refer to Figures 8-16 The substrate above the top of the etch stop layer 106 is patterned to form fins 119 protruding from the remaining substrate in the device region 100A and the isolation region 100B. The patterned remaining substrate serves as a substrate 160, and the top surface of the substrate 160 is flush with the top surface of the etch stop layer 106.

[0071] The fin 119 formed in the device region 100A is used to provide a channel for the transistor formed in the device region 100A.

[0072] In this embodiment, fins 119 protruding from the remaining substrate are formed in both the device region 100A and the isolation region 100B, thereby improving the width uniformity and morphological quality of the fins 119.

[0073] Reference Figures 8-16 The steps for patterning the substrate above the top of the etch stop layer are described in detail.

[0074] refer to Figures 8-15 Using a self-aligned dual patterning process, discrete fin mask layers 118 are formed on top of the substrate.

[0075] The fin mask layer 118 serves as an etching mask for subsequent etching of the second substrate 107.

[0076] Specifically, the step of forming discrete fin mask layers 118 on top of the substrate includes: as follows Figure 8 As shown, a fin masking material layer 108 is formed on top of the substrate; a bottom core material layer 109 is formed on top of the fin masking material layer 108; and a top core material layer 110 is formed on top of the bottom core material layer 109; as shown Figure 9 As shown, the top core material layer 110 is graphically represented, forming a discrete top core layer 111; as Figure 10As shown, a first sidewall layer 112 is formed on the sidewall of the top core layer 111; as Figure 11 As shown, the top core layer 111 is removed; as Figure 12 As shown, after removing the top core layer 111, the bottom core material layer 109 is patterned using the first sidewall layer 112 as a mask to form a bottom core layer 113 protruding from the top of the substrate; as Figure 13 As shown, a second sidewall layer 180 is formed on the sidewall of the bottom core layer 113; as Figure 14 As shown, the bottom core layer 113 is removed; as Figure 15 As shown, after removing the bottom core layer 113, the fin mask material layer 108 is patterned using the second sidewall layer 180 as a mask to form a discrete fin mask layer 118.

[0077] In this embodiment, the discrete fin mask layer 118 is formed using a self-aligned dual patterning process, which makes the pattern density of the fin mask layer 118 higher and the pattern conversion more accurate. While meeting the process requirements, it can also overcome the constraints of the lithography equipment.

[0078] refer to Figure 16 Using the fin mask layer 118 as a mask, the substrate above the top of the etch stop layer 106 is patterned, and fins 119 protruding from the remaining substrate are formed in the device region 100A and the isolation region 100B. The patterned remaining substrate serves as a substrate 160.

[0079] In this embodiment, the first substrate 100 is made of silicon, and correspondingly, the substrate 160 is a silicon substrate. In other embodiments, the substrate 160 may also be made of one or both of SiGe and SiC.

[0080] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the discrete fins 119 on the substrate 160 are used to provide the channel of the fin field-effect transistor.

[0081] In this embodiment, the material of the fin 119 is the same as the material of the substrate 160, and the material of the fin 160 is silicon. In other embodiments, the material of the fin may also be one or more of semiconductor materials suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium phosphate, and the material of the fin may also be different from the material of the substrate.

[0082] Continue to refer to Figure 16It should be noted that after the fin 119 and the substrate 160 are formed, a fin mask layer 118 is retained on top of the fin 119. The fin mask layer 118 protects the top of the fin 119 in subsequent manufacturing processes.

[0083] refer to Figure 17 Using the top of the etching stop layer 106 as the stop position, the fin 119 in the isolation region 100B is removed.

[0084] Since the etching rate of the etch stop layer 106 is less than that of the substrate 160, the etch stop layer 106 can protect the top of the substrate 160 in the isolation region 100B during the removal of the fins 119 in the isolation region 100B, reducing the probability of damage to the top of the substrate 160 in the isolation region 100B. Correspondingly, it reduces the probability of the fins 119 in the device region 100A breaking. At the same time, it helps to ensure that all the fins 119 in the isolation region 100B are removed, thereby reducing the risk of short circuits between conductive plugs formed in subsequent processes, and thus improving the performance of the semiconductor structure.

[0085] In this embodiment, the process for removing the fin 119 in the isolation region 100B includes a dry etching process.

[0086] The dry etching process includes anisotropic dry etching. Because of its anisotropic nature, the longitudinal etching rate is much higher than the transverse etching rate, enabling precise removal of the fins 119 in the isolation region 100B while minimizing damage to other film layers.

[0087] It should be noted that after removing the fin 119 in the isolation region 100B, the subsequent process also includes: forming an isolation layer on the substrate 160, the isolation layer covering part of the sidewall of the fin 119 in the device region 100A.

[0088] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.

[0089] It should be noted that during the formation of the isolation layer, the fin mask layer 118 is removed.

[0090] The specific description of the isolation layer will not be repeated here.

[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate including a device region and an isolation region; A doped layer is located in the substrate of the isolation region, and the top surface of the doped layer is flush with the top surface of the substrate, and the material of the doped layer has an etching selectivity ratio with the material of the substrate; The fins protrude from the substrate of the device region and expose the top of the doped layer; An opening is located in the isolation region and the device region, the opening being formed by the sidewall of the fin and the top of the substrate, and by the top of the substrate, the top of the doped layer, and the sidewall of the fin; An isolation medium layer is located in the opening and covers part of the sidewall of the fin.

2. The semiconductor structure as described in claim 1, characterized in that, The materials of the doped layer include boron-doped silicon, carbon-doped silicon, phosphorus-doped silicon, and arsenic-doped silicon.

3. The semiconductor structure as described in claim 1, characterized in that, The thickness of the doped layer is from 100 angstroms to 600 angstroms.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of Si, SiGe, and SiC; The fin is made of one or more of Si, SiGe, and SiC.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the isolation dielectric layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a device region and an isolation region, an etch stop layer is formed in the substrate in the isolation region, the etch stop layer is buried in the substrate, and the material of the etch stop layer has an etch selectivity ratio with the material of the substrate; The substrate above the top of the etch stop layer is patterned to form fins protruding from the remaining substrate in the device region and isolation region. The patterned remaining substrate serves as a substrate, and the top surface of the substrate is flush with the top surface of the etch stop layer. The fin in the isolation zone is removed using the top of the etching stop layer as the stop position.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The step of providing the substrate includes: providing a first substrate, the first substrate including a device region and an isolation region; forming an etch stop layer in the first substrate in the isolation region; and after forming the etch stop layer, forming a second substrate on top of the etch stop layer and the first substrate, the second substrate and the first substrate constituting a substrate.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming an etch stop layer in the first substrate of the isolation region includes: performing a surface modification treatment on the first substrate of the isolation region to convert a portion of the thickness of the first substrate into an etch stop layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of performing surface modification treatment on the top of the first substrate of the isolation region includes: forming a mask layer with a mask opening on the top of the first substrate, the mask opening being located on the top of the first substrate of the isolation region; using the mask layer as a mask, performing doping treatment on the top of the first substrate exposed by the mask opening; and removing the mask layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The doping process includes ion implantation.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of doping the first substrate of the isolation region, the dopant ions include one or more of N, Ge, P, B and As.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The parameters of the ion implantation process include: a doping dose range of 10E15 atom / cm². 3 Up to 10E21atom / cm 3 The injection energy range is from 1 keV to 600 keV.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The top of the etching stop layer is at a predetermined distance from the top of the substrate, the predetermined distance being 900 angstroms to 1300 angstroms.

14. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness of the etching stop layer is 100 angstroms to 600 angstroms.

15. The method for forming a semiconductor structure as described in claim 6, characterized in that, The step of patterning the substrate above the top of the etch stop layer includes: forming discrete fin mask layers on top of the substrate using a self-aligned dual patterning process. Using the fin mask layer as a mask, the substrate above the top of the etch stop layer is patterned, and fins protruding from the remaining substrate are formed in the device region and the isolation region. The patterned remaining substrate serves as a substrate.

16. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for removing the fins from the isolation zone includes a dry etching process.

17. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process of forming a second substrate on top of the etch stop layer and the first substrate after forming the etch stop layer includes an epitaxial process.

18. The method for forming a semiconductor structure as described in claim 6, characterized in that, The substrate material includes one or more of Si, SiGe, and SiC; The fin is made of one or more of Si, SiGe, and SiC.

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