Frame unit marking pseudo-gate layout and its design method

Abstract

The application provides a frame unit mark pseudo-gate layout, which comprises a frame pattern, the frame pattern being a pattern of a remaining area in a single shot except a chip; the frame pattern is provided with a mark pattern, the mark pattern being used for defining a pattern on a substrate cutting path for alignment and measurement; the mark patterns have gaps therebetween, first pseudo-gate patterns are inserted between the mark patterns; second pseudo-gate patterns provided in the mark patterns, the second pseudo-gate patterns having different sizes according to different levels of the mark patterns; a dummy block mark layer provided on the mark patterns, the dummy block mark layer being used for defining an area in which the pseudo-gate is not formed. The original frame unit mark pseudo-gate layout is subjected to pseudo-gate pattern adding processing to achieve the purpose of measurement or alignment, and the problem of falling off of the register mark in the advanced technology node process is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a frame unit marking pseudo-gate layout and a design method thereof. Background Art

[0002] The self-aligned double patterning (SADP) process can achieve a smaller pitch (period) than photolithography can expose, doubling the pitch. This is limited to patterns with a large number of repeated unit layers.

[0003] In a frame layout, a frame cell mark is a graphic placed on the cutting path for alignment and measurement. Current processes do not add dummy gates to frame cells, but rather add them throughout the entire frame layout. This method only adds dummy gates within a very small number of frame cells and at certain levels. Currently, frame cells used in semiconductor fabrication plants (FABs) can fall off at more advanced technology nodes.

[0004] In order to solve the above problems, it is necessary to propose a new frame unit marking pseudo-gate layout and its design method. Summary of the Invention

[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a frame unit marking pseudo-gate layout and a design method thereof, which is used to solve the problem that the frame unit in the prior art does not add a pseudo gate, but adds a pseudo gate through the entire frame layout. At the same time, this method only adds pseudo gates inside a very small number of frame units and some layers. The frame units currently used in semiconductor factories will fall off at more advanced technology nodes.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a frame unit marking pseudo-gate layout, comprising:

[0007] A frame pattern, which is a pattern of the remaining area excluding the chip in a single shot;

[0008] A marking pattern is provided on the frame pattern, and the marking pattern is used to define a pattern for alignment and measurement on the substrate cutting path;

[0009] There are gaps between the mark patterns, and a first dummy gate pattern is inserted between the mark patterns;

[0010] The second dummy grid pattern is provided in the marking pattern, and the second dummy grid pattern has different sizes according to the marking patterns at different levels;

[0011] A dummy block marking layer is provided on the marking pattern, and the dummy block marking layer is used to define an area where a dummy gate is not formed.

[0012] Preferably, the region where the marking pattern is located includes the MOA layer and the back-end metal layer.

[0013] Preferably, the second dummy gate patterns are distributed in sequence and at equal intervals in the region of the marking pattern.

[0014] Preferably, the length of the second dummy gate in the MOA layer is 1.2 microns, the width is 0.038 microns, the period of two adjacent second dummy gates is 0.18 microns, and the period of two adjacent second dummy gates is 1.366 microns.

[0015] Preferably, the length and width of the second dummy gate in the back-end metal layer are both 0.8 micrometers, and the period of two second dummy gates adjacent to each other on the left and right and the period of two second dummy gates adjacent to each other on the top and bottom are both 0.8 micrometers.

[0016] The present invention also provides a method for designing a frame unit mark pseudo-grid layout, comprising:

[0017] Step 1: Provide a frame pattern, which is a pattern of the remaining area excluding the chip in a single shot;

[0018] A marking pattern is provided on the frame pattern, and the marking pattern is used to define a pattern for alignment and measurement on the substrate cutting path;

[0019] enlarging the gaps between the mark patterns according to the types of the mark patterns, and then inserting a first dummy gate pattern between the mark patterns;

[0020] Step 2: setting second dummy grid patterns of different sizes according to the marking patterns at different levels, wherein the second dummy grid patterns are used to be set within the marking patterns;

[0021] Step 3: indent each side of the marking pattern inward by a set value, and then add the second dummy grid pattern within the marking pattern;

[0022] Step 4: setting a dummy block marking layer according to the marking patterns at different levels, wherein the dummy block marking layer is used to define an area where a dummy gate is not formed.

[0023] Preferably, the region where the marking pattern is located in step one includes the MOA layer and the back-end metal layer.

[0024] Preferably, the second dummy gate pattern in step 1 is formed simultaneously with the frame pattern according to design rules of design software.

[0025] Preferably, in step 2, the second dummy gate patterns are distributed in sequence and at equal intervals in the region of the marking pattern.

[0026] Preferably, the length and width of the second dummy gate in the M0A layer in step two are 1.2 microns and 0.038 microns respectively, the period of two adjacent second dummy gates in the left and right direction is 0.18 microns, and the period of two adjacent second dummy gates in the up and down direction is 1.366 microns.

[0027] Preferably, the length and width of the second dummy gate in the back metal layer in step two are both 0.8 microns, and the period of two adjacent second dummy gates in the left and right direction and the period of two adjacent second dummy gates in the up and down direction are both 0.8 microns.

[0028] Preferably, the retracted value in step three is 5 to 20 microns.

[0029] As described above, the frame unit marking dummy gate layout and the design method thereof of the present application have the following beneficial effects:

[0030] The present application adds dummy gate patterns to the original frame unit marking dummy gate layout for the purpose of measurement or alignment, and solves the problem of missing registration marks in advanced technology nodes. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 An M0A dummy gate layout in a frame unit of the present application is shown;

[0032] Figure 2 A partial enlarged view of an M0A dummy gate layout in a frame unit of the present application is shown;

[0033] Figure 3 A back metal layer dummy gate layout of the present application is shown;

[0034] Figure 4 An overlaid view of dummy gate layouts of different layers in a frame unit of the present application is shown;

[0035] Figure 5 A gap view of different marking patterns in a frame unit of the present application is shown;

[0036] Figure 6 A design method of the present application is shown. DETAILED DESCRIPTION

[0037] The embodiments of the present application will be described in detail hereinafter with specific reference to the drawings. Other advantages and effects of the present application will be easily understood by those skilled in the art from the contents disclosed in the present specification. The present application can also be implemented or applied in other different embodiments, and the details in the present specification can be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0038] The present application provides a frame unit marking dummy gate layout, comprising:

[0039] The frame pattern is a pattern of a remaining area in a single shot (exposure point) except for a chip;

[0040] The frame pattern is provided with a mark pattern, and the mark pattern is used to define a pattern on a substrate cutting path for alignment and measurement.

[0041] In the embodiment of the present application, the area where the mark pattern is located includes an M0A layer and a back-end metal layer, and the M0A layer includes a metal 0 layer, a contact hole layer (V0), and a metal 1 layer (M1).

[0042] Please refer to Figure 5 , the mark patterns have gaps therebetween, the distance of the gap part is determined by the type of the mark pattern, which is not specifically limited here, and the first dummy gate pattern is inserted between the mark patterns, and the mark pattern and the first dummy gate pattern are usually added by design software at the same time.

[0043] The second dummy gate pattern provided in the mark pattern has different sizes according to different levels of the mark pattern.

[0044] In the embodiment of the present application, the second dummy gate pattern is distributed equidistantly in the area of the mark pattern, that is, equidistantly in the horizontal direction and the vertical direction.

[0045] In the embodiment of the present application, please refer to Figure 1 and Figure 2 , the length of the second dummy gate in the M0A layer is 1.2 microns, the width is 0.038 microns, the period of the two second dummy gates adjacent to each other on the left and right is 0.18 microns, and the period of the two second dummy gates adjacent to each other on the top and bottom is 1.366 microns.

[0046] In the embodiment of the present application, please refer to Figure 3 , the length and width of the second dummy gate in the back-end metal layer are both 0.8 microns, and the period of the two second dummy gates adjacent to each other on the left and right and the period of the two second dummy gates adjacent to each other on the top and bottom are both 0.8 microns.

[0047] In the embodiment of the present application, please refer to Figure 4 , which shows the case after superposition of the dummy gate patterns of different levels in the frame unit.

[0048] It should be noted that the length, width, period, and other parameters of the second dummy gate are determined by the production process, and can also be other values.

[0049] The dummy block mark layer provided on the mark pattern is used to define an area where the dummy gate is not formed.

[0050] In the embodiment of the present application, the layout is used for a process of a technology node of 7 nanometers and below.

[0051] See also Figure 6 The present invention also provides a method for designing a frame unit mark pseudo-grid layout, comprising:

[0052] Step 1: Provide a frame pattern, which is the pattern of the remaining area excluding the chip in a single shot;

[0053] A marking pattern is provided on the frame pattern, and the marking pattern is used to define a pattern for alignment and measurement on the substrate cutting path;

[0054] See also Figure 5 , widening the gap between the mark patterns according to the type of the mark patterns, the distance of the gap portion is determined by the type of the mark patterns and is not specifically limited here, and then inserting a first dummy grid pattern between the mark patterns;

[0055] In an embodiment of the present invention, the region where the marking pattern is located in step 1 includes the MOA layer and the back-end metal layer.

[0056] In an embodiment of the present invention, the second dummy gate pattern in step 1 is formed simultaneously with the frame pattern according to the design rules of the design software.

[0057] Step 2: setting second dummy grid patterns of different sizes according to the marking patterns at different levels, wherein the second dummy grid patterns are used to be set within the marking patterns;

[0058] In an embodiment of the present invention, in step 2, the second dummy grid patterns are distributed in the region of the marking pattern at equal intervals, that is, they are distributed in the horizontal direction and the vertical direction at equal intervals.

[0059] In the embodiments of the present invention, see Figure 1 and Figure 2 In step 2, the length of the second dummy gate in the MOA layer is 1.2 microns, the width is 0.038 microns, the period of the two second dummy gates adjacent to each other on the left and right is 0.18 microns, and the period of the two second dummy gates adjacent to each other on the top and bottom is 1.366 microns.

[0060] In the embodiments of the present invention, see Figure 3 In step 2, the length and width of the second dummy gate in the rear metal layer are both 0.8 microns, and the period of the two second dummy gates adjacent to each other on the left and right and the period of the two second dummy gates adjacent to each other on the top and bottom are both 0.8 microns.

[0061] It should be noted that the length, width, period and other parameters of the second dummy gate are determined by the production process and may also be other values.

[0062] In the embodiments of the present invention, see Figure 4 , which shows the situation after the pseudo-gate graphics of different levels in the frame unit are superimposed.

[0063] Step 3: Indent each side of the marking pattern inward by a set value, and then add a second dummy grid pattern within the marking pattern;

[0064] In an embodiment of the present invention, the indentation value in step three is 5 to 20 microns, for example, 5 microns, 10 microns, 15 microns or 20 microns. The indentation value here is determined by actual production conditions and may also be other values.

[0065] Step 4: setting a dummy block marking layer according to marking patterns of different levels, wherein the dummy block marking layer is used to define an area where a dummy gate is not formed.

[0066] In an embodiment of the present invention, the layout is used for processes at 7 nanometer technology nodes and below.

[0067] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0068] In summary, the present invention adds a dummy grid pattern to the existing frame unit mark dummy grid layout to achieve measurement or alignment purposes, solving the problem of registration mark shedding in advanced technology nodes. Therefore, the present invention effectively overcomes the various shortcomings of the existing technology and has high industrial application value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A frame unit marking pseudo-gate layout, characterized in that: include: A frame pattern, which is a pattern of the remaining area excluding the chip in a single shot; A marking pattern is provided on the frame pattern, and the marking pattern is used to define a pattern for alignment and measurement on the substrate cutting path, and the area where the marking pattern is located includes the MOA layer and the back-end metal layer; There are gaps between the mark patterns, and a first dummy gate pattern is inserted between the mark patterns; a second dummy gate pattern provided in the marking pattern, wherein the second dummy gate pattern has different sizes according to the marking patterns at different levels of the MOA layer and the back-end metal layer; A dummy block marking layer is provided on the marking pattern, and the dummy block marking layer is used to define an area where a dummy gate is not formed.

2. The frame unit marking pseudo-gate layout according to claim 1, characterized in that: The second dummy gate patterns are sequentially and equidistantly distributed in the region of the mark pattern.

3. The frame unit marking pseudo-gate layout according to claim 1, characterized in that: The second dummy gate in the MOA layer has a length of 1.2 microns and a width of 0.038 microns. The period between two adjacent second dummy gates is 0.18 microns, and the period between two adjacent second dummy gates is 1.366 microns.

4. The frame unit mark pseudo-gate layout according to claim 1, characterized in that: The length and width of the second dummy gate in the back-end metal layer are both 0.8 micrometers, and the period of two second dummy gates adjacent to each other on the left and right and the period of two second dummy gates adjacent to each other on the top and bottom are both 0.8 micrometers.

5. A design method for a frame unit marking pseudo-gate layout, characterized in that: At least: Step 1: Provide a frame pattern, which is a pattern of the remaining area excluding the chip in a single shot; Enlarging the gap between the mark patterns according to the type of the mark patterns, wherein the region where the mark patterns are located includes the MOA layer and the back-end metal layer, and then inserting a first dummy gate pattern between the mark patterns; Step 2: setting second dummy gate patterns of different sizes according to the marking patterns of different layers of the MOA layer and the back-end metal layer, wherein the second dummy gate patterns are used to be set within the marking patterns; Step 3: indent each side of the marking pattern inward by a set value, and then add the second dummy grid pattern within the marking pattern; Step 4: setting a dummy block marking layer according to the marking patterns at different levels, wherein the dummy block marking layer is used to define an area where a dummy gate is not formed.

6. The design method of the frame unit mark pseudo-grid layout according to claim 5, characterized in that: The second dummy gate pattern in step 2 is formed simultaneously with the frame pattern according to the design rules of the design software.

7. The design method of the frame unit mark pseudo-grid layout according to claim 5, characterized in that: In step 2, the second dummy gate patterns are distributed in sequence and at equal intervals in the region of the marking pattern.

8. The design method of the frame unit mark pseudo-grid layout according to claim 5, characterized in that: The second dummy gate in the MOA layer in step 2 has a length of 1.2 microns and a width of 0.038 microns. The period of two adjacent second dummy gates is 0.18 microns, and the period of two adjacent second dummy gates is 1.366 microns.

9. The method for designing a frame unit mark pseudo-grid layout according to claim 5, characterized in that: In step 2, the length and width of the second dummy gate in the rear metal layer are both 0.8 microns, and the period of two adjacent second dummy gates on the left and right and the period of two adjacent second dummy gates on the top and bottom are both 0.8 microns.

10. The design method of the frame unit mark pseudo-grid layout according to claim 5, characterized in that: The indentation setting value in step 3 is 5 to 20 microns.

Images