Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof. The method comprises: providing a layer to be etched; forming a plurality of etching stop structures on the surface of the layer to be etched; forming a protective layer on the sidewall surface of the plurality of etching stop structures; after forming the protective layer, forming a first mask layer on the plurality of etching stop structures and the layer to be etched, the first mask layer having a first mask opening, the first mask opening exposing part of the surface of the plurality of etching stop structures and the layer to be etched; etching the layer to be etched with the first mask layer and the plurality of etching stop structures as masks, forming a plurality of first conductive openings in the layer to be etched; and forming a plurality of first conductive structures in the plurality of first conductive openings. Thus, the process window is increased, and the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits is constantly shrinking, which will effectively improve the operating speed of the entire integrated circuit.

[0003] However, as the size requirements of components become smaller and smaller, the size of the conductive structures formed to connect with semiconductor devices becomes smaller and smaller, resulting in poor reliability of existing semiconductor structures, and the process window of existing manufacturing processes is small. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to increase the process window and improve the reliability of the semiconductor structure.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate having a plurality of mutually discrete fins; a plurality of gate structures located on the substrate and mutually discrete, the gate structures spanning the plurality of fins, and source / drain structures within the fins between adjacent gate structures; a first dielectric layer located on the substrate and the plurality of gate structures, the surface of the first dielectric layer being higher than the top surface of the gate structures; a plurality of etch-block structures located on the surface of the first dielectric layer between adjacent fins, at least a portion of the etch-block structures also being located on the first dielectric layer between adjacent gate structures; a protective layer located on the sidewalls of the plurality of etch-block structures; a plurality of first conductive openings located within the first dielectric layer, the extension direction of the first conductive openings being perpendicular to the extension direction of the fins, the first conductive openings exposing the top surface of the source / drain structures, and, in the extension direction of the first conductive openings, there is a gap between the projection of the first conductive opening and the projection of the etch-block structure.

[0006] Optionally, it further includes: a first mask layer located on the plurality of etching barrier structures and the first dielectric layer, the first mask layer having a first mask opening, the first mask opening exposing the plurality of etching barrier structures, the protective layer and the first conductive opening, and the etching barrier structures and the protective layer penetrating the first mask opening in a first direction, the first direction being perpendicular to the extension direction of the first mask opening.

[0007] Optionally, in the direction perpendicular to the sidewall of the etching barrier structure, the protective layer consists of two or more sub-protective layers, and the materials of adjacent sub-protective layers are different.

[0008] Optionally, the material of the protective layer includes silicon nitride.

[0009] Optionally, the thickness of the protective layer ranges from 5 angstroms to 3 nanometers.

[0010] Optionally, the material of the etching barrier structure includes titanium nitride.

[0011] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a layer to be etched; forming a plurality of etch barrier structures on the surface of the layer to be etched; forming a protective layer on the sidewalls of the plurality of etch barrier structures; after forming the protective layer, forming a first mask layer on the plurality of etch barrier structures and the layer to be etched, the first mask layer having a first mask opening, the first mask opening exposing a portion of the surfaces of the plurality of etch barrier structures and the layer to be etched, and the etch barrier structures penetrating the first mask opening in a first direction, the first direction being perpendicular to the extension direction of the first mask opening; using the first mask layer and the plurality of etch barrier structures as masks, etching the layer to be etched, forming a plurality of first conductive openings in the layer to be etched; and forming a plurality of first conductive structures in the plurality of first conductive openings.

[0012] Optionally, the method of forming a protective layer on the sidewalls of the plurality of etching barrier structures includes: forming a sidewall film on the surface of the layer to be etched and the plurality of etching barrier structures; and etching the sidewall film using an anisotropic etching process until the top surface of the plurality of etching barrier structures and the surface of the layer to be etched are exposed.

[0013] Optionally, the anisotropic etching process includes plasma etching.

[0014] Optionally, the process for forming the sidewall membrane includes atomic layer deposition.

[0015] Optionally, the layer to be etched includes: a substrate having a plurality of mutually discrete fins; a plurality of gate structures located on the substrate and mutually discrete, the gate structures spanning the plurality of fins, and source / drain structures within the fins between adjacent gate structures; and a first dielectric layer located on the substrate and the plurality of gate structures, the surface of the first dielectric layer being higher than the top surface of the gate structures.

[0016] Optionally, the first mask opening exposes the surface of the first dielectric layer on the source / drain structure, and the projection of the fin on the surface of the layer to be etched penetrates the projection of the first mask opening on the surface of the layer to be etched along a first direction.

[0017] Optionally, the etching barrier structure is located on a first dielectric layer between adjacent fins, and at least a portion of the etching barrier structure is also located on a first dielectric layer between adjacent gate structures.

[0018] Optionally, the method for forming a plurality of first conductive openings includes: using the first mask layer and a plurality of the etching barrier structures as masks, etching the first dielectric layer until the top surface of the source / drain structure is exposed; the first conductive structure is in contact with the top surface of the source / drain structure.

[0019] Optionally, it further includes: after forming the first conductive structure, forming a second dielectric layer on the surface of the first dielectric layer and the first conductive structure; forming a plurality of second conductive structures in the first dielectric layer and the second dielectric layer that are in contact with the top surface of the gate structure; in the extension direction of the first mask opening, at least one of the plurality of second conductive structures is also located in the first dielectric layer between adjacent first conductive structures, and the spacing between the adjacent first conductive structures is greater than the width of the second conductive structure.

[0020] Optionally, the etching barrier layer is made of titanium nitride, and the protective layer is made of silicon nitride.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] In the semiconductor structure formation method provided by the present invention, a protective layer is formed on the sidewall of an etch barrier structure, protecting the sidewall of the etch barrier structure during the etching process of forming the first conductive opening. Therefore, during the etching process of forming the first conductive opening, the wear on the sidewall of the etch barrier structure can be reduced, allowing the dimensions of the etch barrier structure in the width direction and the morphology of the sidewall to remain unchanged or change only slightly. This not only increases the process window for the etching process of forming the first conductive opening, but also improves the sidewall morphology and dimensional accuracy of the first conductive opening, reducing the risk of interconnection between the first conductive openings spaced apart by the etch barrier structure and the risk of short circuits between subsequently formed adjacent first conductive structures, thereby improving the reliability of the semiconductor structure. Attached Figure Description

[0023] Figures 1 to 4 This is a cross-sectional schematic diagram of the various steps in the formation process of a semiconductor structure;

[0024] Figures 5 to 22 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0025] Figure 23 This is a cross-sectional structural schematic diagram of the steps of a method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, the reliability of existing semiconductor structures is poor, and the process window of existing manufacturing processes is small.

[0027] The following detailed description is provided in conjunction with the attached figures.

[0028] Figures 1 to 4 This is a cross-sectional schematic diagram of the various steps in the formation process of a semiconductor structure.

[0029] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 A top-view structural diagram. Figure 2 yes Figure 1 A cross-sectional structural diagram along the X1-X2 direction is provided, showing the layer 100 to be etched.

[0030] Please continue to refer to this. Figure 1 and Figure 2 A plurality of etching barrier structures 110 are formed on the surface of the layer to be etched 100; an opening mask layer 120 is formed on the etching barrier structures 110 and the layer to be etched 100, the opening mask layer 120 exposing part of the etching barrier structures 110 and the surface of the layer to be etched 100.

[0031] Please refer to Figure 3 , Figure 3 and Figure 2 With the view direction consistent, the etching barrier structure 110 and the opening mask layer 120 are used as masks to etch the layer to be etched 100, forming a plurality of conductive openings 131 in the layer to be etched 100.

[0032] Figure 3 Region P in the text refers to the shape of the etch barrier structure 110 before the etch layer 100 is etched to form the conductive opening 131, before it is worn away.

[0033] Please refer to Figure 4 , Figure 4 and Figure 3 The views are aligned, and a conductive structure 130 is formed within the conductive opening 131.

[0034] However, when etching the material of the etching barrier structure 110, since the material at the top is etched for a longer time, island-shaped etching barrier structures 110 are usually formed, and the sidewalls of the etching barrier structure 110 are thinner near the bottom. Therefore, during the etching process to form the conductive opening 131, the material near the bottom of the sidewalls of the etching barrier structure 110 is easily worn away (e.g., Figure 3As shown, this results in poor morphology and dimensional accuracy of the conductive opening 131. For example, the conductive opening 131 may have gaps, or its size may increase in the X1-X2 direction. Therefore, on the one hand, controlling the wear on the etch stop structure 110 requires a high-precision etching process to form the conductive opening 131, resulting in a small process window for manufacturing. On the other hand, the conductive openings 131 separated by the etch stop structure 110 are prone to interconnection, leading to a high risk of short circuits between adjacent conductive structures 130 and poor reliability of the semiconductor structure. In summary, the semiconductor structure has poor reliability, and the manufacturing process window is small.

[0035] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure and a method for forming the same. By forming a protective layer on the sidewall of an etch barrier structure, the process window is increased, and the reliability of the semiconductor structure is improved.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 5 to 22 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] First, provide the layer to be etched.

[0039] In this embodiment, the layer to be etched includes: a substrate having a plurality of mutually discrete fins; a plurality of mutually discrete gate structures located on the substrate, the gate structures spanning the plurality of fins, and source / drain structures within the fins between adjacent gate structures; and a first dielectric layer located on the substrate and the plurality of gate structures, the surface of the first dielectric layer being higher than the top surface of the gate structures. For specific steps in forming the layer to be etched, please refer to [reference needed]. Figures 5 to 11 .

[0040] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 A schematic diagram of the three-dimensional structure. Figure 6 yes Figure 5 A top view of the structure is provided, with a substrate 201 having a plurality of mutually independent fins.

[0041] The substrate 201 is made of semiconductor material.

[0042] Specifically, the material of substrate 201 includes silicon.

[0043] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0044] In this embodiment, the substrate 201 has an isolation layer 203 on its surface, the isolation layer 203 is also located between adjacent fins 202, and the surface of the isolation layer 203 is lower than the top surface of the fin 202.

[0045] The function of the isolation layer 203 is to provide electrical insulation between adjacent fins 202 and between the semiconductor device and the substrate 201.

[0046] Please refer to Figure 7 and Figure 8 , Figure 7 and Figure 6 The view orientation is consistent. Figure 8 yes Figure 7 A cross-sectional structural diagram along the Y1-Y2 direction shows that several independent gate structures 210 are formed on the isolation layer 203, and the gate structures 210 span the top surface and part of the side wall surface of several of the fins 202.

[0047] In this embodiment, the gate structure 210 includes: a gate oxide layer (not shown) and a gate electrode (not shown) located on the surface of the gate oxide layer.

[0048] In this embodiment, the sidewalls of the grid structure 210 have sidewalls (not shown).

[0049] The gate oxide layer is made of silicon oxide. The gate electrode is made of polycrystalline silicon or amorphous silicon.

[0050] The sidewall material includes a low-k dielectric material (k less than 3.9) or a combination of multiple low-k dielectric materials, including SiOC, SiOCN and SiOCH.

[0051] The sidewall is used to define the location of the source drain opening later.

[0052] The method for forming the gate structure 210 and the sidewalls includes: forming a gate oxide film (not shown) on the isolation layer 203; forming a gate material layer (not shown) on the surface of the gate oxide film; forming a plurality of mutually discrete gate mask structures (not shown) on the surface of the gate material layer; using the gate mask structures as masks, etching the gate material layer and the gate oxide film until the surface of the isolation layer 203 is exposed to form the gate and the gate oxide layer; and forming sidewalls on the sidewalls of the gate oxide layer and the gate.

[0053] Please refer to Figure 9 , Figure 9 and Figure 8 With the same viewing direction, source and drain structures 204 are formed in the fins 202 on both sides of the gate structure 210.

[0054] In this embodiment, the method of forming the source-drain structure 204 includes: forming source-drain openings (not shown) in the fins 202 on both sides of the gate structure 210, the source-drain openings providing space for the source-drain structure; and forming the source-drain structure 204 in the source-drain openings.

[0055] In this embodiment, the method for forming source / drain openings includes: forming a source / drain mask layer (not shown) on the fin 202, the isolation layer 203, and the gate structure 210, wherein the source / drain mask layer exposes the surface of the fin 202 between adjacent gate structures 210; etching the fin 202 using the source / drain mask layer and the sidewalls as masks to form source / drain openings in the fins 202 on both sides of the gate structure 210.

[0056] In this embodiment, the process of etching the fin 202 to form the source / drain opening includes at least one of dry etching and wet etching.

[0057] In this embodiment, the process for forming the source / drain structure 204 includes an epitaxial growth process.

[0058] Please refer to Figure 10 and Figure 11 , Figure 10 and Figure 7 The view orientation is consistent. Figure 11 yes Figure 10 A cross-sectional view along the Y1-Y2 direction shows that a first dielectric layer 220 is formed on the substrate 201, and the surface of the first dielectric layer 220 is higher than the top surface of the gate structure 210.

[0059] In this embodiment, the etchable layer 200 includes: the substrate 201, the fin 202, the isolation layer 203, the gate structure 210, and the first dielectric layer 220.

[0060] In this embodiment, the process for forming the first dielectric layer 220 includes a spin coating process or a deposition process, wherein the deposition process includes chemical vapor deposition or physical vapor deposition, etc.

[0061] The material of the first dielectric layer 220 includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0062] In this embodiment, the material of the first dielectric layer 220 includes silicon oxide.

[0063] In another embodiment, a first dielectric layer 420 is formed on the substrate 201 (e.g., Figure 23 As shown), and, during the formation of the first dielectric layer 420, a gate structure 410 is formed (as shown). Figure 23 As shown), to form the layer to be etched 400 (as shown). Figure 23 As shown in the figure, the etchable layer 400 includes a substrate 201, a fin 202, an isolation layer 203, a gate structure 410 and a first dielectric layer 420, wherein the gate structure 410 is a metal gate.

[0064] The gate structure 410 spans a plurality of fins 202, and the source / drain structure 204 is located within the fins 202 between adjacent gate structures 410.

[0065] The gate structure 410 includes: a gate dielectric layer (not shown), a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode (not shown) located on the surface of the work function layer. The material of the gate dielectric layer includes silicon oxide or a high-k dielectric material, wherein the high-k dielectric material refers to a material with a dielectric constant greater than 3.9. The material of the work function layer includes one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN. The material of the gate electrode includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0066] The method of forming the first dielectric layer 420 and the gate structure 410 includes: forming a lower first dielectric layer (not shown) on the surfaces of the fin 202, the isolation layer 203, the source / drain structure 204, and the gate structure 210, wherein the lower first dielectric layer exposes the top surface of the gate structure 210; etching the exposed gate structure 210 to remove the gate structure 210; forming a gate opening (not shown) in the lower first dielectric layer, wherein the gate opening provides space for forming the gate structure 230; forming the gate structure 230 in the gate opening; and forming an upper first dielectric layer (not shown) on the surfaces of the gate structure 230 and the lower first dielectric layer, wherein the lower first dielectric layer and the upper first dielectric layer constitute the first dielectric layer 420.

[0067] Please refer to Figure 12 and Figure 13 , Figure 12 and Figure 10 The view orientation is consistent. Figure 13 yes Figure 12 A cross-sectional view along the Y3-Y4 direction shows that several etching barrier structures 300 are formed on the surface of the layer to be etched 200.

[0068] The etching barrier structure 300 is used to subsequently form the spaced-out first conductive opening.

[0069] The material of the etching barrier structure 300 is different from the material of the first dielectric layer 220. Therefore, the subsequent etching process for forming the first conductive opening can have different etching rates for the first dielectric layer 220 and the etching barrier structure 300, so that the formed first conductive opening is spaced apart by the etching barrier structure 300.

[0070] In this embodiment, the material of the etching barrier structure 300 includes titanium nitride.

[0071] It should be noted that, for ease of understanding, Figure 12 The diagram schematically shows the projection A of the fin 202 on the surface of the layer 200 to be etched, and the projection B of the gate structure 210 on the surface of the layer 200 to be etched.

[0072] In this embodiment, the etching barrier structure 300 is located on the first dielectric layer 220 between adjacent fins 202, and at least a portion of the etching barrier structure 300 is also located on the first dielectric layer 220 between adjacent gate structures 210.

[0073] Specifically, among the several etch barrier structures 300, at least one etch barrier structure 300 spans a gate structure 210.

[0074] In other embodiments, some etch barrier structures may not span the gate structure.

[0075] In this embodiment, the method for forming the etching barrier structure 300 includes: forming an etching barrier material layer (not shown) on the surface of the layer to be etched 200; forming a barrier patterning layer (not shown) on the surface of the etching barrier material layer, wherein the barrier patterning layer exposes part of the etching barrier material layer; and etching the etching barrier material layer using the barrier patterning layer as a mask until the surface of the first dielectric layer 220 is exposed.

[0076] In this embodiment, after forming a plurality of etch-blocking structures 300, the blocking patterning layer is removed.

[0077] Please refer to Figure 14 , Figure 14 and Figure 13 With the view orientation consistent, a protective layer 310 is formed on the sidewall surface of several of the etching barrier structures 300.

[0078] By forming a protective layer 310 on the sidewall of the etch barrier structure 300, the sidewall of the etch barrier structure 300 is protected during the subsequent etching process to form the first conductive opening. Therefore, during the subsequent etching process to form the first conductive opening, the wear on the sidewall of the etch barrier structure 300 can be reduced, allowing the dimensions of the etch barrier structure 300 in the width direction (direction X) and the morphology of the sidewall to remain unchanged or change only slightly. This not only increases the process window for the subsequent etching process to form the first conductive opening, but also improves the sidewall morphology and dimensional accuracy of the first conductive opening, reducing the risk of interconnection between the first conductive openings separated by the etch barrier structure and the risk of short circuits between adjacent first conductive structures formed subsequently, thereby improving the reliability of the semiconductor structure.

[0079] Furthermore, due to the protective layer 310, the etching barrier structure 300 is positioned in the width direction (e.g., ...). Figures 12 to 14 The dimensions in the direction X shown remain unchanged or change only slightly. Therefore, it is also possible to ensure that the spacing between adjacent first conductive openings in the direction X is large. This is beneficial for increasing the process window for forming the second conductive structure when it is subsequently formed.

[0080] The material of the protective layer 310 is different from the material of the etching barrier structure 300, and the material of the protective layer 310 is different from the material of the first dielectric layer 220. Therefore, the protective layer 310 can provide better protection for the sidewalls of the etching barrier structure 300 during the subsequent etching process to form the first conductive opening.

[0081] Specifically, the material of the protective layer 310 includes silicon nitride.

[0082] In this embodiment, the thickness of the protective layer 310 in the direction perpendicular to the sidewall of the etching barrier structure 300 ranges from 5 angstroms to 3 nanometers.

[0083] If the thickness of the protective layer 310 is too small, it is easily completely lost during the subsequent etching process to form the first conductive opening, or it is difficult to form a continuous protective layer 310 on the sidewall of the etching barrier structure 300. This results in poor protection of the sidewall of the etching barrier structure 300 during the subsequent etching process to form the first conductive opening, which is not conducive to increasing the process window of the semiconductor structure manufacturing process and improving the reliability of the semiconductor structure. If the thickness of the protective layer 310 is too large, the surface of the first dielectric layer 220 on the source / drain structure 204 may be blocked by the protective layer 310, which may easily lead to poor contact between the subsequently formed first conductive structure and the source / drain structure 204, or increase the contact resistance between the first conductive structure and the source / drain structure 204, which is not conducive to improving the performance and reliability of the semiconductor structure. Therefore, by making the thickness of the protective layer 310 range from 5 angstroms to 3 nanometers, it is possible to ensure that the protective layer 310 provides good protection for the sidewalls of the etch barrier structure 300, while avoiding the risk of poor contact between the first conductive structure and the source / drain structure 204 and the increase in contact resistance between the first conductive structure and the source / drain structure 204, thereby further improving the performance and reliability of the semiconductor structure.

[0084] In other embodiments, the protective layer consists of two or more sub-protective layers in a direction perpendicular to the sidewall of the etching barrier structure, and the materials of adjacent sub-protective layers are different.

[0085] Since the protective layer is composed of two or more sub-protective layers, and the materials of adjacent sub-protective layers are different, the etching process for forming the first conductive opening can be carried out at different etching rates for each sub-protective layer to better reduce the wear on the protective layer, thereby further enhancing the protection of the etching barrier structure during the etching process for forming the first conductive opening.

[0086] In this embodiment, the method of forming a protective layer 310 on the sidewall surface of the plurality of etching barrier structures 300 includes: forming a sidewall film (not shown) on the surface of the layer to be etched 200 and the plurality of etching barrier structures 300; and etching the sidewall film using an anisotropic etching process until the top surface of the plurality of etching barrier structures 300 and the surface of the layer to be etched 200 are exposed.

[0087] In this embodiment, the process for forming the sidewall membrane includes atomic layer deposition (ALD).

[0088] The atomic layer deposition process produces materials with high density, resulting in a highly dense protective layer 310. Furthermore, the atomic layer deposition process also improves the integrity, continuity, and uniformity of the sidewalls. This further enhances the protective effect of the protective layer 310 on the sidewalls of the etching barrier structure 300 during the subsequent formation of the first conductive opening.

[0089] In other embodiments, the process for forming the sidewall membrane includes chemical vapor deposition or physical vapor deposition, etc.

[0090] In this embodiment, the anisotropic etching process includes a plasma etching process.

[0091] Please refer to Figure 15 , Figure 15 and Figure 12 With the view direction consistent, after the protective layer 310 is formed, a first mask layer 320 is formed on the plurality of etching barrier structures 300 and the layer to be etched 200. The first mask layer 320 has a first mask opening 321, which exposes a portion of the surfaces of the plurality of etching barrier structures 300 and the layer to be etched 200. Furthermore, the etching barrier structure 300 penetrates the first mask opening 321 in a first direction Y, which is perpendicular to the extension direction of the first mask opening 321.

[0092] Specifically, the first mask opening 321 exposes the surface of the first dielectric layer 220 on the source / drain structure 204, and the projection A of the fin 202 on the surface of the layer to be etched 200 (e.g., Figure 12 (As shown) The projection of the first mask opening 321 through the first direction Y onto the surface of the layer to be etched 200.

[0093] In this embodiment, the method for forming the first mask layer 320 includes: forming a first mask material layer (not shown) on the surface of the layer to be etched 200 and the surface of the etch barrier structure 300, wherein the surface of the first mask material layer is higher than the top surface of the etch barrier structure 300; and patterning the first mask material layer to form a first mask layer 320 having the first mask opening 321.

[0094] The material of the first mask layer 320 is different from the materials of the etch barrier structure 300, the protective layer 310, and the first dielectric layer 220. Therefore, on the one hand, during the etching of the first mask material layer, the etching process can achieve a lower etching rate for the etch barrier structure 300, the protective layer 310, and the first dielectric layer 220, while achieving a higher etching rate for the first mask material layer, thus forming the first mask layer 320 with the first mask opening 321. On the other hand, during the subsequent etching of the first dielectric layer 220, the etching process can achieve a lower etching rate for the first mask layer 320, the etch barrier structure 300, and the protective layer 310, while achieving a higher etching rate for the first dielectric layer 220, thus forming the first conductive opening.

[0095] Specifically, the first mask layer 320 includes an organic etch barrier layer (not shown) and a photoresist layer (not shown) on the organic etch barrier layer.

[0096] In other embodiments, the first mask layer further includes an optical anti-reflective layer.

[0097] Please refer to Figure 16 and Figure 17 , Figure 16 and Figure 15 The view orientation is consistent. Figure 17 yes Figure 16 A cross-sectional structural diagram along the Y3-Y4 direction shows that the first mask layer 320 and several etching barrier structures 300 are used as masks to etch the layer to be etched 200, forming several first conductive openings 221 in the layer to be etched 200.

[0098] The first conductive opening 221 provides space for the subsequent formation of the first conductive structure.

[0099] In this embodiment, the first conductive opening 221 exposes the top surface of the source / drain structure 204, and a plurality of fins 202 penetrate the first conductive opening 221 along the first direction Y.

[0100] Specifically, in this embodiment, the method for forming a plurality of first conductive openings 221 includes: using the first mask layer 320 and a plurality of the etching barrier structures 300 as masks, etching the first dielectric layer 220 until the top surface of the source / drain structure 204 is exposed.

[0101] In this embodiment, the etching process of the first dielectric layer 220 includes at least one of dry etching process and wet etching process.

[0102] In this embodiment, after the first conductive opening 221 is formed, the first mask layer 320, the etch barrier structure 300, and the protective film 310 are removed.

[0103] Please refer to Figure 18 and Figure 19 , Figure 18 and Figure 16 The view orientation is consistent. Figure 19 yes Figure 18 A cross-sectional structural diagram along the Y3-Y4 direction, showing several first conductive openings 221 (e.g. Figure 16 and Figure 17 Several first conductive structures 330 are formed within the structure shown in the diagram.

[0104] In this embodiment, the first conductive structure 330 is in contact with the top surface of the source / drain structure 204.

[0105] In this embodiment, the material of the first conductive structure 330 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0106] In this embodiment, the method for forming the first conductive structure 330 includes: forming a first conductive structure material layer (not shown) inside the first conductive opening 221 and on the surface of the first dielectric layer 220, wherein the surface of the first conductive structure material layer is higher than the surface of the first dielectric layer 220; and planarizing the first conductive structure material layer until the top surface of the first dielectric layer 220 is exposed.

[0107] The process for forming the first conductive structural material layer includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Preferably, CVD is used to form the first conductive structural material layer.

[0108] The process for planarizing the first conductive structural material layer includes chemical mechanical polishing.

[0109] Please refer to Figure 20 , Figure 20 and Figure 18 With the view orientation consistent, after the first conductive structure 330 is formed, a second dielectric layer 340 is formed on the surface of the first dielectric layer 220 and the first conductive structure 330.

[0110] It should be noted that, for ease of understanding, Figure 20 The diagram schematically shows the projection C of several etch barrier structures 300 on the surface of the second dielectric layer 340.

[0111] In this embodiment, the process for forming the second dielectric layer 340 includes a spin coating process or a deposition process, wherein the deposition process includes a chemical vapor deposition process or a physical vapor deposition process, etc.

[0112] The material of the second dielectric layer 340 includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0113] In this embodiment, the material of the second dielectric layer 340 includes silicon oxide.

[0114] Next, a plurality of second conductive structures are formed within the first dielectric layer 220 and the second dielectric layer 340 to contact the top surface of the gate structure 210. In the extending direction (direction X) of the first mask opening 321, at least one of the plurality of second conductive structures is also located within the first dielectric layer 220 between adjacent first conductive structures 330, and the spacing W between the adjacent first conductive structures 220 (e.g., ...) Figure 18 (As shown in the diagram) is greater than the width of the second conductive structure.

[0115] Please refer to Figure 21 , Figure 21 and Figure 20 With the same viewing direction, a plurality of second conductive openings 341 are formed in the first dielectric layer 220 and the second dielectric layer 340, and each second conductive opening 341 exposes at least a portion of the top surface of the gate structure 210.

[0116] It should be noted that, for ease of understanding, Figure 21 The diagram schematically shows the projection C of several etch barrier structures 300 on the surface of the second dielectric layer 340.

[0117] In this embodiment, at least one of the plurality of second conductive openings 341 also exposes a portion of the top surface of at least two gate structures 210. Specifically, the second conductive opening 341 passes through the first dielectric layer 220 between adjacent first conductive structures 330 along the first direction Y.

[0118] The second conductive opening 341 provides space for the subsequent formation of the second conductive structure, which is in contact with the top surface of the gate structure.

[0119] Because a protective layer 310 is formed on the sidewall of the etch barrier structure 300, the dimensions of the etch barrier structure 300 in the width direction (direction X) and the morphology of the sidewall of the etch barrier structure can remain unchanged or change only slightly. Therefore, the spacing W between adjacent first conductive structures 330 in direction X is relatively large. This reduces, on the one hand, the overlay accuracy requirements and the width K1 requirements of the second conductive opening 341 are lowered, which is beneficial for increasing the process window size of the second conductive opening 341 formation process. On the other hand, it also increases the distance between the subsequently formed second conductive structure and the first conductive structure 330, reducing the risk of short circuits between the two structures and improving the reliability of the semiconductor structure.

[0120] In this embodiment, the method for forming the second conductive opening 341 includes: forming a second conductive opening mask layer (not shown) on the surface of the second dielectric layer 340, wherein the second conductive opening mask layer exposes a portion of the surface of the second dielectric layer 340; using the second conductive opening mask layer as a mask, etching the second dielectric layer 340 and the first dielectric layer 220 until the top surface of the gate structure 210 is exposed.

[0121] Please refer to Figure 22 , Figure 22 and Figure 21 With the view orientation consistent, a plurality of second conductive structures 350 are formed within a plurality of second conductive openings 341 that are in contact with the top surface of the gate structure 210.

[0122] It should be noted that, for ease of understanding, Figure 22 The diagram schematically shows the projection C of several etch barrier structures 300 on the surface of the second dielectric layer 340.

[0123] In this embodiment, in the extending direction (direction X) of the first mask opening 321, at least one of the second conductive structures 350 is also located within the first dielectric layer 220 between adjacent first conductive structures 330, and the spacing W between the adjacent first conductive structures 330 is greater than the width K2 of the second conductive structure 350.

[0124] In this embodiment, the material of the second conductive structure 350 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0125] In this embodiment, the method for forming the second conductive structure 350 includes: forming a second conductive structure material layer (not shown) inside the second conductive opening 341 and on the surface of the second dielectric layer 340, wherein the surface of the second conductive structure material layer is higher than the surface of the second dielectric layer 340; and planarizing the second conductive structure material layer until the top surface of the second dielectric layer 340 is exposed.

[0126] The process for forming the second conductive structural material layer includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Preferably, CVD is used to form the second conductive structural material layer.

[0127] The process for planarizing the second conductive structural material layer includes a chemical mechanical polishing process.

[0128] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [the original text]. Figure 16 and Figure 17 The device includes: a substrate 201 having a plurality of mutually discrete fins 202; a plurality of mutually discrete gate structures 210 located on the substrate 201, the gate structures 210 spanning the plurality of fins 202, and source / drain structures 204 within the fins 202 between adjacent gate structures 210; and a first dielectric layer 220 located on the substrate 201 and the plurality of gate structures 210, the surface of the first dielectric layer 220 being higher than the top surface of the gate structures 210.

[0129] The substrate 201 is made of semiconductor material.

[0130] Specifically, the material of substrate 201 includes silicon.

[0131] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0132] The gate structure 210 includes a gate oxide layer (not shown) and a gate electrode (not shown) located on the surface of the gate oxide layer. The gate structure 210 has sidewalls (not shown) on its sidewalls.

[0133] The gate oxide layer is made of silicon oxide. The gate electrode is made of polycrystalline silicon or amorphous silicon.

[0134] The sidewall material includes a low-k dielectric material (k less than 3.9) or a combination of multiple low-k dielectric materials, including SiOC, SiOCN and SiOCH.

[0135] In this embodiment, the substrate 201 has an isolation layer 203 on its surface, the isolation layer 203 is also located between adjacent fins 202, and the surface of the isolation layer 203 is lower than the top surface of the fin 202.

[0136] Specifically, the gate structure 210 and the first dielectric layer 220 are located on the isolation layer 203.

[0137] In another embodiment, the semiconductor structure includes: a substrate 201 having a plurality of mutually discrete fins 202, an isolation layer 203 on the surface of the substrate 201, the isolation layer 203 being located between adjacent fins 202, and the surface of the isolation layer 203 being lower than the top surface of the fins 202; a plurality of mutually discrete gate structures 410 located on the isolation layer 203, the gate structures 410 spanning the plurality of fins 202, and source / drain structures 204 within the fins 202 between adjacent gate structures 410; and a first dielectric layer 420 located on the isolation layer 203 and the plurality of gate structures 410, the surface of the first dielectric layer 420 being higher than the top surface of the gate structures 410.

[0138] The main difference between this embodiment and another embodiment is that the gate structure 410 is different from the gate structure 210 in this embodiment. Specifically, the gate structure 410 is a metal gate. The gate structure 410 includes: a gate dielectric layer (not shown), a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode (not shown) located on the surface of the work function layer. The material of the gate dielectric layer includes: silicon oxide or a high-K dielectric material, wherein the high-K dielectric material refers to a material with a dielectric constant greater than 3.9. The material of the work function layer includes one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN. The material of the gate electrode includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0139] The semiconductor structure further includes: a plurality of etch barrier structures 300 located on the surface of a first dielectric layer 220 between adjacent fins 202, at least a portion of the etch barrier structures 300 being located on the first dielectric layer 220 between adjacent gate structures 210; and a protective layer 310 located on the sidewalls of the plurality of etch barrier structures 300.

[0140] The material of the etching barrier structure 300 is different from the material of the first dielectric layer 220.

[0141] In this embodiment, the material of the etching barrier structure 300 includes titanium nitride.

[0142] In this embodiment, among the plurality of etch barrier structures 300, at least one etch barrier structure 300 spans a gate structure 210.

[0143] In other embodiments, some etch barrier structures may not span the gate structure.

[0144] The material of the protective layer 310 is different from the material of the etching barrier structure 300, and the material of the protective layer 310 is different from the material of the first dielectric layer 220.

[0145] In this embodiment, the material of the protective layer 310 includes silicon nitride.

[0146] In other embodiments, the protective layer consists of two or more sub-protective layers in a direction perpendicular to the sidewall of the etching barrier structure, and the materials of adjacent sub-protective layers are different.

[0147] In this embodiment, the thickness of the protective layer 310 ranges from 5 angstroms to 3 nanometers.

[0148] The semiconductor structure further includes a plurality of first conductive openings 221 located within the first dielectric layer 220. The extension direction of the first conductive openings 221 is perpendicular to the extension direction of the fin 202. The first conductive openings 221 expose the top surface of the source / drain structure 204. Furthermore, there is a gap between the projection of the first conductive opening 221 and the projection of the etch barrier structure 300 in the extension direction of the first conductive opening 221.

[0149] In this embodiment, the semiconductor structure further includes a first mask layer 320 located on the plurality of etch barrier structures 300 and the first dielectric layer 220. The first mask layer 320 has a first mask opening 321, which exposes the plurality of etch barrier structures 300, the protective layer 310 and the first conductive opening 221. Furthermore, the etch barrier structures 300 and the protective layer 210 penetrate the first mask opening 321 in a first direction Y, which is perpendicular to the extension direction of the first mask opening 321.

[0150] Specifically, the first mask layer 320, the etching barrier structure 300, and the protective layer 310 are used together to form a plurality of first conductive openings 221 within the first dielectric layer 220. These first conductive openings 221 are used to form the first conductive structure 330 (e.g., ...). Figure 18 (As shown).

[0151] In this embodiment, the material of the first mask layer 320 is different from the materials of the etching barrier structure 300, the protective layer 310, and the first dielectric layer 220.

[0152] Specifically, the first mask layer 320 includes an organic etch barrier layer (not shown) and a photoresist layer (not shown) on the organic etch barrier layer.

[0153] In other embodiments, the first mask layer further includes an optical anti-reflective layer.

[0154] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a plurality of mutually discrete fins; A plurality of gate structures located on a substrate and being mutually independent, the gate structures spanning a plurality of the fins, and the fins between adjacent gate structures having source and drain structures; A first dielectric layer is located on the substrate and the plurality of gate structures, the surface of the first dielectric layer being higher than the top surface of the gate structures; A plurality of etching barrier structures are located on the surface of a first dielectric layer between adjacent fins, and at least a portion of the etching barrier structures are also located on the first dielectric layer between adjacent gate structures; A protective layer located on the sidewalls of several of the etching barrier structures; A plurality of first conductive openings are located within the first dielectric layer. The extension direction of the first conductive openings is perpendicular to the extension direction of the fin. The first conductive openings expose the top surface of the source / drain structure. Furthermore, there is a gap between the projection of the first conductive opening and the projection of the etching barrier structure in the extension direction of the first conductive opening. A first mask layer is located on a plurality of the etching barrier structures and the first dielectric layer. The first mask layer has a first mask opening. The first mask opening exposes the plurality of the etching barrier structures, the protective layer and the first conductive opening. The etching barrier structures and the protective layer penetrate the first mask opening in a first direction, which is perpendicular to the extension direction of the first mask opening.

2. The semiconductor structure as described in claim 1, characterized in that, In the direction perpendicular to the sidewall of the etching barrier structure, the protective layer consists of two or more sub-protective layers, and the materials of adjacent sub-protective layers are different.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes silicon nitride.

4. The semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer ranges from 5 angstroms to 3 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the etching barrier structure includes titanium nitride.

6. A method for forming a semiconductor structure, characterized in that, include: Provide the layer to be etched; Several etching barrier structures are formed on the surface of the layer to be etched; A protective layer is formed on the sidewall surface of several of the etching barrier structures; After the protective layer is formed, a first mask layer is formed on the plurality of etching barrier structures and the layer to be etched. The first mask layer has a first mask opening, which exposes a portion of the surfaces of the plurality of etching barrier structures and the layer to be etched. Furthermore, the etching barrier structures penetrate the first mask opening in a first direction, which is perpendicular to the extension direction of the first mask opening. Using the first mask layer and several etching barrier structures as masks, the layer to be etched is etched to form several first conductive openings in the layer to be etched. A plurality of first conductive structures are formed within a plurality of the first conductive openings.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, A method for forming a protective layer on the sidewall surface of a plurality of etching barrier structures includes: forming a sidewall film on the surface of the layer to be etched and the surfaces of the plurality of etching barrier structures; and etching the sidewall film using an anisotropic etching process until the top surfaces of the plurality of etching barrier structures and the surface of the layer to be etched are exposed.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The anisotropic etching process includes plasma etching.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process for forming the sidewall membrane includes atomic layer deposition.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, The layer to be etched includes: a substrate having a plurality of mutually discrete fins; a plurality of gate structures located on the substrate and mutually discrete, the gate structures spanning the plurality of fins, and source / drain structures within the fins between adjacent gate structures; and a first dielectric layer located on the substrate and the plurality of gate structures, the surface of the first dielectric layer being higher than the top surface of the gate structures.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first mask opening exposes the surface of the first dielectric layer on the source / drain structure, and the projection of the fin on the surface of the layer to be etched penetrates the projection of the first mask opening on the surface of the layer to be etched along the first direction.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The etching barrier structure is located on a first dielectric layer between adjacent fins, and at least a portion of the etching barrier structure is also located on a first dielectric layer between adjacent gate structures.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming a plurality of first conductive openings includes: using the first mask layer and a plurality of the etching barrier structures as masks, etching the first dielectric layer until the top surface of the source / drain structure is exposed; the first conductive structure is in contact with the top surface of the source / drain structure.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, Also includes: After the first conductive structure is formed, a second dielectric layer is formed on the surface of the first dielectric layer and the first conductive structure. A plurality of second conductive structures are formed in the first dielectric layer and the second dielectric layer to contact the top surface of the gate structure. In the extension direction of the first mask opening, at least one of the plurality of second conductive structures is also located in the first dielectric layer between adjacent first conductive structures, and the spacing between the adjacent first conductive structures is greater than the width of the second conductive structure.

15. The method for forming a semiconductor structure as described in claim 6, characterized in that, The etching barrier structure is made of titanium nitride, and the protective layer is made of silicon nitride.

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