Array substrate and method for preparing the same

Abstract

The present application provides an array substrate and a method for manufacturing the same. The array substrate includes a display area and a peripheral area. The display area includes a first thin film transistor, and the peripheral area includes a second thin film transistor. The first thin film transistor includes a first active layer, and the first active layer is amorphous silicon. The second thin film transistor includes a second active layer, and the second active layer is low-temperature polycrystalline silicon. Among them, the first active layer and the second active layer are disposed on the same layer. The array substrate provided by the present application has high mobility, high stability, high compatibility with existing mass production processes, simple processes, and low costs.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate and a method for manufacturing the same. Background Art

[0002] The future development trend of display screens is narrow borders, large panel sizes, high product resolution, and high driving frequencies, which pose higher requirements for display panels. Among them, gate driver on array (GOA) is a technology that integrates a gate driving circuit on an array substrate. It can not only achieve a borderless design, increasing the customer's process design options, but also save gate chips (Gate ICs), and has obvious benefits in large-size and high-resolution panels, and has great application potential in the field of display panels, especially in high-end products.

[0003] Since the working conditions of GOA are more demanding, GOA has higher requirements for the mobility and stability of thin film transistors (TFTs). Currently, the mainstream TFT technologies include amorphous silicon (a-Si) thin film transistors, metal oxide (Oxide) thin film transistors, and low temperature poly-silicon (LTPS). Among them, the a-Si technology is the most mature, but its low mobility greatly limits the advantages of GOA technology; although oxide semiconductors have high mobility, they are sensitive to water, oxygen, and light, and have poor stability; in contrast, LTPS has the advantages of high mobility and good stability, and can be used as an excellent material for GOA TFT devices.

[0004] The large-size display screens of high-end products cannot do without the application of GOA. However, currently, the high-generation lines in mass production or to be put into production are mainly based on the back-channel etch (BCE) structure and mostly adopt the Top-Gate structure, with complex processes. Therefore, there is an urgent need to develop an array substrate structure that is suitable for large-size display panels, has high mobility, high stability, high compatibility with existing mass production processes, simple processes, and low costs. Summary of the Invention

[0005] In view of this, this application provides an array substrate with high mobility and high stability that is suitable for large-size display panels, and the entire manufacturing process of this array substrate has high compatibility with existing mass production processes, simple processes, and low costs.

[0006] In a first aspect, this application provides an array substrate, including a display area and a peripheral area. The display area includes a first thin film transistor, and the peripheral area includes a second thin film transistor;

[0007] The first thin film transistor includes a first active layer, and the first active layer is amorphous silicon;

[0008] The second thin film transistor includes a second active layer, and the second active layer is low-temperature polycrystalline silicon;

[0009] Wherein, the first active layer and the second active layer are arranged in the same layer.

[0010] In an alternative embodiment of the present application, the first thin film transistor further includes a first gate opposite to the first active layer, and the first gate includes a first metal layer and a second metal layer located on the first metal layer;

[0011] The second thin film transistor further includes a second gate opposite to the second active layer, and the second gate includes at least a part of a third metal layer;

[0012] Wherein, the temperature tolerance of the first metal layer and the third metal layer is higher than that of the second metal layer, and the resistivity of the second metal layer is lower than that of the first metal layer.

[0013] In an alternative embodiment of the present application, the third metal layer includes a first region and a second region located on at least one side of the first region. The third metal layer in the first region is opposite to the second active layer, and a fourth metal layer is provided on the third metal layer in the second region. The third metal layer in the second region and the fourth metal layer form a scanning trace;

[0014] Wherein, the resistivity of the fourth metal layer is lower than that of the third metal layer.

[0015] In an alternative embodiment of the present application, the first metal layer and the third metal layer are arranged in the same layer, and the first metal layer and the third metal layer are made of the same material, which is molybdenum, titanium or a molybdenum-titanium alloy.

[0016] In an alternative embodiment of the present application, the second metal layer and the fourth metal layer are arranged in the same layer, and the second metal layer and the fourth metal layer are made of the same material, which is aluminum or copper.

[0017] In an alternative embodiment of the present application, the peripheral region includes a GOA gate driving circuit, and the GOA gate driving circuit includes the second thin film transistor and the scanning trace.

[0018] In an alternative embodiment of the present application, the array substrate further includes a substrate and a gate insulating layer. The first thin film transistor further includes a first source electrode and a first drain electrode, and the second thin film transistor further includes a second source electrode and a second drain electrode;

[0019] Among them, the first gate and the second gate are located on one side of the substrate, the gate insulating layer is located on the side of the first gate and the second gate away from the substrate, the first active layer and the second active layer are located on the side of the gate insulating layer away from the first gate and the second gate, the first source electrode and the first drain electrode are located on the side of the first active layer away from the gate insulating layer and are electrically connected to the first active layer, and the second source electrode and the second drain electrode are located on the side of the second active layer away from the gate insulating layer and are electrically connected to the second active layer.

[0020] In a second aspect, the present application provides a method for manufacturing an array substrate, where the array substrate includes a display area and a peripheral area, and the method includes:

[0021] Form a first gate and a second gate on the substrate, where the first gate is located in the display area and the second gate is located in the peripheral area; the first gate includes a first metal layer and a second metal layer located on the first metal layer, and the second gate includes at least a part of a third metal layer; among them, the temperature tolerance of the first metal layer and the third metal layer is higher than that of the second metal layer, and the resistivity of the second metal layer is lower than that of the first metal layer.

[0022] Form a gate insulating layer on the substrate, the first gate, and the second gate;

[0023] Form a first active layer and a second active layer on the gate insulating layer; among them, the first active layer is amorphous silicon and is opposite to the first gate, and the second active layer is low-temperature polycrystalline silicon and is opposite to the second gate;

[0024] Form a first source electrode and a first drain electrode on the first active layer, and form a second source electrode and a second drain electrode on the second active layer; among them, the first source electrode and the first drain electrode are electrically connected to the first active layer, and the second source electrode and the second drain electrode are electrically connected to the second active layer.

[0025] In an optional embodiment of the present application, the third metal layer includes a first region and a second region located on at least one side of the first region, the third metal layer in the first region is opposite to the second active layer, a fourth metal layer is provided on the third metal layer in the second region, and the third metal layer and the fourth metal layer in the second region form a scanning trace;

[0026] Among them, the resistivity of the fourth metal layer is lower than that of the third metal layer.

[0027] In an alternative embodiment of the present application, the first metal layer and the third metal layer are disposed on the same layer, and the first metal layer and the third metal layer are made of the same material, which is molybdenum, titanium, or a molybdenum-titanium alloy;

[0028] The second metal layer and the fourth metal layer are disposed on the same layer, and the second metal layer and the fourth metal layer are made of the same material, which is aluminum or copper.

[0029] The present application provides an array substrate and a method for manufacturing the same. The array substrate provided by the present application is a hybrid TFT type array substrate, including a first thin film transistor located in the display area and a second thin film transistor located in the peripheral area. The first thin film transistor is an amorphous silicon thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor. Moreover, the first active layer of the first thin film transistor and the second active layer of the second thin film transistor are disposed on the same layer. The array substrate of the present application uses the amorphous silicon manufacturing process commonly used in existing mass production processes in the display area and uses the low-temperature polycrystalline silicon manufacturing process with high mobility and high stability in the peripheral area. The entire manufacturing process of this array substrate has high compatibility with the existing amorphous silicon mass production process. It only needs to add a crystallization process after the amorphous silicon film formation of the first active layer and the second active layer to make the amorphous silicon of the second active layer crystallize to form polycrystalline silicon. Moreover, the first active layer of the first thin film transistor and the second active layer of the second thin film transistor are disposed on the same layer, which can reduce the number of photomasks and simplify the process. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 It is a schematic structural diagram of an array substrate provided by an embodiment of the present application.

[0032] Figure 2 It is a schematic structural diagram of step S10 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0033] Figure 3 It is a schematic structural diagram of step S11 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0034] Figure 4 It is a schematic structural diagram of step S12 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0035] Figure 5Schematic structural diagram of step S13 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0036] Figure 6 Schematic structural diagram of step S14 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0037] Figure 7 Schematic structural diagram of step S15 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0038] Figure 8 Schematic structural diagram of step S16 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0039] Figure 9 Schematic structural diagram of step S17 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0040] Figure 10 Schematic structural diagram of step S18 of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0041] Figure 11 Schematic structural diagram of step S20 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0042] Figure 12 Schematic structural diagram of step S21 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0043] Figure 13 Schematic structural diagram of step S22 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0044] Figure 14 Schematic structural diagram of step S23 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0045] Figure 15 Schematic structural diagram of step S24 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0046] Figure 16 Schematic structural diagram of step S25 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0047] Figure 17 Schematic structural diagram of step S26 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0048] Figure 18 Schematic structural diagram of step S27 of a method for manufacturing an array substrate provided by another embodiment of the present application.

[0049] Figure 19 Schematic structural diagram of step S28 in a method for manufacturing an array substrate provided in another embodiment of the present application. Detailed implementation manners

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0051] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0052] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or arrangements discussed.

[0053] The array substrate and the method for manufacturing the array substrate provided by the present application will be described in detail below with reference to specific embodiments and the accompanying drawings.

[0054] As Figure 1 shown, the present application provides an array substrate, including a display area and a peripheral area. The display area includes a first thin-film transistor, and the peripheral area includes a second thin-film transistor. The first thin-film transistor includes a first active layer 410, and the first active layer 410 is amorphous silicon (a-Si). The second thin-film transistor includes a second active layer 420, and the second active layer 420 is low-temperature polycrystalline silicon (LTPS). Wherein, the first active layer 410 and the second active layer 420 are arranged in the same layer.

[0055] Since the amorphous silicon thin film transistor technology is the most mature, the existing mass production processes of array substrates are mostly amorphous silicon processes. Based on the existing amorphous silicon mass production process, this application designs the structure of the array substrate. By using conventional amorphous silicon thin film transistors in the display area of the array substrate and low-temperature polycrystalline silicon thin film transistors with high mobility and high stability in the peripheral area of the array substrate, the overall performance of the array substrate is improved. The entire manufacturing process of the array substrate in this application has high compatibility with the existing amorphous silicon mass production process. It only needs to add a crystallization process after the amorphous silicon film formation of the first active layer and the second active layer to make the amorphous silicon of the second active layer crystallize into polycrystalline silicon. Moreover, the first active layer of the first thin film transistor and the second active layer of the second thin film transistor are arranged in the same layer, which can reduce the number of photomasks, simplify the process, and save costs.

[0056] In one embodiment, the first thin film transistor further includes a first gate 210 opposite to the first active layer 410. The first gate 210 includes a first metal layer 211 and a second metal layer 212 located on the first metal layer 211. The second thin film transistor further includes a second gate 220 opposite to the second active layer 420. The second gate 220 includes at least a part of a third metal layer 221. Among them, the temperature tolerance of the first metal layer 211 and the third metal layer 221 is higher than that of the second metal layer 212, and the resistivity of the second metal layer 212 is lower than that of the first metal layer 211.

[0057] Since the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor, and the low-temperature polycrystalline silicon is formed by laser high-temperature crystallization of amorphous silicon. During the crystallization process of the amorphous silicon in the second active layer, the corresponding second gate is prone to high-temperature damage due to laser high-temperature irradiation. Therefore, in this application, the material of the second gate is selected as a high-temperature resistant metal material to avoid the problem of damage to the second gate caused by the laser crystallization process. However, the resistivity of high-temperature resistant materials is relatively high. In order to ensure the display performance of the display area, a second metal layer with a resistivity lower than that of the first metal layer is provided on the high-temperature resistant first metal layer to ensure the low-resistance characteristic of the first gate.

[0058] In one embodiment, the third metal layer 221 includes a first region 223 and a second region 224 located on at least one side of the first region 223. The third metal layer in the first region 223 is opposite to the second active layer 420. A fourth metal layer 222 is provided on the third metal layer in the second region 224. The third metal layer in the second region 224 and the fourth metal layer 222 form a scanning trace. Among them, the resistivity of the fourth metal layer 222 is lower than that of the third metal layer 221 to ensure the low-resistance characteristic of the scanning trace.

[0059] In one embodiment, the first metal layer 211 and the third metal layer 221 are arranged on the same layer. The first metal layer 211 and the third metal layer 221 are formed by the same manufacturing process, and the patterns of the first metal layer 211 and the third metal layer 221 are formed by using the same mask plate, which can simplify the process.

[0060] Furthermore, the first metal layer 211 and the third metal layer 221 are made of the same material, which is molybdenum, titanium or molybdenum-titanium alloy. The first metal layer 211 and the third metal layer 221 are made of high-temperature resistant metal materials such as molybdenum, titanium or molybdenum-titanium alloy to avoid the problem of gate damage caused by high temperature when the amorphous silicon of the second active layer 420 is crystallized by laser.

[0061] Furthermore, the first metal layer 211 and the third metal layer 221 have the same thickness, which is 50 to 400 angstroms.

[0062] In one embodiment, the second metal layer 212 and the fourth metal layer 222 are arranged on the same layer. The second metal layer 212 and the fourth metal layer 222 are formed by the same manufacturing process, and the patterns of the second metal layer 212 and the fourth metal layer 222 are formed by using the same mask plate, which can simplify the process.

[0063] Furthermore, the second metal layer 212 and the fourth metal layer 222 are made of the same material, which is aluminum or copper. The second metal layer 212 is arranged on the first metal layer 211, and the fourth metal layer 222 is arranged on the third metal layer 221. The second metal layer 212 and the fourth metal layer 222 are made of aluminum or copper to reduce the resistance and ensure the low-resistance characteristic of the circuit.

[0064] In one embodiment, the Half Tone Mask process can also be used to perform differential patterning on the gate metal layer. The patterns of the first metal layer 211, the second metal layer 212, the third metal layer 221 and the fourth metal layer 222 are formed simultaneously by using the Half Tone Mask to save the number of mask plates, reduce the number of photomasks and simplify the process. The Half Tone Mask is opaque in the area corresponding to the first gate 210 to form the patterns of the stacked first metal layer 211 and the second metal layer 212 of the first gate 210; the Half Tone Mask is partially transparent in the area corresponding to the first region 223 and opaque in the area corresponding to the second region 224 to form the pattern of the third metal layer 221 of the second gate 220 and the patterns of the stacked third metal layer 221 and the fourth metal layer 222 of the scan trace.

[0065] Further, the peripheral region includes a GOA gate driving circuit, and the GOA gate driving circuit includes the second thin film transistor and the scanning trace. By using conventional amorphous silicon TFTs in the display area of the array substrate and LTPS TFTs in the GOA area, normal display in the display area can be ensured, while the mobility and stability in the GOA area are improved to enhance the performance of the array substrate.

[0066] In one embodiment, the array substrate further includes a substrate 100 and a gate insulating layer 300. The first thin film transistor further includes a first source electrode 510 and a first drain electrode 520. The second thin film transistor further includes a second source electrode 530 and a second drain electrode 540.

[0067] Specifically, the first gate electrode 210 and the second gate electrode 220 are located on one side of the substrate. The gate insulating layer 300 is located on the side of the first gate electrode 210 and the second gate electrode 220 away from the substrate 100. The first active layer 410 is located on the side of the gate insulating layer 300 away from the first gate electrode 210 and opposite to the first gate electrode 210. The second active layer 420 is located on the side of the gate insulating layer 300 away from the second gate electrode 220 and opposite to the second gate electrode 220. The first source electrode 510 and the first drain electrode 520 are located on the side of the first active layer 410 away from the gate insulating layer 300 and electrically connected to the first active layer 410. The second source electrode 530 and the second drain electrode 540 are located on the side of the second active layer 420 away from the gate insulating layer 300 and electrically connected to the second active layer 420. Adopting a bottom-gate structure can reduce the number of photomasks, simplify the process, and reduce costs.

[0068] Further, the array substrate further includes a passivation layer 600 located on the first source electrode 510, the first drain electrode 520, the second source electrode 530, and the second drain electrode 540, and a first electrode layer 710 and a second electrode layer 720 located on the passivation layer 600.

[0069] The present application also provides a method for manufacturing an array substrate. The array substrate includes a display area and a peripheral area. The method includes:

[0070] A first gate 210 and a second gate 220 are formed on a substrate 100. The first gate 210 is located in the display area, and the second gate 220 is located in the peripheral area. The first gate 210 includes a first metal layer 211 and a second metal layer 212 located on the first metal layer 211. The second gate 220 includes at least a part of a third metal layer 221. Among them, the first metal layer 211 and the third metal layer 221 are high-temperature resistant metals, and the resistivity of the second metal layer 212 is lower than that of the first metal layer 211.

[0071] A gate insulating layer 300 is formed on the substrate 100, the first gate 210, and the second gate 220.

[0072] A first active layer 410 and a second active layer 420 are formed on the gate insulating layer 300. Among them, the first active layer 410 is amorphous silicon and is opposite to the first gate 210, and the second active layer 420 is low-temperature polycrystalline silicon and is opposite to the second gate 220.

[0073] A first source electrode 510 and a first drain electrode 520 are formed on the first active layer 410, and a second source electrode 530 and a second drain electrode 540 are formed on the second active layer 420. Among them, the first source electrode 510 and the first drain electrode 520 are electrically connected to the first active layer 410, and the second source electrode 530 and the second drain electrode 540 are electrically connected to the second active layer 420.

[0074] Further, the third metal layer 221 includes a first region 223 and a second region 224 located on at least one side of the first region 223. The third metal layer of the first region 223 is opposite to the second active layer 420, and a fourth metal layer 222 is provided on the third metal layer of the second region 224. The third metal layer of the second region 224 and the fourth metal layer 222 form a scanning trace. Among them, the resistivity of the fourth metal layer 222 is lower than that of the third metal layer 221.

[0075] Further, the first metal layer 211 and the third metal layer 221 are arranged in the same layer; the second metal layer 212 and the fourth metal layer 222 are arranged in the same layer to simplify the process.

[0076] Further, the first metal layer 211 and the third metal layer 221 are made of the same material, which is a high-temperature resistant metal such as molybdenum, titanium, or a molybdenum-titanium alloy; the second metal layer 212 and the fourth metal layer 222 are made of the same material, which is aluminum or copper.

[0077] Further, the first active layer 410 and the second active layer 420 are disposed on the same layer to simplify the process. Specifically, an amorphous silicon layer 400 is deposited on the gate insulating layer 300, and through patterning, an amorphous silicon pattern of the first active layer 410 and an amorphous silicon pattern of the second active layer 420 are formed. Then, the amorphous silicon of the second active layer 420 is crystallized into Poly-Si (LTPS) by a two-step laser annealing method, that is, in the first step, dehydrogenation treatment is performed on the amorphous silicon of the second active layer 420 using a low energy density, and in the second step, annealing crystallization is performed on the second active layer 420 using a high energy density to form Poly-Si.

[0078] Further, the first source electrode 510, the first drain electrode 520, the second source electrode 530, and the second drain electrode 540 are disposed on the same layer to simplify the process.

[0079] Further, the peripheral region includes a GOA gate driving circuit, and the GOA gate driving circuit includes the second thin film transistor and the scanning trace.

[0080] The preparation method of the array substrate provided by the present application is described in detail below through specific embodiments.

[0081] In an embodiment, the array substrate includes a display area and a peripheral region, and the peripheral region includes a GOA gate driving circuit (GOA area).

[0082] The preparation method of the array substrate includes the following steps:

[0083] S10: As Figure 2 shown, on the substrate 100, a first gate metal sub-layer 201 and a second gate metal sub-layer 202 are sequentially deposited by a PVD process. The first gate metal sub-layer 201 is a high-temperature resistant layer, and the second gate metal sub-layer 202 is a main body layer. The material of the first gate metal sub-layer 201 can be a high-temperature resistant metal such as Mo, Ti, or a MoTi alloy, etc. The deposition thickness of the first gate metal sub-layer 201 is 50 - 400 angstroms, and the material of the second gate metal sub-layer 202 can be Al, Cu, etc.

[0084] S11: As Figure 3As shown, the Half Tone Mask process is used to perform differential patterning on the first gate metal sub-layer 201 and the second gate metal sub-layer 202. The mask 800 used in the Half Tone Mask process includes a light-transmitting area 810 and a first light-blocking area 820 in the display area, and a light-transmitting area 810, a partially light-transmitting area 830, and a second light-blocking area 840 in the GOA area. During the photomask process, the light intensity of the incident light passing through different areas of the mask 800 is different. In the GOA area, the photoresist PR corresponding to the partially light-transmitting area 830 is thinner than the photoresist PR corresponding to the second light-blocking area 840, so as to simultaneously perform differential patterning on the first gate metal sub-layer 201 and the second gate metal sub-layer 202.

[0085] S12: As Figure 4 shown, after patterning the first gate metal sub-layer 201, a pattern of a first metal layer 211 and a third metal layer 221 is formed, and after patterning the second gate metal sub-layer 202, a pattern of a second metal layer 212 and a fourth metal layer 222 is formed. Among them, the second metal layer 212 covers the first metal layer 211, the third metal layer 221 includes a first area 223 and a second area 224, and the fourth metal layer 222 covers the third metal layer 221 of the second area 224.

[0086] The first metal layer 211 and the third metal layer 221 are of the same layer, and the first metal layer 211 and the third metal layer 221 are made of the same material, which is a high-temperature resistant metal such as molybdenum, titanium, or molybdenum-titanium alloy. The thickness of the first metal layer 211 and the third metal layer 221 is the same, which is 50 - 400 angstroms.

[0087] The second metal layer 212 and the fourth metal layer 222 are of the same layer, and the second metal layer 212 and the fourth metal layer 222 are made of the same material, which is aluminum or copper.

[0088] The first metal layer 211 and the second metal layer 212 in the display area form the first gate 210 of the first thin-film transistor. The third metal layer 221 in the first area 223 in the GOA area forms the second gate 220 of the second thin-film transistor. The third metal layer 221 and the fourth metal layer 222 in the second area 224 form a scanning trace.

[0089] S13: As Figure 5 shown, the gate insulating layer 300 and the amorphous silicon layer 400 are sequentially deposited by the CVD process. The gate insulating layer 300 can be SiOx, SiNx, SiNx / SiOx, SiNOx, etc.

[0090] S14: As Figure 6As shown, the amorphous silicon in the first region 223 is subjected to two laser annealing treatments using a laser annealing device 440. Among them, the first laser annealing uses a low energy density to dehydrogenate the amorphous silicon in the annealing region. The second laser annealing uses a high energy density to anneal and crystallize the amorphous silicon in the annealing region to form polycrystalline silicon (Poly-Si), that is, low-temperature polycrystalline silicon LTPS.

[0091] S15: As Figure 7 shown, a dry etching process is used to pattern the amorphous silicon and polycrystalline silicon layers to form patterns of the first active layer 410 and the second active layer 420. The first active layer 410 is opposite to the first gate 210 in the display region, and the second active layer 420 is opposite to the second gate 220 in the GOA region. The first active layer 410 is amorphous silicon, and the second active layer 420 is Poly-Si (LTPS).

[0092] S16: As Figure 8 shown, an ohmic contact layer N+ 430 is deposited on the first active layer 410 and the second active layer 420 using a CVD process. The N+ is an amorphous silicon layer doped with PH3. Then, a source-drain metal layer 500 is deposited on the ohmic contact layer N+ 430 using a PVD process.

[0093] S17: As Figure 9 shown, a 1W1D (WET etch and Dry etch) process is used to pattern the source-drain metal layer 500 and the ohmic contact layer N+ 430 to form a first N+ doping pattern 431 on both sides of the first active layer 410 and a second N+ doping pattern 432 on both sides of the second active layer 420, and to form patterns of a first source electrode 510, a first drain electrode 520, a second source electrode 530, and a second drain electrode 540. The first source electrode 510 and the first drain electrode 520 are respectively electrically connected to the N+ doping regions on both sides of the first active layer 410, and the second source electrode 530 and the second drain electrode 540 are respectively electrically connected to the N+ doping regions on both sides of the second active layer 420.

[0094] S18: As Figure 10 shown, a passivation layer 600 and an electrode layer are sequentially deposited on the first source electrode 510, the first drain electrode 520, the second source electrode 530, and the second drain electrode 540, and the passivation layer 600 is patterned to form a first via hole and a second via hole penetrating the passivation layer 600, and the electrode layer is patterned to form patterns of a first electrode layer 710 and a second electrode layer 720. The first electrode layer 710 is electrically connected to the first drain electrode 520 through the first via hole, and the second electrode layer 720 is electrically connected to the second drain electrode 540 through the second via hole.

[0095] In this embodiment, the array substrate adopts a conventional amorphous silicon process in the display area and a low-temperature polycrystalline silicon process with high mobility and high stability in the GOA area, enabling a significant improvement in the performance of the array substrate and providing a new technical route for high-end large-size products. At the same time, the entire process has high compatibility with the existing amorphous silicon mass production process of the BCE structure, and only one crystallization process needs to be added after the amorphous silicon film formation. The process is simple and the cost is low.

[0096] In another embodiment, the array substrate includes a display area and a peripheral area, and the peripheral area includes a gate-on-array (GOA) gate driving circuit (GOA area).

[0097] The method for manufacturing the array substrate includes the following steps:

[0098] S20: As Figure 11 shown, on the substrate 100, a first gate metal sub-layer 201 and a second gate metal sub-layer 202 are sequentially deposited by a PVD process. The first gate metal sub-layer 201 is a high-temperature resistant layer, and the second gate metal sub-layer 202 is a main layer. The material of the first gate metal sub-layer 201 can be a high-temperature resistant metal such as Mo, Ti, or a MoTi alloy, etc. The deposition thickness of the first gate metal sub-layer 201 is 50 - 400 angstroms, and the material of the second gate metal sub-layer 202 can be Al or Cu, etc.

[0099] S21: As Figure 12 shown, a differential patterning is performed on the first gate metal sub-layer 201 and the second gate metal sub-layer 202 by using a Half Tone Mask process. The mask 800 used in the Half Tone Mask process includes a light-transmitting area 810 and a first light-blocking area 820 in the display area, and includes a light-transmitting area 810, a partially light-transmitting area 830, and a second light-blocking area 840 in the GOA area. During the photomask process, the light intensity of the incident light passing through different areas of the mask 800 is different. In the GOA area, the photoresist PR corresponding to the partially light-transmitting area 830 is thinner than the photoresist PR corresponding to the second light-blocking area 840, so as to simultaneously perform differential patterning on the first gate metal sub-layer 201 and the second gate metal sub-layer 202.

[0100] S22: As Figure 13As shown, after patterning the first gate metal sub-layer 201, patterns of the first metal layer 211 and the third metal layer 221 are formed. After patterning the second gate metal sub-layer 202, patterns of the second metal layer 212 and the fourth metal layer 222 are formed. Among them, the second metal layer 212 covers the first metal layer 211. The third metal layer 221 includes a first region 223 and a second region 224. The fourth metal layer 222 covers the third metal layer 221 of the second region 224.

[0101] The first metal layer 211 and the third metal layer 221 are on the same layer, and the first metal layer 211 and the third metal layer 221 are made of the same material, which is a high-temperature resistant metal such as molybdenum, titanium or molybdenum-titanium alloy. The thickness of the first metal layer 211 and the third metal layer 221 is the same, which is 50 - 400 angstroms.

[0102] The second metal layer 212 and the fourth metal layer 222 are on the same layer, and the second metal layer 212 and the fourth metal layer 222 are made of the same material, which is aluminum or copper.

[0103] The first metal layer 211 and the second metal layer 212 in the display area form the first gate 210 of the first thin-film transistor. The third metal layer 221 in the first region 223 of the GOA area forms the second gate 220 of the second thin-film transistor. The third metal layer 221 and the fourth metal layer 222 in the second region 224 form a scan line.

[0104] S23: As Figure 14 shown, the gate insulating layer 300 and the amorphous silicon layer 400 are sequentially deposited by CVD process. The gate insulating layer 300 can be SiOx, SiNx, SiNx / SiOx, SiNOx, etc.

[0105] S24: As Figure 15 shown, the ohmic contact layer N+ 430 is deposited by CVD process. The N+ is an amorphous silicon layer doped with PH3. Then, the ohmic contact layer N+ 430 is patterned by dry etching process to form a first N+ doping pattern 431 in the display area and a second N+ doping pattern 432 in the first region 223.

[0106] S25: As Figure 16As shown in the figure, the amorphous silicon and N+ layer in the first region 223 are subjected to two laser annealing treatments by a laser annealing device 440. Among them, the first laser annealing uses a low energy density to dehydrogenate the amorphous silicon and N+ layer in the annealing region. The second laser annealing uses a high energy density to anneal and crystallize the amorphous silicon and N+ layer in the annealing region to form polycrystalline silicon (Poly-Si). In this solution, N+ and the amorphous silicon layer are co-crystallized into polycrystalline silicon (Poly-Si), so that the interface characteristics between the film layers are better, which is conducive to achieving better device characteristics.

[0107] S26: As Figure 17 shown in the figure, a dry etching process is used to pattern the amorphous silicon and polycrystalline silicon layers to form patterns of the first active layer 410 and the second active layer 420. The first active layer 410 is located opposite the first gate 210 in the display region, and the second active layer 420 is located opposite the second gate 220 in the GOA region. The first active layer 410 is amorphous silicon, and the second active layer 420 is Poly-Si (LTPS).

[0108] S27: As Figure 18 shown in the figure, a wet etching process is used to pattern the source-drain metal layer 500 to form patterns of the first source electrode 510, the first drain electrode 520, the second source electrode 530, and the second drain electrode 540. The first source electrode 510 and the first drain electrode 520 are respectively electrically connected to the N+ doped regions on both sides of the first active layer 410, and the second source electrode 530 and the second drain electrode 540 are respectively electrically connected to the N+ doped regions on both sides of the second active layer 420.

[0109] S28: As Figure 19 shown in the figure, a passivation layer 600 and an electrode layer are sequentially deposited on the first source electrode 510, the first drain electrode 520, the second source electrode 530, and the second drain electrode 540. The passivation layer 600 is patterned to form a first via hole and a second via hole penetrating the passivation layer 600, and the electrode layer is patterned to form patterns of the first electrode layer 710 and the second electrode layer 720. The first electrode layer 710 is electrically connected to the first source electrode 510 or the first drain electrode 520 through the first via hole, and the second electrode layer 720 is electrically connected to the second source electrode 530 or the second drain electrode 540 through the second via hole.

[0110] In this embodiment, an ohmic contact layer N+ 430 is first deposited before the amorphous silicon is crystallized into polycrystalline silicon. N+ and the amorphous silicon are co-crystallized into polycrystalline silicon (poly-Si), so that the interface characteristics between the two film layers are better and the electrical properties of the device are better.

[0111] The present application provides an array substrate and a manufacturing method thereof. The array substrate provided by the present application is a hybrid TFT type array substrate, including a first thin film transistor located in the display area and a second thin film transistor located in the peripheral area. The first thin film transistor is an amorphous silicon thin film transistor, and the second thin film transistor is a low temperature polycrystalline silicon thin film transistor. Moreover, a first active layer of the first thin film transistor and a second active layer of the second thin film transistor are arranged on the same layer. The array substrate of the present application adopts the amorphous silicon process commonly used in the existing mass production process in the display area and adopts the low temperature polycrystalline silicon process with high mobility and high stability in the peripheral area. The whole manufacturing process of this array substrate has high compatibility with the existing amorphous silicon mass production process. It only needs to add a crystallization process after the amorphous silicon film formation of the first active layer and the second active layer to make the amorphous silicon of the second active layer crystallize to form polycrystalline silicon. And the first active layer of the first thin film transistor and the second active layer of the second thin film transistor are arranged on the same layer, which can reduce the photomask and simplify the process.

[0112] In summary, although the present application has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. An array substrate, characterized in that, It includes a display area and a peripheral area. A first thin-film transistor is provided in the display area, and a second thin-film transistor is provided in the peripheral area. The array substrate includes: A substrate; A first active layer of the first thin-film transistor, which is located on the substrate and is amorphous silicon; A second active layer of the second thin-film transistor, which is located on the substrate and is low-temperature polycrystalline silicon. The first active layer and the second active layer are arranged on the same layer; An ohmic contact layer, which includes a first N+ doping pattern and a second N+ doping pattern. The first N+ doping pattern is located on the side of the first active layer away from the substrate, and the second N+ doping pattern is located on the side of the second active layer away from the substrate. The second N+ doping pattern and the second active layer are crystallized together to form polycrystalline silicon, and the interface characteristics between the second N+ doping pattern and the second active layer are better than the interface characteristics between the first N+ doping pattern and the first active layer.

2. The array substrate according to claim 1, wherein The first thin-film transistor further includes a first gate opposite to the first active layer. The first gate includes a first metal layer and a second metal layer located on the first metal layer; The second thin-film transistor further includes a second gate opposite to the second active layer. The second gate includes at least part of a third metal layer; Wherein, the temperature tolerance of the first metal layer and the third metal layer is higher than that of the second metal layer, and the resistivity of the second metal layer is lower than that of the first metal layer.

3. The array substrate according to claim 2, wherein The third metal layer includes a first region and a second region located on at least one side of the first region. The third metal layer in the first region is opposite to the second active layer, and a fourth metal layer is provided on the third metal layer in the second region. The third metal layer in the second region and the fourth metal layer form a scanning trace; Wherein, the resistivity of the fourth metal layer is lower than that of the third metal layer.

4. The array substrate according to claim 3, wherein, The first metal layer and the third metal layer are arranged on the same layer, and the first metal layer and the third metal layer are made of the same material, which is molybdenum, titanium or a molybdenum-titanium alloy.

5. The array substrate according to claim 3, wherein, The second metal layer and the fourth metal layer are arranged on the same layer, and the second metal layer and the fourth metal layer are made of the same material, which is aluminum or copper.

6. The array substrate according to claim 3, characterized in that The peripheral area includes a GOA gate driving circuit, and the GOA gate driving circuit includes the second thin-film transistor and the scanning trace.

7. The array substrate according to any one of claims 2-6, characterized in that, The array substrate further includes a gate insulating layer. The first thin-film transistor further includes a first source electrode and a first drain electrode, and the second thin-film transistor further includes a second source electrode and a second drain electrode; Wherein, the first gate and the second gate are located on one side of the substrate, the gate insulating layer is located on the side of the first gate and the second gate away from the substrate, the first active layer and the second active layer are located on the side of the gate insulating layer away from the first gate and the second gate, the first source electrode and the first drain electrode are located on the side of the first active layer away from the gate insulating layer and are electrically connected to the first active layer, and the second source electrode and the second drain electrode are located on the side of the second active layer away from the gate insulating layer and are electrically connected to the second active layer.

8. A method for preparing an array substrate, characterized in that, The array substrate includes a display area and a peripheral area, and the method includes: Forming a first gate and a second gate on the substrate, the first gate is located in the display area, and the second gate is located in the peripheral area; the first gate includes a first metal layer and a second metal layer located on the first metal layer, and the second gate includes at least a part of a third metal layer; wherein, the temperature tolerance of the first metal layer and the third metal layer is higher than that of the second metal layer, and the resistivity of the second metal layer is lower than that of the first metal layer; Forming a gate insulating layer on the substrate, the first gate and the second gate; Forming a first active layer and a second active layer on the gate insulating layer; wherein, the first active layer is amorphous silicon and is opposite to the first gate, and the second active layer is low-temperature polycrystalline silicon and is opposite to the second gate; Forming a first N+ doping pattern on the surface of the first active layer away from the substrate, and forming a second N+ doping pattern on the surface of the second active layer away from the substrate, and the second N+ doping pattern and the second active layer are crystallized together to form polycrystalline silicon, and the interface characteristics between the second N+ doping pattern and the second active layer are better than those between the first N+ doping pattern and the first active layer; Forming a first source electrode and a first drain electrode on the first active layer, and forming a second source electrode and a second drain electrode on the second active layer; wherein, the first source electrode and the first drain electrode are electrically connected to the first active layer, and the second source electrode and the second drain electrode are electrically connected to the second active layer.

9. The method for manufacturing an array substrate according to claim 8, wherein, The third metal layer includes a first region and a second region located on at least one side of the first region, the third metal layer in the first region is opposite to the second active layer, and a fourth metal layer is provided on the third metal layer in the second region, and the third metal layer in the second region and the fourth metal layer form a scanning trace; Wherein, the resistivity of the fourth metal layer is lower than that of the third metal layer.

10. The method for preparing an array substrate according to claim 9, wherein The first metal layer and the third metal layer are arranged on the same layer, and the first metal layer and the third metal layer are made of the same material, which is molybdenum, titanium or a molybdenum-titanium alloy; The second metal layer and the fourth metal layer are arranged on the same layer, and the second metal layer and the fourth metal layer are made of the same material, which is aluminum or copper.

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