Semiconductor device, method of manufacture, power conversion circuit, and vehicle

Abstract

The application provides a semiconductor device, a preparation method, a power conversion circuit and a vehicle, which comprise an N-type semiconductor substrate, a drift layer, a plurality of gate trenches arranged at intervals, a gate, an interlayer dielectric layer, a source and a drain. The drift layer is arranged on the semiconductor substrate. The plurality of gate trenches extend along a first direction parallel to a plane in which the semiconductor substrate is located, and are arranged along a second direction parallel to the plane in which the semiconductor substrate is located. The gate comprises a first gate and a second gate which are in contact with each other. The first gate is arranged in the gate trench through the gate dielectric layer. The second gate is arranged on the top of the drift layer through the gate dielectric layer. The interlayer dielectric layer is arranged on the side of the gate away from the semiconductor substrate. The source is arranged on the side of the interlayer dielectric layer away from the semiconductor substrate. The drain is arranged on the side of the semiconductor substrate away from the drift layer, so that the total on-resistance of the device is reduced, the electric field of the gate dielectric layer at the bottom of the gate trench is shielded, and the robustness of the device in operation is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor devices, fabrication methods, power conversion circuits, and vehicles. Background Technology

[0002] Silicon carbide (SiC) materials offer advantages over silicon (Si) materials, including a wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher electron saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) made from SiC exhibit higher breakdown voltage and lower on-state voltage drop compared to insulated-gate bipolar transistors (IGBTs) made from Si. Furthermore, the unipolar conductivity of SiC MOSFETs results in faster switching speeds, lower conduction losses, and lower switching losses compared to Si IGBTs. Therefore, SiC MOSFETs have already replaced Si IGBTs in some applications, such as automotive microcontroller units (MCUs) and on-board battery chargers (OBCs).

[0003] Compared to conventional planar gate devices, SiC MOSFET devices employing trench gate structures embed the gate within the SiC body, shifting the conductive channel from a planar orientation to a vertical one. This significantly reduces the device's cell size and greatly increases the conductive channel density, thereby substantially reducing the chip's on-resistance and improving current-carrying capacity. Trench gate structures have become the mainstream technology for future devices. However, in trench-gate SiC MOSFET devices, there is a significant contradiction between the channel resistance and the junction field-effect transistor (JFET) resistance. (Refer to...) Figure 1 The horizontal axis represents the cell size, and the vertical axis represents the resistance. Figure 1It is known that by reducing the spacing of the trench gate structure in SiC MOSFET devices, the cell size of the SiC MOSFET device can be reduced, the conductive channel density can be increased, and the channel resistance can be reduced. However, at the same time, the current-carrying width of the JFET region will also decrease, leading to an increase in the JFET region resistance. Consequently, the overall on-resistance of the SiC MOSFET device will increase, reducing device performance and increasing chip losses. Furthermore, in SiC MOSFET devices with trench gate structures, the gate dielectric layer at the bottom and corners of the trench gate structure will be subjected to extremely high electric field strength during device operation. These are weak points for electric field breakdown and are prone to long-term reliability failure. Therefore, effectively shielding the gate dielectric layer from high electric field stress is crucial for the robustness and reliability design of the device. Summary of the Invention

[0004] This application provides a semiconductor device, a fabrication method, a power conversion circuit, and a vehicle, which are used to reduce the total on-resistance of the device, improve device performance, reduce device losses, and improve the robustness of device operation.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, comprising: an N-type semiconductor substrate, a drift layer, a plurality of gate trenches spaced apart from each other, a gate, an interlayer dielectric layer, a source, and a drain. The drift layer is disposed on the semiconductor substrate, and the plurality of gate trenches extend along a first direction parallel to the plane of the semiconductor substrate and are arranged along a second direction parallel to the plane of the semiconductor substrate. The gate includes a first gate and a second gate that are in contact with each other. The first gate is filled in the gate trench through the gate dielectric layer, and the second gate is disposed on top of the drift layer through the gate dielectric layer. The interlayer dielectric layer covers the side of the gate away from the semiconductor substrate, the source is disposed on the side of the interlayer dielectric layer away from the semiconductor substrate, and the drain is disposed on the side of the semiconductor substrate away from the drift layer.

[0006] Furthermore, the drift layer includes: a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on a semiconductor substrate, and a first P-type semiconductor region disposed on two sides of the drift layer, i.e., the second P-type semiconductor region is disposed between the first N-type semiconductor region and the source region. The first P-type semiconductor region extends from the top of the drift layer into the first N-type semiconductor region along a third direction perpendicular to the plane of the semiconductor substrate. Multiple gate trenches extend into the first N-type semiconductor region along a third direction, and the distance between the bottom of the first P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the gate trench and the top of the drift layer. An interlayer dielectric layer covers a first portion of the gate and source regions, exposing a second portion of the first P-type semiconductor region and the source region (equivalent to having a contact hole in the interlayer dielectric layer corresponding to the second portion of the first P-type semiconductor region and the source region). The source covers the interlayer dielectric layer, the first P-type semiconductor region, and the second portion of the source region, so that the source can contact the second portion of the first P-type semiconductor region and the source region to transmit signals. The drain is also covered by a semiconductor substrate, and signals can be transmitted between the source and drain when the channel is on.

[0007] In some embodiments provided in this application, the semiconductor substrate and drift layer are made of SiC. Therefore, the semiconductor device provided in the embodiments of this application can be a SiC MOSFET.

[0008] The semiconductor device provided in this application embodiment fabricates a closely spaced array of gate trenches in a drift layer, and a first gate is disposed in the gate trenches. The region where the second P-type semiconductor region intersects with the gate dielectric layer forms a channel. Furthermore, the source can contact the source region, achieving a source-source region connection, thereby enabling signal transmission between the source and drain when the gate-controlled channel is turned on. Additionally, the extension direction of the contact hole in the interlayer dielectric layer is a second direction, and the extension direction of the gate trench (or first gate) is a first direction. Therefore, the extension direction of the contact hole is perpendicular to the extension direction of the gate trench (or first gate), placing the contact hole perpendicular to the direction of the gate trench (or first gate). Compared to the prior art where the gate trench and contact hole are parallel, the semiconductor device provided in this application embodiment reduces the restriction of the contact hole on the trench spacing C of adjacent gate trenches in the second direction, allowing for a more compact gate trench fabrication, i.e., a more compact first gate. This facilitates reducing the trench spacing between gate trenches, thereby miniaturizing the cell, improving cell density, and increasing the device's current carrying capacity. Therefore, the gate trench array density of the semiconductor device provided in this application embodiment can be much higher than the gate trench array density of the device structure in the prior art, thereby increasing the channel density of the SiC MOSFET with trench gate structure, significantly reducing the total on-resistance per unit area of ​​the device, improving the current carrying capacity and device performance, and reducing device losses.

[0009] Furthermore, in this application, the distance between the bottom of the first P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the gate trench and the top of the drift layer. That is, the depth of the first P-type semiconductor region in the third direction is greater than the depth of the gate trench in the third direction. Additionally, the source can also contact the first P-type semiconductor region through a contact hole, achieving a connection between the source and the first P-type semiconductor region. In other words, in this application, the source and the first P-type semiconductor region can be made conductive. In practical applications, when the SiC MOSFET device is operating, a voltage is applied to the source. Since the first P-type semiconductor region is connected to the source, the voltage applied to the source is input to the first P-type semiconductor region, giving it a corresponding voltage. This allows the first P-type semiconductor region to act as a shielding structure, effectively shielding the gate dielectric layer electric field at the bottom of the gate trench, thereby improving the robustness of the device operation.

[0010] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can be grounded and its drain can be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the ground voltage (0V). Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.

[0011] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.

[0012] In this application, the semiconductor substrate can be a single-crystal silicon carbide substrate doped with pentavalent elements. The drift layer can be formed by epitaxial growth of SiC material doped with the corresponding impurities. For example, the first N-type semiconductor region is a portion of the drift layer formed by epitaxial growth. The source region is an N-type semiconductor region, and the source region can be formed by ion implantation process to dope the drift layer with N-type impurities.

[0013] For example, in this application, the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).

[0014] For example, in this application, the doping concentration of the semiconductor substrate is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the source region is also greater than the doping concentration of the first N-type semiconductor region. Optionally, the doping concentration of the semiconductor substrate is similar to or the same as the doping concentration of the source region. Of course, the doping concentration of the semiconductor substrate and the doping concentration of the source region can also be different; for example, the doping concentration of the semiconductor substrate may be greater than or less than the doping concentration of the source region, which is not limited here.

[0015] In this application, the second P-type semiconductor region can also be formed by epitaxially growing SiC material doped with P-type impurities; that is, the second P-type semiconductor region can also be a portion of the drift layer formed by epitaxial growth. Alternatively, the second P-type semiconductor region can also be formed by ion implantation, through P-type impurity doping of the drift layer. This application does not limit the formation process of the second P-type semiconductor region.

[0016] For example, in this application, the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0017] This application does not limit the material of the gate. For example, the gate material can be polycrystalline silicon or other materials with good electrical conductivity, such as metals (e.g., W, Al, Ti, Cu, Mo, or Pt).

[0018] This application does not limit the material used to form the interlayer dielectric layer. For example, the material used to form the interlayer dielectric layer can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0019] This application does not limit the materials used to form the source and drain electrodes. For example, the materials used to form the source and drain electrodes can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt.

[0020] In this application, the first direction, the second direction, and the third direction are arranged intersecting each other. For example, the first direction, the second direction, and the third direction are arranged perpendicular to each other.

[0021] In some possible embodiments of this application, the orthogonal projection of the first P-type semiconductor region onto a first plane formed by the second direction and the third direction covers the orthogonal projection of the gate trench onto the first plane. The first plane formed by the second direction and the third direction is equivalent to being parallel to the second direction and the third direction.

[0022] In some possible embodiments of this application, the first P-type semiconductor regions respectively disposed on the same side of the drift layer can be configured as a single integral region. That is, the first P-type semiconductor regions disposed on the first side of the same trench group are configured as a single integral region, and the first P-type semiconductor regions disposed on the second side of the same trench group are also configured as a single integral region. Furthermore, the orthographic projection of each first P-type semiconductor region onto the semiconductor substrate is a strip-shaped region extending along the second direction. Also, each first P-type semiconductor region extends along the second direction Y from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench.

[0023] In some possible embodiments of this application, the first P-type semiconductor regions respectively disposed on the same side of the drift layer may be multiple regions, and the multiple first P-type semiconductor regions disposed on the same sidewall of the multiple gate trenches and the third portion region of the source region may be spaced apart from each other. That is, the orthogonal projection of the third portion region of the source region on the semiconductor substrate is between the orthogonal projections of two adjacent first P-type semiconductor regions disposed on the same sidewall of the multiple gate trenches onto the semiconductor substrate. For example, when the multiple gate trenches are divided into two trench groups, multiple first P-type semiconductor regions are disposed on the first side of one of the two trench groups, and multiple first P-type semiconductor regions are also disposed on the second side of the trench group. Multiple first P-type semiconductor regions are also disposed on the first side of the other trench group, and multiple first P-type semiconductor regions are also disposed on the second side of the trench group.

[0024] In some possible embodiments of this application, the edge of the orthographic projection of the first P-type semiconductor region on the first plane can be disposed outside the edge of the orthographic projection of the sidewall of the corresponding gate trench on the first plane. For example, when multiple gate trenches are divided into two trench groups, the edge of the orthographic projection of each first P-type semiconductor region on the first plane at the first side of one of the two trench groups is disposed outside the edge of the orthographic projection of the first sidewall of the corresponding gate trench in that trench group on the first plane. The rest can be deduced similarly and will not be elaborated further here.

[0025] In some possible embodiments of this application, the edge of the orthographic projection of the first P-type semiconductor region on the first plane may overlap with the orthographic projection of the sidewall of the corresponding gate trench on the first plane. For example, when multiple gate trenches are divided into two trench groups, the edge of the orthographic projection of the first P-type semiconductor region on the first plane at the first side of one of the trench groups overlaps with the orthographic projection of the first sidewall of the corresponding gate trench in that trench group on the first plane. The rest can be deduced similarly and will not be elaborated further here.

[0026] In some possible embodiments of this application, the orthographic projection of the first P-type semiconductor region onto the semiconductor substrate and the orthographic projection of the gate trench onto the semiconductor substrate may not overlap. That is, in the third direction, there is no overlapping region between each first P-type semiconductor region and each gate trench.

[0027] In some possible embodiments of this application, a fourth portion of the source region may be formed between the gate trench and the corresponding first P-type semiconductor region. That is, the fourth portion of the source region is formed between the orthogonal projection of the first and second sidewalls of the gate trench onto the semiconductor substrate and the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate. In other words, the gate dielectric layer disposed on the surfaces of the first and second sidewalls of the gate trench is not in contact with the first P-type semiconductor region.

[0028] In some possible embodiments of this application, when there are multiple first P-type semiconductor regions disposed on the same side of the drift layer, the gate trench contacts the corresponding first P-type semiconductor region through the corresponding gate dielectric layer. For example, when there are multiple first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches, and the multiple first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches are spaced apart from the third portion of the source region, the orthographic projection of the gate dielectric layer of the first and second sidewalls of the gate trench onto the semiconductor substrate contacts the orthographic projection of the corresponding first P-type semiconductor region onto the semiconductor substrate.

[0029] Of course, when the first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches are multiple regions, and the multiple first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches are spaced apart from the third portion of the source region, a fourth portion of the source region can also be provided between the gate trench and the corresponding first P-type semiconductor region. That is, the orthogonal projection of the first and second sidewalls of the gate trench onto the semiconductor substrate and the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate are provided between the orthogonal projection of the fourth portion of the source region onto the semiconductor substrate, that is, the gate dielectric layer disposed on the surface of the first and second sidewalls of the gate trench is not in contact with the first P-type semiconductor region.

[0030] In some possible embodiments of this application, the drift layer further includes a first shielding trench, which is disposed on two sides of the drift layer, and the sidewalls and bottom of the first shielding trench are provided with first P-type semiconductor regions. The first shielding trench extends from the top of the drift layer into the first N-type semiconductor region along a third direction, and the first and second sidewalls of the gate trench are respectively provided with first shielding trenches on the side opposite to the corresponding first gate. Furthermore, the sidewalls and bottom of the first shielding trench are respectively provided with P-type semiconductor regions, and the P-type semiconductor regions provided on the sidewalls and bottom of each first shielding trench can serve as first P-type semiconductor regions.

[0031] For example, the first shielding trench disposed on the same side of the drift layer can be one. For instance, the first shielding trench disposed on the same side of the same sidewall among the first and second sidewalls of a plurality of gate trenches can be one. Furthermore, the orthogonal projection of the first shielding trench onto the semiconductor substrate can be a strip-shaped region extending along the second direction, which can make the orthogonal projection of the formed first P-type semiconductor region onto the semiconductor substrate a strip-shaped region extending along the second direction.

[0032] For example, there may be multiple first shielding trenches disposed on the same side of the drift layer. For instance, multiple first shielding trenches may be disposed on the same side of the same sidewall among the first and second sidewalls of multiple gate trenches, and each first shielding trench may have a P-type semiconductor region disposed on its sidewall and bottom. This P-type semiconductor region can serve as the first P-type semiconductor region.

[0033] In some possible embodiments of this application, each first shielding trench is filled with a filler material, and this application does not limit the filler material. Exemplarily, the filler material can be the gate material, that is, each first shielding trench can be filled with the gate material. For example, in actual process fabrication, when forming the gate, the gate material can be filled into the first shielding trench. Of course, each first shielding trench can also be filled with the material of the interlayer dielectric layer. Alternatively, each first shielding trench can also be filled with the material of the source or drain electrode.

[0034] In some possible embodiments of this application, the drift layer further includes second shielding trenches disposed on two sides of the drift layer, with the first P-type semiconductor region disposed within the second shielding trenches. For example, the plurality of second shielding trenches extend from the top of the drift layer into the first N-type semiconductor region along a third direction. Furthermore, the first and second sidewalls of the gate trenches, on the side facing away from the corresponding first gate, are respectively provided with second shielding trenches. Each second shielding trench is filled with a P-type epitaxial layer, which serves as the first P-type semiconductor region. That is, the first P-type semiconductor region can be a P-type epitaxial layer disposed within the second shielding trench.

[0035] For example, the second shielding trench disposed on the same side of the drift layer can be one. For instance, the second shielding trench disposed on the same side of the same sidewall of the first and second sidewalls of a plurality of gate trenches can be one, and the orthogonal projection of the second shielding trench onto the semiconductor substrate can be a strip-shaped region extending along the second direction, so that the orthogonal projection of the formed first P-type semiconductor region onto the semiconductor substrate can be a strip-shaped region extending along the second direction.

[0036] For example, there can be multiple second shielding trenches disposed on the same side of the drift layer. For instance, multiple second shielding trenches can be disposed on the same side of the same sidewall of the first and second sidewalls of the multiple gate trenches, and each second shielding trench has a P-type epitaxial layer disposed on its sidewall. This P-type epitaxial layer can serve as the first P-type semiconductor region.

[0037] This application does not limit the material used to form the P-type epitaxial layer. For example, the material used to form the P-type epitaxial layer may include SiC doped with P-type impurities.

[0038] In some possible embodiments of this application, multiple gate trenches in a semiconductor device can be divided into one or more trench groups, and two or more contact holes can be provided. Furthermore, a trench group is provided between two adjacent contact holes. This allows for more uniform signal flow. For example, multiple gate trenches in a semiconductor device can be divided into multiple trench groups, and multiple contact holes are also provided. These multiple trench groups are arranged along a first direction, and the multiple contact holes are also arranged along the first direction.

[0039] For example, the number of gate trenches in different trench groups can be the same. This allows for a uniform distribution of the gate trenches. Alternatively, the number of gate trenches can be the same in some trench groups, while the number of gate trenches differs in the remaining trench groups. Alternatively, the number of gate trenches in different trench groups can also differ. In practical applications, the specific number of gate trenches in a trench group can be determined according to the needs of the application, and this application does not limit this.

[0040] In some possible embodiments of this application, in the second direction, the two gate trenches at the edge of the trench group are respectively defined as the first edge trench and the second edge trench, and the contact hole extends from the side of the first edge trench away from the second edge trench along the second direction to the side of the second edge trench away from the first edge trench.

[0041] This application does not limit the shape of the region enclosed by the orthographic projection of each trench group onto the semiconductor substrate. In some examples, the region enclosed by the orthographic projection of each trench group onto the semiconductor substrate is rectangular. For example, the rectangle can be a rectangle or a square.

[0042] In other examples, when multiple trench groups are configured, the area enclosed by the orthographic projection of each trench group onto the semiconductor substrate is rectangular. Furthermore, the area enclosed by the orthographic projection of all trench groups onto the semiconductor substrate can be one of the following polygons: square, rectangle, hexagon, octagon, etc., without limitation.

[0043] In some possible embodiments of this application, when there are multiple trench groups, adjacent trench groups share a first P-type semiconductor region disposed between the adjacent trench groups. Exemplarily, adjacent trench groups share a first shielding trench or a second shielding trench disposed between the adjacent trench groups. Further, adjacent trench groups share the third and fourth sidewalls and the bottom of the first or second shielding trench disposed between the adjacent trench groups, as well as the P-type semiconductor region disposed thereunder.

[0044] In some possible embodiments of this application, the drift layer further includes a second N-type semiconductor region disposed between the first N-type semiconductor region and the second P-type semiconductor region. Furthermore, the doping concentration of the second N-type semiconductor region is greater than that of the first N-type semiconductor region, and the doping concentration of the second N-type semiconductor region is less than that of the source region.

[0045] This application does not limit the doping concentration of the second N-type semiconductor region; the doping concentration can meet the above requirements.

[0046] In this application, by providing a second N-type semiconductor region in the drift layer, the diffusion resistance of the current in the device at the upper end of the drift layer can be reduced.

[0047] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, comprising the following steps:

[0048] A drift layer is epitaxially grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are formed in the drift layer, which are sequentially stacked on the semiconductor substrate. That is, the second P-type semiconductor region is disposed between the first N-type semiconductor region and the source region.

[0049] On both sides of the drift layer, a first P-type semiconductor region is formed, and the first P-type semiconductor region extends from the top of the drift layer into the first N-type semiconductor region along a third direction perpendicular to the plane where the semiconductor substrate is located.

[0050] The drift layer is etched to form a plurality of gate trenches that are spaced apart from each other and extend upward along a third direction from the top of the drift layer to the first N-type semiconductor region. The plurality of gate trenches extend along a first direction parallel to the plane of the semiconductor substrate and are arranged along a second direction parallel to the plane of the semiconductor substrate. The distance between the bottom of the first P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the gate trench and the top of the drift layer. The first direction, the second direction and the third direction are intersected.

[0051] A gate dielectric layer is formed in the gate trench.

[0052] A first gate is formed in a gate trench in which a gate dielectric layer is formed, and a second gate is formed on top of a drift layer, and the first gate and the second gate are brought into contact with each other.

[0053] An interlayer dielectric layer covering the entire drift layer is formed on the gate.

[0054] The interlayer dielectric layer is etched to expose a second portion of the first P-type semiconductor region and the source region, and the interlayer dielectric layer covers a first portion of the source region and completely covers the gate.

[0055] A source is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, such that the source is in contact with a second portion of the first P-type semiconductor region and the source region, and a drain is formed on the side of the semiconductor substrate away from the drift layer.

[0056] In the first direction, each of the plurality of gate trenches has a first sidewall and a second sidewall disposed opposite to each other, and a first P-type semiconductor region is disposed on the side of the first sidewall and the second sidewall away from the corresponding first gate, and the distance between the bottom of the first P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the gate trench and the top of the drift layer.

[0057] In some possible embodiments of this application, epitaxially growing a drift layer on an N-type semiconductor substrate, and forming a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate in the drift layer, may include the following steps:

[0058] First, an epitaxial layer is grown on an N-type semiconductor substrate using an epitaxial process. For example, an epitaxial layer of SiC material doped with N-type impurities is grown on an N-type SiC semiconductor substrate to form a drift layer of a predetermined thickness. This application does not limit the specific value of the predetermined thickness. In practical applications, the specific value of the predetermined thickness can be determined according to the requirements of the actual application environment.

[0059] Subsequently, ion implantation is performed in a portion of the drift layer to form a second P-type semiconductor region and a source region. Regions in the drift layer not implanted with ions form a first N-type semiconductor region, with the second P-type semiconductor region positioned between the first N-type semiconductor region and the source region. For example, firstly, ion implantation is used to dope the surface of the drift layer with P-type impurities to form a second P-type semiconductor region. Then, a first mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. A suitable etching process, either dry or wet, is used to etch the first mask layer, forming a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Next, ion implantation is used to dope the surface of the drift layer with N-type impurities to form the source region. Finally, the first mask layer is removed. Alternatively, first, an ion implantation process is used to dope the surface of the drift layer with P-type impurities to form a second P-type semiconductor region. Then, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region.

[0060] In some possible embodiments of this application, a drift layer is epitaxially grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are formed in the drift layer. This may also include the following steps:

[0061] First, an epitaxial layer of a first predetermined thickness is grown on an N-type semiconductor substrate using an epitaxial process. For example, an epitaxial process is used to grow SiC material doped with N-type impurities on an N-type SiC semiconductor substrate to form a drift layer reaching the first predetermined thickness. This application does not limit the specific value of the first predetermined thickness. In practical applications, the specific value of the first predetermined thickness can be determined according to the requirements of the actual application environment.

[0062] Subsequently, an epitaxial growth process is used to epitaxially grow a second P-type semiconductor region of a second predetermined thickness on a drift layer of a first predetermined thickness. For example, an epitaxial growth process is used to epitaxially grow SiC material doped with P-type impurities on the drift layer to form a second P-type semiconductor region reaching the second predetermined thickness. This application does not limit the specific value of the second predetermined thickness. In practical applications, the specific value of the second predetermined thickness can be determined according to the requirements of the actual application environment.

[0063] Subsequently, epitaxial growth is continued on the second P-type semiconductor region using an epitaxial process until a drift layer reaching a third predetermined thickness is formed. For example, using an epitaxial process, SiC material doped with N-type impurities is further epitaxially grown on the second P-type semiconductor region to form a drift layer reaching the third predetermined thickness. This application does not limit the specific value of the third predetermined thickness. In practical applications, the specific value of the third predetermined thickness can be determined according to the requirements of the actual application environment.

[0064] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer to form a source region. The un-implanted regions of the drift layer form a first N-type semiconductor region, and a second P-type semiconductor region is positioned between the first N-type semiconductor region and the source region. For example, firstly, a first mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. A suitable etching process, either dry or wet, is used to etch the first mask layer, forming a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Then, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region. Finally, the first mask layer is removed. Alternatively, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region.

[0065] In some possible embodiments of this application, a drift layer is epitaxially grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are sequentially stacked on the semiconductor substrate in the drift layer. This may also include the following steps:

[0066] First, an epitaxial layer is grown on an N-type semiconductor substrate using an epitaxial process. For example, an epitaxial layer of SiC material doped with N-type impurities is grown on an N-type SiC semiconductor substrate to form a drift layer of a predetermined thickness. This application does not limit the specific value of the predetermined thickness. In practical applications, the specific value of the predetermined thickness can be determined according to the requirements of the actual application environment.

[0067] Subsequently, ion implantation is performed in a portion of the drift layer to form a second N-type semiconductor region, a second P-type semiconductor region, and a source region. The un-ion-implanted regions of the drift layer form a first N-type semiconductor region. The formed second P-type semiconductor region is positioned between the second N-type semiconductor region and the source region, and the first N-type semiconductor region is positioned between the second N-type semiconductor region and the semiconductor substrate. For example, firstly, N-type impurities are doped onto the surface of the drift layer using ion implantation to form a second N-type semiconductor region. Then, P-type impurities are doped onto the surface of the drift layer using ion implantation to form a second P-type semiconductor region. Next, a tenth mask layer is formed on the drift layer (this tenth mask layer can be a mask formed of silicon dioxide, polysilicon, or silicon nitride). A suitable etching process, either dry or wet, is used to etch the tenth mask layer, forming a tenth mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining tenth mask layer covers the rest of the drift layer. Next, ion implantation is used to dope the surface of the drift layer with N-type impurities to form the source region. Then, the tenth mask layer is removed. Alternatively, first, ion implantation is used to dope the surface of the drift layer with N-type impurities to form a second N-type semiconductor region. Then, ion implantation is used to dope the surface of the drift layer with P-type impurities to form a second P-type semiconductor region. Finally, ion implantation is used to dope the surface of the drift layer with N-type impurities to form the source region.

[0068] In some possible embodiments of this application, forming a first P-type semiconductor region on both sides of the drift layer may include the following steps:

[0069] First, the two sides of the drift layer are etched to form first shielding trenches extending upward along a third direction into the first N-type semiconductor region within the drift layer. Each first shielding trench is projected onto the semiconductor substrate as a strip-shaped region extending along a second direction. The first and second sidewalls of the gate trenches, facing away from the corresponding first gate, are respectively provided with first shielding trenches. For example, a second mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The second mask layer is etched using a suitable etching process, either dry or wet, to form a second mask opening. This opening exposes the corresponding region in the drift layer where the first shielding trenches need to be formed, while the remaining regions of the drift layer are covered by the remaining second mask layer. Subsequently, a dry etching process is used to etch the drift layer exposed through the opening of the second mask until it reaches the first N-type semiconductor region, so as to form a plurality of first shielding trenches extending in the second direction and arranged in the first direction in the drift layer.

[0070] Subsequently, ion implantation is performed on the sidewalls and bottom of each of the multiple first shielding trenches to form a first P-type semiconductor region. For example, ion implantation is used to dope the sidewalls and bottom of each first shielding trench with P-type impurities. Then, the second mask layer is removed. Afterwards, the semiconductor device with P-type impurity doping on the sidewalls and bottom of each first shielding trench is sequentially subjected to ion activation annealing and surface cleaning treatment to form the first P-type semiconductor region.

[0071] In this application, the first shielding trenches located on the same sidewall of each trench group can also be multiple trenches arranged in relation to each other. This implementation method can be referred to the above description, and will not be repeated here.

[0072] In some possible embodiments of this application, forming a first P-type semiconductor region on both sides of the drift layer may also include the following steps:

[0073] First, the two sides of the drift layer are etched to form a second shielding trench extending upward along a third direction into the first N-type semiconductor region. Multiple second shielding trenches are spaced apart on the same sidewall of each trench group. The orthographic projection of the first and second sidewalls of the gate trench onto the semiconductor substrate and the orthographic projection of the corresponding second shielding trench onto the semiconductor substrate form the orthographic projection of the fourth portion of the source region onto the semiconductor substrate. The first and second sidewalls of the gate trench have second shielding trenches on the side facing away from the corresponding first gate. For example, an eighth mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The eighth mask layer is etched using a suitable etching process, either dry or wet, to form an eighth mask opening. This opening exposes the corresponding region in the drift layer where the second shielding trench needs to be formed, while the remaining regions of the drift layer are covered by the retained eighth mask layer. Subsequently, a dry etching process is used to etch the drift layer exposed through the opening of the eighth mask until it is etched into the first N-type semiconductor region, so as to form a strip-shaped second shielding trench at the same sidewall of each trench group, and to make the first and second sidewalls of the gate trench have the orthographic projection of the semiconductor substrate on the semiconductor substrate between the orthographic projection of the corresponding second shielding trench on the semiconductor substrate and the orthographic projection of the fourth part of the source region on the semiconductor substrate.

[0074] Subsequently, a P-type epitaxial layer is epitaxially grown on the entire drift layer, and the epitaxial layer fills each of the plurality of second shielding trenches. For example, using an epitaxial process, a SiC material doped with P-type impurities is epitaxially grown on the entire drift layer where the second shielding trenches are formed, and the SiC material doped with P-type impurities fills each of the second shielding trenches as a P-type epitaxial layer. After filling the second shielding trenches with the SiC material doped with P-type impurities, the entire drift layer is covered with a SiC material film doped with P-type impurities.

[0075] Next, a planarization process is used to planarize the epitaxial layer. The process stops when the top of the drift layer (e.g., the source region of the drift layer) is exposed. The remaining epitaxial layers, except those in the second shielding trench, are removed. The epitaxial layer in the second shielding trench then serves as the first P-type semiconductor region. For example, a planarization process such as Chemical Mechanical Polishing (CMP) is used to planarize the epitaxial layer. The planarization process stops when the top of the drift layer (e.g., the source region of the drift layer) is exposed, retaining the epitaxial layer in the second shielding trench and removing the remaining epitaxial layers. The retained epitaxial layer then serves as the first P-type semiconductor region.

[0076] In this application, the second shielding trenches located on the same sidewall of each trench group can also be multiple trenches arranged in relation to each other. This implementation method can be referred to the above description, and will not be repeated here.

[0077] In some possible embodiments of this application, forming a first P-type semiconductor region on two sides of the drift layer may also include the following steps: using an ion implantation process to form a first P-type semiconductor region extending upwards along a third direction into a first N-type semiconductor region on two sides of the drift layer. For example, a ninth mask layer (which may be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The ninth mask layer is etched using a suitable etching process, either dry or wet, to form a ninth mask opening. The corresponding region in the drift layer where the first P-type semiconductor region needs to be formed is exposed through the ninth mask opening, while the remaining region of the drift layer is covered by the retained ninth mask layer. Then, an ion implantation process is used to dope the drift layer exposed through the ninth mask opening with P-type impurities. Afterwards, the ninth mask layer is removed. Then, the semiconductor device after P-type impurity doping of the drift layer is subjected to ion activation annealing and surface cleaning treatment sequentially to form the first P-type semiconductor region.

[0078] In this application, the first P-type semiconductor regions disposed on the same sidewall of each trench group can also be multiple regions disposed on each other. This embodiment can be referred to the above description, and will not be repeated here.

[0079] In some possible embodiments of this application, to form multiple gate trenches, a plurality of gate trenches are formed in the drift layer that are spaced apart and extend from the top of the drift layer to the first N-type semiconductor region in a third direction. This may include the following steps: forming a third mask layer on the drift layer (the third mask layer may be a mask formed of silicon dioxide, polysilicon, or silicon nitride); etching the third mask layer using a suitable etching process, either dry etching or wet etching, to form a third mask opening; exposing the corresponding region in the drift layer where the gate trenches need to be formed through the third mask opening, while covering the remaining region of the drift layer with the remaining third mask layer; then, using a dry etching process, etching the drift layer exposed through the second mask opening until etching into the first N-type semiconductor region to form a plurality of gate trenches extending from the top of the drift layer in a first direction and arranged in a second direction in the drift layer; and finally, removing the third mask layer.

[0080] In some possible embodiments of this application, forming a gate dielectric layer in a gate trench may include the following steps: oxidizing the entire drift layer using an oxidation process to form a gate dielectric layer on the surface of the drift layer. That is, a gate dielectric layer is formed on the surface of each gate trench, and a gate dielectric layer is also formed on the side of the drift layer facing away from the semiconductor substrate.

[0081] In some possible embodiments of this application, to form a gate, a first gate is formed in a gate trench where a gate dielectric layer is formed, and a second gate is formed on top of a drift layer, with the first and second gates in contact with each other. This can include the following steps: First, a deposition process is used to deposit polysilicon material on the entire drift layer where the gate trenches are formed, filling each gate trench and each first shielding trench with the polysilicon material. After filling the gate trenches and first shielding trenches with polysilicon material, a polysilicon film is applied to the entire drift layer. Then, a fourth mask layer (which may be a mask formed of silicon dioxide, a polysilicon layer, or silicon nitride) is formed on the drift layer. The fourth mask layer is etched using a suitable etching process, either dry or wet, to form a fourth mask opening. The area where the second gate is formed is covered by the retained fourth mask layer, and the remaining area is exposed through the fourth mask opening. Subsequently, a dry etching process is used to etch the polysilicon material region exposed through the fourth mask opening until the source region and the first P-type semiconductor region are exposed, and then the etching is stopped to form the first gate and the second gate.

[0082] In some possible embodiments of this application, in order to form an interlayer dielectric layer, forming an interlayer dielectric layer on the gate that covers the entire drift layer may include the following steps: using a deposition process to deposit an interlayer dielectric layer on the entire drift layer and make the interlayer dielectric layer cover the entire drift layer.

[0083] In some possible embodiments of this application, etching the interlayer dielectric layer to expose a first P-type semiconductor region and a second portion of the source region, while the interlayer dielectric layer covers the first portion of the source region and completely covers the gate, may include the following steps: First, a fifth mask layer (which may be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. A fourth mask layer is etched using a suitable etching process, either dry or wet, to form a fifth mask opening. The fifth mask layer is then used to cover the first portion of the source region that needs to be covered and the area that completely covers the gate (i.e., the area where contact holes do not need to be formed) in the interlayer dielectric layer. The area in the interlayer dielectric layer corresponding to the second portion of the first P-type semiconductor region and the source region that needs to be exposed (i.e., the area where contact holes are formed) is exposed through the fifth mask opening. Then, a dry etching process is used to etch the area exposed through the fifth mask opening in the interlayer dielectric layer to form contact holes, thereby exposing the second portion of the source region and the first P-type semiconductor region.

[0084] In some possible embodiments of this application, to form the source and drain, the source is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, so that the source contacts the second portion of the first P-type semiconductor region and the source region. This is achieved by the source contacting the second portion of the first P-type semiconductor region and the source region exposed through contact holes, thereby connecting the source to each of the first P-type semiconductor regions. The drain is formed on the side of the semiconductor substrate away from the drift layer. This can include the following steps: using a deposition process, depositing a metal material on the side of the interlayer dielectric layer away from the semiconductor substrate to form the source, so that the source contacts not only the interlayer dielectric layer but also the second portion of the first P-type semiconductor region and the source region. That is, the metal material fills the contact holes, allowing the source to contact the source region through the metal material filled in the contact holes. Furthermore, when forming the source, a deposition process is also used to deposit a metal material on the side of the semiconductor substrate away from the drift layer to form the drain. Alternatively, a deposition process can be used to deposit a metal material on the side of the interlayer dielectric layer away from the semiconductor substrate to form the source electrode. This allows the source electrode to contact not only the interlayer dielectric layer but also a second portion of the first P-type semiconductor region and the source region. In other words, the metal material fills the contact holes, allowing the source electrode to contact the source region through the metal material filling the contact holes. Then, a deposition process is used to deposit a metal material on the side of the semiconductor substrate away from the drift layer to form the drain electrode.

[0085] Thirdly, embodiments of this application also provide a power conversion circuit for converting alternating current (AC) and / or direct current (DC) to output direct current. For example, the power conversion circuit can be an AC-to-DC converter and / or a DC-to-DC converter. The power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. The semiconductor devices may be those used in the first aspect or various possible designs of the first aspect, or those fabricated using the second aspect or various possible designs of the second aspect. Because the aforementioned semiconductor devices have good performance, the power conversion circuit including these semiconductor devices also has good performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0086] Fourthly, embodiments of this application also provide a vehicle that may include a load and a power conversion circuit. The power conversion circuit converts alternating current and / or direct current into direct current before inputting it to the load to supply power. This power conversion circuit can be as described in the third aspect or various possible designs of the third aspect. Because the power conversion circuit described above has good performance, the vehicle including such a circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effects of this vehicle can be referred to the technical effects of the aforementioned power conversion circuit, and repetitions will not be repeated. Attached Figure Description

[0087] Figure 1 This diagram shows the relationship between the channel resistance and the JFET resistance in a SiC MOSFET device.

[0088] Figure 2a This is a schematic diagram of the structure of an electric vehicle provided in one embodiment of this application;

[0089] Figure 2b This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application;

[0090] Figure 3 This is a partial top view of a semiconductor device provided in one embodiment of this application;

[0091] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of AA'.

[0092] Figure 5 for Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of BB'.

[0093] Figure 6 for Figure 3 A schematic diagram of the cross-sectional structure along the VV' tangent direction;

[0094] Figure 7 for Figure 3 A schematic diagram of the three-dimensional structure in the selected area;

[0095] Figure 8 for Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without a source electrode.

[0096] Figure 9 for Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0097] Figure 10 for Figure 3 A partial top view of the contact hole structure of the semiconductor device shown;

[0098] Figure 11 Some flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0099] Figures 12a to 12h These are three-dimensional structural schematic diagrams of a process for fabricating a semiconductor device provided in the embodiments of this application;

[0100] Figure 13 A partial top view of a semiconductor device provided in another embodiment of this application;

[0101] Figure 14 for Figure 13 A schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0102] Figure 15 for Figure 13 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0103] Figure 16 for Figure 13 A schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0104] Figure 17 A partial top view of a semiconductor device provided in another embodiment of this application;

[0105] Figure 18 for Figure 17 A schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0106] Figure 19 for Figure 17 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0107] Figure 20 for Figure 17 A schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0108] Figure 21 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0109] Figure 22 for Figure 21 A partial top view of the semiconductor device shown;

[0110] Figure 23 for Figure 22 A schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0111] Figure 24 for Figure 22 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0112] Figure 25 for Figure 22 A schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0113] Figure 26 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0114] Figure 27 for Figure 26 The illustrated embodiment provides a partial top view of the semiconductor device.

[0115] Figure 28 for Figure 27 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0116] Figure 29 for Figure 27 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0117] Figure 30 for Figure 27 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0118] Figure 31 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0119] Figure 32 for Figure 31 The illustrated embodiment provides a partial top view of the semiconductor device.

[0120] Figure 33 for Figure 32 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0121] Figure 34 for Figure 32 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0122] Figure 35 for Figure 32 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the VV' tangent direction.

[0123] Figure label:

[0124] 010-Electric vehicle; 012-Battery; 013-Load; 0100-Electronic device; 011 / 0110-Power conversion circuit; 0120-Load module; 0200-Power supply; 0111-DC-DC converter; 01-Gate trench; 02 / 021 / 022 / 023-Contact hole; 1-Drain; 2-Semiconductor substrate; 100-Drift layer; 3-First N-type semiconductor region; 4 / 4a / 4b / 4c / 4d-First P-type semiconductor region; 5-Second P-type semiconductor region; 6-Gate dielectric layer; 7-Gate; 71-First gate; 72-Second gate; 8-Source region; 10-Interlayer dielectric layer; 11-Source; 12- First shielding trench; 13 / 13a / 13b / 13c - Second shielding trench; 14 - Second N-type semiconductor region; 15 - Filling material; 01a - First edge trench; 01b - Second edge trench; X - First direction; Y - Second direction; Z - Third direction; C - Trench spacing; D - Trench length; E - Trench width; F - Contact width; GK1 / GK2 - Trench group; S1 - First sidewall; S2 - Second sidewall; S3 - Third sidewall; S4 - Fourth sidewall; DS0 - Set thickness; 8a - First part area; 8b - Second part area; 8c - Third part area; 8d1 / 8d2 / 8d3 / 8d4 - Fourth part area. Detailed Implementation

[0125] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are only used for distinguishing the purpose of description and should not be construed as indicating or implying relative importance or order.

[0126] It should be noted that in the embodiments of this application, "connection" refers to electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B. Alternatively, it can be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0127] Furthermore, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them are omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0128] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out this application; however, the description is for the purpose of illustrating the general principles of this application and is not intended to limit the scope of this application.

[0129] To facilitate understanding of the semiconductor devices, fabrication methods, power conversion circuits, and vehicles provided in the embodiments of this application, their application scenarios will be introduced first below.

[0130] The semiconductor devices provided in this application can be used in vehicles (e.g., electric vehicles), such as in onboard microcontroller units (MCUs) and onboard battery chargers (OBCs). It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of devices, including but not limited to. The following description uses an electric vehicle as an example.

[0131] Figure 2a This is a schematic diagram of the structure of an electric vehicle provided in an embodiment of this application. (Refer to...) Figure 2a The electric vehicle 010 may include a power conversion circuit 011 and a battery 012.

[0132] In one possible implementation, the power conversion circuit 011 may include an alternating current (AC) to direct current (DC) converter and a DC-DC converter. The power conversion circuit 011 can also be referred to as an inverter. For example, when an electric vehicle is charging, the electric vehicle 010 can be connected to a three-phase power grid and receive three-phase AC power from the grid. By controlling the operation of the power switch in the AC-DC converter in the power conversion circuit 011, the AC-DC converter can convert the three-phase AC power into DC power. Furthermore, by controlling the operation of the power switch in the DC-DC converter in the power conversion circuit 011, the DC-DC converter can regulate the voltage of the DC power output from the AC-DC converter, thereby providing voltage-matched DC power to the battery 012. This allows the battery 012 to store the DC power, thus achieving the charging function.

[0133] In another possible implementation, the power conversion circuit 011 can also be a DC-DC converter circuit, and the electric vehicle 010 can also include a load 013, which can be an on-board device, power system, etc. of the electric vehicle 010. For example, by controlling the operation of the power switch of the DC-DC converter circuit of the power conversion circuit 011, the power conversion circuit 011 can regulate the DC power output from the battery and output it to the load 013, thereby providing voltage-adapted DC power to the load 013.

[0134] The semiconductor device provided in this application embodiment is a trench-gate MOSFET, which can increase the conduction channel density without increasing the JFET region resistance, thereby reducing the total conduction resistance, improving device performance, and reducing device losses. Exemplarily, the semiconductor device provided in this application embodiment can be applied to the power conversion circuit 011 of a vehicle as a power switch in an AC-DC converter and / or a DC-DC converter. Because the semiconductor device provided in this application embodiment has good device performance, when applied to an AC-DC converter and / or a DC-DC converter, it can improve the performance of the AC-DC converter and / or the DC-DC converter and reduce drive losses, thereby improving the overall circuit performance and reducing drive losses.

[0135] The semiconductor devices provided in this application can also be widely used in various electronic devices, such as those with logic devices or memory devices. For example, such electronic devices can be smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), etc. It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of electronic devices, including but not limited to.

[0136] Figure 2b This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Refer to...) Figure 2b The electronic device 0100 provided in this application embodiment includes a power conversion circuit 0110 and a load module 0120, with the power conversion circuit 0110 and load module 0120 electrically connected. Exemplarily, the electronic device 0100 can be any electrical device. Examples include smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), in-vehicle microcontroller units (MCUs), and on-board battery chargers (OBCs). It should be noted that this application does not limit the specific type of electronic device.

[0137] In some embodiments, the power conversion circuit 0110 can be a DC-DC power conversion circuit, used to boost or buck DC power and output DC power to supply power to the load module 0120. For example, the power conversion circuit 0110 can convert the DC power (e.g., 48V) output from the power supply 0200 into DC power suitable for all types of load modules 0120 and output it to the load module 0120 for operation. This application does not impose any limitations on the power supply 0200 and the load module 0120. The power supply 0200 can be any device or component capable of outputting DC power. For example, the power supply 0200 can be a battery (e.g., a storage battery). The power conversion circuit 0110 can receive the battery voltage provided by the battery, convert the battery voltage into the operating voltage of the load module 0120, and output it to the load module 0120. The load module 0120 can be any functional module that uses DC power, such as a processor, chip, etc.

[0138] Reference Figure 2a The power conversion circuit 0110 includes a DC-DC converter 0111. In operation, the MOSFETs in the DC-DC converter 0111 operate at a certain switching frequency, causing the DC-DC converter 0111 to boost or buck the DC power from the power supply 0200 and output DC power to provide the operating voltage for the load module 0120. For example, the DC-DC converter may be a Buck converter, a Boost converter, a half-bridge converter, a full-bridge converter, or an inductor-inductor-capacitor (LLC) resonant converter.

[0139] The semiconductor device provided in this application embodiment is a trench-gate MOSFET, which can increase the conduction channel density without increasing the JFET region resistance, thereby reducing the total conduction resistance, improving device performance, and reducing device losses. Exemplarily, the semiconductor device provided in this application embodiment can be applied to a DC-DC converter 0111 as a MOSFET in the DC-DC converter 0111. Because the semiconductor device provided in this application embodiment has good device performance, when applied to the MOSFET in the DC-DC converter 0111, it can improve the performance of the DC-DC converter 0111 and reduce drive losses, thereby improving the performance of the entire electronic device and reducing drive losses.

[0140] It should be noted that the above scenario descriptions are merely illustrative of some feasible application methods of the semiconductor device of this application. This application does not limit the specific application scenarios of the semiconductor device provided in the embodiments of this application, and can be determined according to the actual application requirements.

[0141] In some embodiments provided in this application, the semiconductor substrate and drift layer are made of SiC. Therefore, the semiconductor device provided in the embodiments of this application is a SiC MOSFET.

[0142] It should be explicitly stated that, in this application, layers and regions prefixed with N or P represent electrons or holes as the majority carriers, respectively. Furthermore, a "+" sign marked with N or P indicates a higher doping concentration than layers or regions without a "+" sign, and the more "+" signs, the higher the doping concentration. The presence of the same number of "+" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration. Similarly, a "-" sign marked with N or P indicates a lower doping concentration than layers or regions without a "-" sign, and the more "-" signs, the lower the doping concentration. The presence of the same number of "-" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration.

[0143] It should also be noted that the comparison of doping concentration between the two regions in this application refers only to the comparison of the concentration of impurities doped in the two regions. The composition of the impurities is not limited to the substrate used to dope the impurities; that is, the composition of the impurities may be the same or different. The materials of the substrates used to dope the impurities may be the same or different.

[0144] Figure 3 This illustration shows a partial top view of a semiconductor device provided in one embodiment of the present application. Figure 4 It shows Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of AA'. Figure 5 It shows Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of BB'. Figure 6 It shows Figure 3 A schematic diagram of a cross-sectional structure along the VV' tangent direction. Figure 7 It shows Figure 3 The diagram shows the three-dimensional structure of the selected region QB. Figure 8 It shows Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without a source electrode. Figure 9 It shows Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0145] Reference Figures 3 to 9The semiconductor device provided in this application includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches 01 spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. The drift layer 100 is disposed on the semiconductor substrate 2 and includes: a first N-type semiconductor region 3, a second P-type semiconductor region 5, and a source region 8 sequentially stacked on the semiconductor substrate 2, and first P-type semiconductor regions 4 (e.g., 4a, 4b, 4c, 4d) disposed on both sides of the drift layer 100, i.e., the second P-type semiconductor region 5 is disposed between the first N-type semiconductor region 3 and the source region 8. That is, the first N-type semiconductor region 3 is in contact with the semiconductor substrate 2, and the source region 8 is disposed in the region at the top of the drift layer 100. Furthermore, each of the first P-type semiconductor regions 4 (such as 4a, 4b, 4c, 4d) extends from the top of the drift layer 100 into the first N-type semiconductor region 3 along a third direction Z perpendicular to the plane where the semiconductor substrate 2 is located.

[0146] In this application, the semiconductor substrate can be a silicon carbide single crystal substrate doped with pentavalent elements. The drift layer 100 can be formed by epitaxial growth of SiC material doped with corresponding impurities. For example, the first N-type semiconductor region 3 is a portion of the drift layer 100 formed by epitaxial growth. The source region 8 is an N-type semiconductor region, and the source region 8 can be formed by N-type impurity doping of the drift layer 100 using an ion implantation process.

[0147] For example, in this application, the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).

[0148] For example, in this application, the doping concentration of the semiconductor substrate 2 is greater than the doping concentration of the first N-type semiconductor region 3, and the doping concentration of the source region 8 is also greater than the doping concentration of the first N-type semiconductor region 3. Optionally, the doping concentration of the semiconductor substrate 2 is similar to or the same as the doping concentration of the source region 8. Of course, the doping concentration of the semiconductor substrate 2 and the doping concentration of the source region 8 can also be different; for example, the doping concentration of the semiconductor substrate 2 may be greater than or less than the doping concentration of the source region 8, which is not limited here.

[0149] In this application, the second P-type semiconductor region 5 can also be formed by epitaxially growing SiC material doped with P-type impurities; that is, the second P-type semiconductor region 5 can also be a portion of the drift layer 100 formed by epitaxial growth. Alternatively, the second P-type semiconductor region 5 can also be formed by ion implantation, through P-type impurity doping of the drift layer 100. This application does not limit the formation process of the second P-type semiconductor region 5.

[0150] For example, in this application, the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0151] Continue to refer to Figures 3 to 9 In this application, a plurality of gate trenches 01, spaced apart from each other, are disposed in the drift layer 100, and the plurality of gate trenches 01 extend from the top of the drift layer 100 to the first N-type semiconductor region 3 along a third direction Z. The plurality of gate trenches 01 extend along a first direction X parallel to the plane of the semiconductor substrate 2, and are arranged along a second direction Y parallel to the plane of the semiconductor substrate 2. That is, a closely spaced array of gate trenches 01 is fabricated in the drift layer 100.

[0152] Continue to refer to Figures 3 to 9 In this application, the gate 7 includes a first gate 71 and a second gate 72 that are in contact with each other. The first gate 71 is filled in the gate trench 01 through the gate dielectric layer 6, so that the first gate 71 is embedded inside the SiC material drift layer 100. The second gate 72 is also disposed on top of the SiC material drift layer 100 through the gate dielectric layer 6, so as to connect the first gates 71 disposed in different gate trenches 01. Furthermore, the first gate 71, together with the second P-type semiconductor region 5 through the gate dielectric layer 6, forms the trench gate structure of the SiC MOSFET device. That is to say, the semiconductor device provided in this application embodiment is formed as a SiC MOSFET with a trench gate structure.

[0153] For example, in this application, the first gate 71 is disposed in the gate trench 01, which is equivalent to the first gate 71 extending along the first direction X and arranged along the second direction Y. The second gate 72 can be configured to extend along the second direction Y, such that a portion of the second gate 72 is disposed on top of the drift layer 100 through the gate dielectric layer 6, and another portion is disposed on top of the first gate 71, directly contacting the first gate 71. Thus, the first gates 71 disposed in different gate trenches can be connected through the second gates 72 above the gate trench 01.

[0154] For example, in this application, the portions of the first gate 71 disposed on both sides of the second gate 72 in contact with it have similar or the same length in the first direction. Of course, in the same trench group, the portions of the first gate 71 disposed on both sides of the second gate 72 in contact with it may have different lengths in the first direction. This application does not limit this, and it can be determined according to the needs of actual application.

[0155] This application does not limit the material of the gate 7. For example, the material of the gate 7 can be polycrystalline silicon, or other materials with good conductivity such as metals (e.g., W, Al, Ti, Cu, Mo or Pt).

[0156] Continue to refer to Figures 3 to 9 The interlayer dielectric layer 10 covers the side of the gate 7 away from the semiconductor substrate 2, that is, the interlayer dielectric layer 10 covers the entire side of the semiconductor substrate 2 with the gate 7. The source 11 is disposed on the side of the interlayer dielectric layer 10 away from the semiconductor substrate 2, that is, the source 11 covers the entire interlayer dielectric layer 10. The drain 1 is disposed on the side of the semiconductor substrate 2 away from the drift layer 100, that is, the drain 1 covers the side of the semiconductor substrate 2 without the drift layer 100. The interlayer dielectric layer 10 covers the gate 7 and the first portion 8a of the source region 8, exposing the second portion 8b of the first P-type semiconductor region 4 and the source region 8. The source 11 can cover the entire interlayer dielectric layer 10 and the second portion 8b of the first P-type semiconductor region 4 and the source region 8, that is, the source 11 is in direct contact with the upper surfaces of the interlayer dielectric layer 10, the first P-type semiconductor region 4, and the second portion 8b of the source region 8. This is equivalent to providing a contact hole 02 extending along the second direction Y in the interlayer dielectric layer 10, exposing the second part of the source region 8b of the source region 8 through the contact hole 02, thereby enabling the source electrode 11 to contact the source region 8 through the contact hole 02, achieving the effect of connecting the source electrode 11 to the source region 8. Thus, when the gate 7 controls the channel to be turned on, a signal can be transmitted between the source electrode 11 and the drain electrode 1.

[0157] In practical applications, signal transmission is required between the source 11 and the drain 1. A contact hole 02 extending along the second direction Y can be provided in the interlayer dielectric layer 10. To prevent the source 11 from contacting the gate 7, the orthogonal projection of the contact hole 02 onto the semiconductor substrate 2 and the orthogonal projection of the gate 7 onto the semiconductor substrate 2 can be made non-overlapping; that is, in the third direction Z, the contact hole 02 and the gate 7 do not overlap. The contact hole 02 exposes a portion of the source region 8 (e.g., the contact hole 02 exposes a portion of the source region 8 located on both sides of the first gate 71 in the first direction X), allowing the source 11 to contact the source region 8 through the contact hole 02, thus achieving the connection between the source 11 and the source region 8. Therefore, when the gate 7 controls the channel to conduct, signal transmission can be achieved between the source 11 and the drain 1.

[0158] This application does not limit the material used to form the interlayer dielectric layer 10. For example, the material used to form the interlayer dielectric layer 10 can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0159] This application does not limit the materials used to form the source electrode 11 and the drain electrode 1. For example, the materials used to form the source electrode 11 and the drain electrode 1 can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt.

[0160] Continue to refer to Figures 3 to 9 The first direction X, the second direction Y, and the third direction Z are arranged to intersect each other. For example, the first direction X, the second direction Y, and the third direction Z are arranged to be perpendicular to each other.

[0161] Figure 10 It shows Figure 3 The diagram shows a partial top view of the contact hole structure of the semiconductor device. (Refer to...) Figure 10 In some embodiments of this application, multiple gate trenches in a semiconductor device can be divided into one or more trench groups, and two or more contact holes can be provided. Furthermore, a trench group is provided between two adjacent contact holes. This allows for more uniform signal flow. For example, multiple gate trenches in a semiconductor device can be divided into multiple trench groups, and multiple contact holes are also provided. These multiple trench groups are arranged along a first direction X, and the multiple contact holes are also arranged along the first direction X. For example, taking the division into two trench groups as an example, refer to... Figure 3 and Figure 10 In a semiconductor device, multiple gate trenches 01 are divided into two trench groups, GK1 and GK2, which are arranged along a first direction X. Three contact holes 02 are provided, 021, 022, and 023, which are also arranged along the first direction X. Trench group GK1 is provided between contact holes 021 and 022, and trench group GK2 is provided between contact holes 022 and 023. Alternatively, multiple gate trenches 01 in the semiconductor device are divided into one trench group, such as trench group GK1. Two contact holes 02 are provided, such as 021 and 022. Trench group GK1 is provided between contact holes 021 and 022.

[0162] In some embodiments of this application, the number of gate trenches in different trench groups can be the same. This allows for a uniform distribution of the gate trenches. For example, see... Figure 3 and Figure 10 Six gate trenches 01 are respectively set in trench groups GK1 and GK2. It should be noted that... Figure 3 and Figure 10 The number of gate trenches 01 shown in trench groups GK1 and GK2 is for illustrative purposes only and does not represent the actual number of gate trenches 01 in the fabricated semiconductor device. In practical applications, the specific number of gate trenches 01 in the trench group can be determined according to the requirements of the application, and this application does not limit it in this regard.

[0163] In some embodiments of this application, the number of gate trenches in some trench groups may be the same, while the number of gate trenches in other trench groups may be different. Alternatively, the number of gate trenches in different trench groups may be different. In practical applications, the specific number of gate trenches in a trench group can be determined according to the needs of the actual application, and this application does not limit it in this regard.

[0164] In some embodiments of this application, in the second direction Y, the two gate trenches at the edges of the trench group are respectively defined as a first edge trench and a second edge trench, and the contact hole extends along the second direction from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench. For example, referring to... Figure 3 and Figure 10 Taking trench group GK2 as an example, in the second direction Y, the two gate trenches 01 at the edge of trench group GK2 are defined as the first edge trench 01a and the second edge trench 01b, respectively. Then, the contact hole 02 extends from the side of the first edge trench 01a away from the second edge trench 01b along the second direction Y to the side of the second edge trench 01b away from the first edge trench 01a. That is to say, the contact hole 02 is a continuous opening, and the gate trenches 01 in different trench groups are not connected.

[0165] This application does not limit the shape of the region enclosed by the orthographic projection of each trench group onto the semiconductor substrate. In some examples, the region enclosed by the orthographic projection of each trench group onto the semiconductor substrate is rectangular. For example, the rectangle can be a rectangle or a square.

[0166] In other examples, when multiple trench groups are configured, the area enclosed by the orthographic projection of each trench group onto the semiconductor substrate is rectangular. Furthermore, the area enclosed by the orthographic projection of all trench groups onto the semiconductor substrate can be one of the following polygons: square, rectangle, hexagon, octagon, etc., without limitation.

[0167] Continue to refer to Figures 3 to 9In this application, the first P-type semiconductor region 4 is disposed on both sides of the drift layer 100, which can be the case that the first P-type semiconductor region 4 is disposed on both sides of each trench group. For example, in the first direction X, the gate trench 01 has a first sidewall S1 and a second sidewall S2 disposed opposite to each other, and the first P-type semiconductor region 4 is disposed on the side of the first sidewall S1 and the second sidewall S2 away from the side of the first gate 71 filled in the gate trench 01, and the distance hd1 between the bottom of the first P-type semiconductor region 4 and the top of the drift layer 100 is greater than the distance hd2 between the bottom of the gate trench 01 and the top of the drift layer 100. That is, the depth of the first P-type semiconductor region 4 in the third direction Z is greater than the depth of the gate trench 01 in the third direction Z. Furthermore, the source 11 is in direct contact with the first P-type semiconductor region 4, achieving the effect of connecting the source 11 with the first P-type semiconductor region 4. That is, in this application, the source 11 and the first P-type semiconductor region 4 can be connected. In practical applications, when the SiC MOSFET device is working, a voltage is applied to the source 11. Since the first P-type semiconductor region 4 is connected to the source 11, the voltage applied to the source 11 will be input to the first P-type semiconductor region 4, so that the first P-type semiconductor region 4 also has a corresponding voltage. The first P-type semiconductor region 4 acts as a shielding structure, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench 01, thereby improving the robustness of the device operation.

[0168] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can be grounded and its drain can be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the ground voltage (0V). Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.

[0169] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the first P-type semiconductor region is connected to the source, the voltage of the first P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, thereby improving the robustness of the device operation.

[0170] This application does not limit the specific values ​​of hd1 and hd2, only requiring that hd1 > hd2. For example, 1.5hd2 ≤ hd1 ≤ 2.5hd2 can be used. For instance, hd1 can be similar to or the same as twice the value of hd2; that is, when the depth of the first P-type semiconductor region 4 is approximately twice the depth of the gate trench, the electric field of the gate dielectric layer at the bottom of the gate trench can be controlled within 3 MV / cm, meeting the device's reliability requirements.

[0171] The semiconductor device provided in this application embodiment fabricates a closely spaced array of gate trenches in a drift layer, and a first gate is disposed in the gate trenches. The region at the boundary between the second P-type semiconductor region and the gate dielectric layer is a channel. Furthermore, the extension direction of the contact holes disposed in the interlayer dielectric layer is a second direction, and the extension direction of the gate trenches (or the first gate) is a first direction. Therefore, the extension direction of the contact holes is perpendicular to the extension direction of the gate trenches (or the first gate), meaning the contact holes are placed in a direction perpendicular to the gate trenches (or the first gate). Compared to the prior art where the gate trenches and contact holes are parallel, the semiconductor device provided in this application embodiment reduces the restriction of the contact holes on the trench spacing C of adjacent gate trenches in the second direction, allowing for a more compact fabrication of the gate trenches, i.e., a more compact first gate. This facilitates reducing the trench spacing between gate trenches, thereby miniaturizing the cells and improving cell density and device current carrying capacity. Therefore, the gate trench array density of the semiconductor device provided in this application embodiment can be much higher than the gate trench array density of the device structure in the prior art, thereby increasing the channel density of the SiC MOSFET with trench gate structure, significantly reducing the total on-resistance per unit area of ​​the device, improving the current carrying capacity and device performance, and reducing device losses.

[0172] For example, refer to Figures 3 to 9 In this application, the orthogonal projection of the first P-type semiconductor region (such as 4a, 4b, 4c, 4d) onto the first plane formed by the second direction Y and the third direction Z covers the orthogonal projection of the gate trench onto the first plane. The first plane is parallel to the second direction Y and the third direction Z.

[0173] For example, in this application, the first P-type semiconductor regions disposed on the same side of the drift layer can be configured as a single, integral region. For instance, the first P-type semiconductor regions disposed on the same side of the trench group can be configured as a single, integral region. That is, one first P-type semiconductor region is disposed on the first side S1 of the same trench group, and another first P-type semiconductor region is disposed on the second side S2 of the same trench group. Furthermore, the orthogonal projection of each first P-type semiconductor region onto the semiconductor substrate is a strip-shaped region extending along the second direction Y. Also, each first P-type semiconductor region extends along the second direction Y from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench. For example, refer to... Figures 3 to 9 A strip-shaped first P-type semiconductor region 4a is provided at the first sidewall S1 of the gate trench in trench group GK1, a strip-shaped first P-type semiconductor region 4b is provided at the second sidewall S2 of the gate trench in trench group GK1, a strip-shaped first P-type semiconductor region 4c is provided at the first sidewall S1 of the gate trench in trench group GK2, and a strip-shaped first P-type semiconductor region 4d is provided at the second sidewall S2 of the gate trench in trench group GK2.

[0174] For example, refer to Figures 3 to 9 In this application, the orthographic projection of each first P-type semiconductor region (e.g., 4a, 4b, 4c, 4d) onto the semiconductor substrate does not overlap with the orthographic projection of each gate trench 01 onto the semiconductor substrate. That is, in the third direction Z, there is no overlapping region between each first P-type semiconductor region (e.g., 4a, 4b, 4c, 4d) and each gate trench 01.

[0175] For example, in this application, a fourth portion of the source region is located between the gate trench and the corresponding first P-type semiconductor region. That is, the fourth portion of the source region is projected onto the semiconductor substrate between the orthogonal projection of the gate trench onto the semiconductor substrate and the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate. For example, referring to… Figures 3 to 9The first sidewall S1 of the gate trench 01 in the trench group GK1 has a fourth part region 8d1 of the source region 8 between the first sidewall S1 of the gate trench 01 in the trench group GK1 and the corresponding first P-type semiconductor region 4a. That is, the fourth part region 8d1 of the source region 8 is projected onto the semiconductor substrate 2 between the orthogonal projection of the first sidewall S1 of the gate trench 01 in the trench group GK1 and the orthogonal projection of the first P-type semiconductor region 4a on the semiconductor substrate 2. That is, the gate dielectric layer 6 provided at the first sidewall S1 of the gate trench 01 in the trench group GK1 is not in contact with the first P-type semiconductor region 4a. The second sidewall S2 of the gate trench 01 in the trench group GK1 has a fourth part region 8d2 of the source region 8 between it and the corresponding first P-type semiconductor region 4b. That is, the second sidewall S2 of the gate trench 01 in the trench group GK1 has a fourth part region 8d2 of the source region 8 between its orthogonal projection on the semiconductor substrate 2 and the orthogonal projection of the first P-type semiconductor region 4b on the semiconductor substrate 2. That is, the gate dielectric layer 6 disposed on the surface of the second sidewall S2 of the gate trench 01 in the trench group GK1 is not in contact with the first P-type semiconductor region 4b. The first sidewall S1 of the gate trench 01 in the trench group GK2 has a fourth part region 8d3 of the source region 8 between it and the corresponding first P-type semiconductor region 4c. That is, the first sidewall S1 of the gate trench 01 in the trench group GK2 has a positive projection of the fourth part region 8d3 of the source region 8 on the semiconductor substrate 2 between the positive projection of the first sidewall S1 of the gate trench 01 in the trench group GK2 and the positive projection of the first P-type semiconductor region 4c on the semiconductor substrate 2. That is, the gate dielectric layer 6 disposed on the surface of the first sidewall S1 of the gate trench 01 in the trench group GK2 is not in contact with the first P-type semiconductor region 4c. The second sidewall S2 of the gate trench 01 in the trench group GK2 has a fourth part region 8d4 of the source region 8 between it and the corresponding first P-type semiconductor region 4d. That is, the second sidewall S2 of the gate trench 01 in the trench group GK2 has a fourth part region 8d4 of the source region 8 between its orthogonal projection on the semiconductor substrate 2 and the orthogonal projection of the first P-type semiconductor region 4d on the semiconductor substrate 2. That is, the gate dielectric layer 6 disposed on the surface of the second sidewall S2 of the gate trench 01 in the trench group GK2 is not in contact with the first P-type semiconductor region 4d.

[0176] For example, refer to Figure 3 and Figure 4 In this application, the drift layer 100 further includes: a plurality of first shielding trenches 12 spaced apart from each other. Figure 3 Taking a first shielding trench disposed between trench group GK1 and trench group GK2 as an example, the plurality of first shielding trenches 12 extend from the top of the drift layer 100 to the first N-type semiconductor region 3 in a third direction Z. Furthermore, the first shielding trenches 12 are disposed on both sides of the drift layer 100, and first P-type semiconductor regions 4 are disposed on the sidewalls and bottom of the first shielding trenches 12. For example, referring to… Figures 3 to 9In each trench group, the first sidewall S1 and the second sidewall S2 of the gate trench 01 are respectively provided with a first shielding trench 12 on the side opposite to the filled first gate 71. For example, a first shielding trench 12 is provided between the second sidewall S2 of the gate trench in trench group GK1 and the first sidewall S1 of the gate trench in trench group GK2.

[0177] In this application, Figure 3 This explanation uses the first shielding trench between the second sidewall S2 of the gate trench 01 in trench group GK1 and the first sidewall S1 of the gate trench 01 in trench group GK2 as an example. In practical applications, the first sidewall S1 of the gate trench 01 in trench group GK1, away from the first gate 71 it fills, also has a first shielding trench. The implementation of this can be referenced from the implementation of the first shielding trench between the second sidewall S2 of the gate trench 01 in trench group GK1 and the first sidewall S1 of the gate trench 01 in trench group GK2. Furthermore, the second sidewall S2 of the gate trench 01 in trench group GK2, away from the first gate 71 it fills, also has a first shielding trench. The implementation of this can be referenced from the implementation of the first shielding trench between the second sidewall S2 of the gate trench 01 in trench group GK1 and the first sidewall S1 of the gate trench 01 in trench group GK2; details will not be elaborated here.

[0178] For example, refer to Figure 3 and Figure 4 In this application, the orthographic projection of the first shielding trench 12 onto the semiconductor substrate 2 is a strip-shaped region extending along the second direction Y.

[0179] For example, refer to Figure 3 and Figure 4 Each first shielding trench 12 has a P-type semiconductor region on its sidewall. That is, each sidewall of each first shielding trench 12 has a P-type semiconductor region. Optionally, the P-type semiconductor region on the sidewall of each first shielding trench 12 in the first direction X can be used as the first P-type semiconductor region. For example, in the first direction, the first shielding trench 12 has a third sidewall S3 and a fourth sidewall S4 disposed opposite to each other. The P-type semiconductor region disposed at the third sidewall S3 of the first shielding trench 12 can be used as the first P-type semiconductor region 4b, and the P-type semiconductor region disposed at the fourth sidewall S4 of the first shielding trench 12 can be used as the first P-type semiconductor region 4c.

[0180] For example, refer to Figure 3 and Figure 4Each first shielding trench 12 also has a P-type semiconductor region at its bottom. By providing a P-type semiconductor region at the bottom of the first shielding trench 12, this application further effectively shields the gate dielectric layer electric field at the bottom of the gate trench 01, thereby improving the robustness of the device operation.

[0181] For example, the doping concentration of the P-type semiconductor region at the bottom of the first shielding trench 12 is similar to or the same as the doping concentration of the first P-type semiconductor region. Optionally, an ion implantation process can be used to form the P-type semiconductor region at the bottom and sidewalls of the first shielding trench 12 in the same step.

[0182] For example, the first P-type semiconductor region may be formed by ion implantation, through P-type impurity doping of the sidewalls (e.g., the third and fourth sidewalls or all sidewalls) of the first shielding trench. Furthermore, when the third and fourth sidewalls of the first shielding trench are P-type impurity doped using ion implantation, the bottom of the first shielding trench 12 is also P-type impurity doped, thereby forming a P-type semiconductor region at its bottom as well.

[0183] For example, the doping concentration of the first P-type semiconductor region (e.g., 4a, 4b, 4c, 4d) is greater than the doping concentration of the second P-type semiconductor region 5. This application does not limit the specific values ​​of the doping concentration of the first P-type semiconductor region (e.g., 4a, 4b, 4c, 4d) and the doping concentration of the second P-type semiconductor region 5.

[0184] For example, refer to Figure 4 The distance hd3 between the first shielding trench 12 and the top of the drift layer 100 is greater than the distance hd2 between the gate trench 01 and the top of the drift layer 100. That is, the depth of the first shielding trench 12 in the third direction Z is greater than the depth of the gate trench 01 in the third direction Z. Thus, when using ion implantation to dope the sidewalls and bottom of the first shielding trench with P-type impurities, the doped ions will diffuse, resulting in the first P-type semiconductor region 4 having a depth greater than the depth of the gate trench 01 in the third direction Z.

[0185] For example, the distance between the first shielding trench and the top of the drift layer can also be approximately equal to the distance between the gate trench and the top of the drift layer. That is, the depth of the first shielding trench in the third direction is similar to or the same as the depth of the gate trench in the third direction. In this way, when the sidewalls and bottom of the first shielding trench are doped using an ion implantation process, the doped ions will diffuse, thereby allowing the depth of the formed first P-type semiconductor region in the third direction to be greater than the depth of the gate trench in the third direction.

[0186] Exemplarily, in this application, when there are multiple trench groups, adjacent trench groups share a first P-type semiconductor region disposed between adjacent trench groups. Exemplarily, adjacent trench groups share a first shielding trench disposed between adjacent trench groups. Further, adjacent trench groups share a P-type semiconductor region disposed on the sidewall and bottom of the first shielding trench disposed between adjacent trench groups. For example, refer to... Figure 3 and Figure 4 The trench group GK1 and the trench group GK2 share the third sidewall S3 and the fourth sidewall S4 of the first shielding trench 12 and the P-type semiconductor region at the bottom.

[0187] For example, refer to Figure 3 and Figure 4 In this application, each first shielding trench is filled with a filler material 15, and this application does not limit the filler material 15. Exemplarily, the filler material 15 can be the gate material, that is, each first shielding trench can be filled with the gate material. For example, in actual process fabrication, when forming the gate, the gate material can be filled into the first shielding trench 12. Of course, each first shielding trench can also be filled with the interlayer dielectric layer material. Alternatively, each first shielding trench can also be filled with the source or drain material.

[0188] Reference Figure 3 In the second direction Y, there is a trench spacing C between two adjacent gate trenches O1. This application does not limit the specific value of the trench spacing C; for example, the trench spacing C is less than 1 μm. Optionally, the trench spacing C ranges from 50 nm to 0.5 μm. For example, the trench spacing C can be approximately one of 50 nm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 5 μm. It should be noted that when the trench spacing C is less than 100 nm, the semiconductor device provided in this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve the carrier channel mobility and further reduce the total on-resistance of the device.

[0189] Continue to refer to Figure 3 In the first direction X, the gate trench 01 has a trench length D. This application does not limit the trench length D; for example, the trench length D is not greater than 5 μm. Optionally, the trench length D is approximately one of: 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm.

[0190] Assuming the electron mobility is uniform across different sides, simple estimation shows that the current density ratio of the SiC MOSFET structure in this application is approximately 2(2D+1) / (D+3) compared to the existing SiC MOSFET structure where the gate trench and contact hole are parallel, where D ≤ 5 μm. Simulation results show that when D is approximately 4 μm, the gate layout structure of the SiC MOSFET in this application achieves an effect almost 2.25 times that of the existing SiC MOSFET structure.

[0191] Furthermore, in this application, when the trench length D of the gate trench 01 is controlled within 5 μm, the shielding structure formed by the adjacent first P-type semiconductor region can provide sufficient protection for the gate dielectric layer at the bottom of the gate trench (the electric field of the gate dielectric layer is less than 3 MV / cm), thereby ensuring the reliability of the device.

[0192] Continue to refer to Figure 3 In the second direction Y, the gate trench 01 has a trench width E. This application does not limit the trench width E; for example, the trench width E is less than 1 μm. Optionally, the trench width E is approximately one of: 0.9 μm, 0.8 μm, 0.5 μm, and 0.3 μm.

[0193] Reference Figure 10 In the first direction X, the contact hole 02 has a contact width F, which can ensure that the groove spacing C is not greater than the contact width F. Of course, the groove spacing C can also be greater than the contact width F. In practical applications, the groove spacing C and the contact width F can be determined according to the environmental requirements of the actual application, and are not limited here.

[0194] Figure 11 Some flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application are shown. (Refer to...) Figure 11 To prepare Figure 7 Taking the structure shown as an example, the preparation method may include the following steps:

[0195] S10. An epitaxial drift layer is grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are formed in the drift layer, which are sequentially stacked on the semiconductor substrate.

[0196] In some examples, step S10 may include:

[0197] First, an epitaxial layer is grown on an N-type semiconductor substrate using an epitaxial process.

[0198] For example, refer to Figure 12aUsing an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate 2 to form a drift layer 100 with a set thickness DS0.

[0199] This application does not limit the specific value of the thickness DS0. In practical applications, the specific value of the thickness DS0 can be determined according to the requirements of the actual application environment.

[0200] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer 100 to form a second P-type semiconductor region 5 and a source region 8. The regions of the drift layer 100 that are not ion implanted form a first N-type semiconductor region 3, and the formed second P-type semiconductor region 5 is disposed between the first N-type semiconductor region 3 and the source region 8.

[0201] For example, refer to Figure 12b First, an ion implantation process is used to dope the surface of the drift layer with P-type impurities, forming a second P-type semiconductor region 5. Next, a first mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The first mask layer is etched using a suitable etching process, either dry or wet, to form a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Then, an ion implantation process is used to dope the surface of the drift layer 100 with N-type impurities, forming a source region 8. Finally, the first mask layer is removed.

[0202] Or, refer to Figure 12b First, an ion implantation process is used to dope the surface of the drift layer with P-type impurities to form a second P-type semiconductor region 5. Then, an ion implantation process is used to dope the surface of the drift layer 100 with N-type impurities to form a source region 8.

[0203] In other examples, step S10 may also include:

[0204] First, an epitaxial layer of a predetermined thickness is grown on an N-type semiconductor substrate using an epitaxial process.

[0205] For example, using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate to form a drift layer reaching a first predetermined thickness.

[0206] This application does not limit the specific value of the first preset thickness. In practical applications, the specific value of the first preset thickness can be determined according to the needs of the actual application environment.

[0207] Subsequently, an epitaxial process is used to epitaxially grow a second P-type semiconductor region of a second predetermined thickness on a drift layer of a first predetermined thickness.

[0208] For example, using an epitaxial process, SiC material doped with P-type impurities is epitaxially grown on a drift layer to form a second P-type semiconductor region reaching a second predetermined thickness.

[0209] This application does not limit the specific value of the second preset thickness. In practical applications, the specific value of the second preset thickness can be determined according to the requirements of the actual application environment.

[0210] Subsequently, an epitaxial growth process is used to continue epitaxial growth on the second P-type semiconductor region until a drift layer with a third predetermined thickness is formed.

[0211] For example, using an epitaxial process, SiC material doped with N-type impurities is further epitaxially grown on the second P-type semiconductor region to form a drift layer reaching a third predetermined thickness.

[0212] This application does not limit the specific value of the third set thickness. In practical applications, the specific value of the third set thickness can be determined according to the needs of the actual application environment.

[0213] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer to form a source region. The regions in the drift layer that are not implanted with ions form a first N-type semiconductor region, and a second P-type semiconductor region is formed between the first N-type semiconductor region and the source region.

[0214] For example, firstly, a first mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The first mask layer is then etched using a suitable etching process, either dry or wet, to form a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Next, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region. Finally, the first mask layer is removed.

[0215] Alternatively, an ion implantation process can be used to dope the surface of the drift layer with N-type impurities to form a source region.

[0216] S20. A first P-type semiconductor region is formed on both sides of the drift layer. The first P-type semiconductor region extends from the top of the drift layer into the first N-type semiconductor region along a third direction, and the orthogonal projection of each first P-type semiconductor region onto the semiconductor substrate is a strip-shaped region extending along a second direction.

[0217] In some examples, step S20 may include:

[0218] First, the two sides of the drift layer are etched to form a first shielding trench extending upward along a third direction into the first N-type semiconductor region within the drift layer. Each first shielding trench is projected onto the semiconductor substrate as a strip-shaped region extending along a second direction. Specifically, the first sidewall S1 and the second sidewall S2 of the gate trench have first shielding trenches on the side opposite to the corresponding first gate.

[0219] For example, refer to Figure 12c A second mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The second mask layer is etched using a suitable etching process, either dry or wet, to form a second mask opening. This opening exposes the corresponding region in the drift layer where the first shielding trenches 12 need to be formed, while the remaining regions of the drift layer are covered by the second mask layer. Then, a dry etching process is used to etch the drift layer exposed through the second mask opening until it reaches the first N-type semiconductor region 3, forming a plurality of first shielding trenches 12 extending along the second direction Y and arranged along the first direction X in the drift layer.

[0220] Subsequently, ion implantation is performed on the sidewalls and bottom of each of the multiple first shielding trenches to form a first P-type semiconductor region.

[0221] For example, refer to Figure 12d The sidewalls and bottom of each first shielding trench 12 are p-type impurity doped using an ion implantation process. Then, the second mask layer is removed. Afterwards, the semiconductor devices with p-type impurity doped sidewalls and bottoms of each first shielding trench 12 are sequentially subjected to ion activation annealing and surface cleaning treatments to form the first p-type semiconductor regions 4a and 4b.

[0222] S30. Etch the drift layer to form a plurality of gate trenches spaced apart from each other, extending from the top of the drift layer into the first N-type semiconductor region along a third direction. The formed plurality of gate trenches extend along a first direction and are arranged along a second direction.

[0223] In some examples, step S30 may include: referring to Figure 12eA third mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The third mask layer is etched using a suitable etching process, either dry or wet, to form a third mask opening. This opening exposes the corresponding region in the drift layer where gate trenches need to be formed, while the remaining areas of the drift layer are covered by the retained third mask layer. Next, a dry etching process is used to etch the drift layer exposed through the second mask opening until etching reaches the first N-type semiconductor region 3, forming a plurality of gate trenches 01 extending along the first direction X and arranged along the second direction Y in the drift layer. Furthermore, the distance between the bottom of the first P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the gate trench and the top of the drift layer. Finally, the third mask layer is removed.

[0224] S40. A gate dielectric layer is formed in the gate trench.

[0225] In some examples, step S40 may include: referring to Figure 12f An oxidation process is used to oxidize the entire drift layer 100, forming a gate dielectric layer 6 on the surface of the drift layer 100. Specifically, a gate dielectric layer 6 is formed on the surface of each gate trench 01, and a gate dielectric layer 6 is also formed on the side of the drift layer 100 facing away from the semiconductor substrate 2 (the gate dielectric layer at this location is only partially formed). Figure 12f (Not shown in the image).

[0226] S50. A first gate is formed in a gate trench in which a gate dielectric layer is formed, and a second gate is formed on top of a drift layer, and the first gate and the second gate are brought into contact with each other.

[0227] In some examples, step S50 may include: First, using a deposition process, depositing polysilicon material on the entire drift layer where gate trenches are formed, and filling each gate trench and each first shielding trench with the polysilicon material, and after filling the gate trenches and first shielding trenches with the polysilicon material, covering the entire drift layer with a polysilicon film. Then, forming a fourth mask layer on the drift layer (the fourth mask layer may be a mask formed of silicon dioxide, a polysilicon layer, or silicon nitride), etching the fourth mask layer using a suitable etching process, either dry etching or wet etching, to form a fourth mask opening. The area where the second gate is formed is covered by the retained fourth mask layer, and the remaining area is exposed through the fourth mask opening. Then, using a dry etching process, etching is performed on the polysilicon material area exposed through the fourth mask opening until the source region 8 and the first P-type semiconductor region 4 are exposed, to form the first gate 71 and the second gate 72, as shown below. Figure 12f .

[0228] S60. An interlayer dielectric layer covering the entire drift layer is formed on the gate.

[0229] In some examples, step S60 may include: referring to Figure 12g An interlayer medium layer 10 is deposited on the entire drift layer using a deposition process, and the interlayer medium layer 10 covers the entire drift layer.

[0230] S70. Etch the interlayer dielectric layer to expose the first P-type semiconductor region and the second part of the source region, and the interlayer dielectric layer covers the first part of the source region and completely covers the gate.

[0231] In some examples, step S70 may include: first, forming a fifth mask layer on the drift layer (the fifth mask layer may be a mask formed of silicon dioxide, polysilicon, or silicon nitride); etching the fourth mask layer using a suitable etching process, either dry or wet, to form a fifth mask opening; covering the first portion of the interlayer dielectric layer that needs to cover the source region and the region that completely covers the gate (i.e., the region where contact hole 02 does not need to be formed) with the retained fifth mask layer; and exposing the second portion of the interlayer dielectric layer that needs to expose the first P-type semiconductor region and the source region (i.e., the region where contact hole 02 is formed) with the fifth mask opening. Then, using a dry etching process, etching is performed on the region exposed through the fifth mask opening in the interlayer dielectric layer 10 to form contact hole 02, thereby exposing the second portion of the source region 8 and the first P-type semiconductor region 4, as described above. Figure 12g .

[0232] S80. A source electrode is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, so that the source electrode contacts the second part of the first P-type semiconductor region and the source region, so that the source electrode contacts the second part of the first P-type semiconductor region and the source region exposed by the contact hole through the contact hole, so that the source electrode is connected to each first P-type semiconductor region, and a drain electrode is formed on the side of the semiconductor substrate away from the drift layer.

[0233] In some examples, step S80 may include: depositing a metal material on the side of the interlayer dielectric layer 10 away from the semiconductor substrate 2 using a deposition process to form a source 11, such that the source 11 contacts not only the interlayer dielectric layer 10 but also the second portion of the first P-type semiconductor region and the source region. That is, the source 11 contacts the source region 8 through the metal material filling the contact hole 02. Furthermore, when forming the source 11, a metal material is also deposited on the side of the semiconductor substrate 2 away from the drift layer using a deposition process to form a drain 1, as shown below. Figure 12h .

[0234] In other examples, step S80 may also include: depositing a metal material on the side of the interlayer dielectric layer 10 away from the semiconductor substrate 2 using a deposition process to form a source 11, such that the source 11 contacts not only the interlayer dielectric layer 10 but also the second portion of the first P-type semiconductor region and the source region. That is, the source 11 contacts the source region 8 through the metal material filling the contact hole 02. Then, a metal material is deposited on the side of the semiconductor substrate 2 away from the drift layer using a deposition process to form a drain 1, as shown below. Figure 12h .

[0235] Figure 13 A partial top view of a semiconductor device provided in another embodiment of this application is shown. Figure 14 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 15 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 16 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the VV' tangent direction.

[0236] Reference Figures 13 to 16 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches 01 spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0237] In this embodiment, multiple first P-type semiconductor regions are respectively disposed on the same side of the drift layer, and the multiple first P-type semiconductor regions and the third portion region of the source region are spaced apart from each other. For example, multiple first P-type semiconductor regions are disposed on the same sidewall of multiple gate trenches, and the multiple first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches are spaced apart from each other. The third portion region of the source region is disposed between two adjacent first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches. That is, the third portion region of the source region is projected onto the semiconductor substrate between the orthogonal projections of two adjacent first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches onto the semiconductor substrate.

[0238] For example, refer to Figures 13 to 16In trench group GK1, a plurality of first P-type semiconductor regions 4a are disposed at the first sidewall S1 of the gate trench 01, and each first sidewall S1 of the gate trench in trench group GK1 is provided with one first P-type semiconductor region 4a. Furthermore, the plurality of first P-type semiconductor regions 4a are spaced apart from the third portion region 8c of the source region 8, meaning that between each pair of adjacent first P-type semiconductor regions 4a projected onto the semiconductor substrate, there is a portion of the source region 8 projected onto the semiconductor substrate.

[0239] For example, refer to Figures 13 to 16 In the trench group GK1, a plurality of first P-type semiconductor regions 4b are disposed at the second sidewall S2 of the gate trench, and each second sidewall S2 of the gate trench in the trench group GK1 is provided with one first P-type semiconductor region 4b. Furthermore, the plurality of first P-type semiconductor regions 4b are spaced apart from the third portion region 8c of the source region 8, meaning that between each pair of adjacent first P-type semiconductor regions 4b projected onto the semiconductor substrate, there is a portion of the source region 8 projected onto the semiconductor substrate.

[0240] For example, refer to Figures 13 to 16 In the trench group GK2, a plurality of first P-type semiconductor regions 4c are disposed at the first sidewall S1 of the gate trench, and each first sidewall S1 of the gate trench in the trench group GK2 is provided with one first P-type semiconductor region 4c. Furthermore, the plurality of first P-type semiconductor regions 4c are spaced apart from the third portion region 8c of the source region 8, meaning that between each pair of adjacent first P-type semiconductor regions 4c projected onto the semiconductor substrate, there is a portion of the source region 8 projected onto the semiconductor substrate.

[0241] For example, refer to Figures 13 to 16 In the trench group GK2, a plurality of first P-type semiconductor regions 4d are disposed at the second sidewall S2 of the gate trench, and each second sidewall S2 of the gate trench in the trench group GK2 is provided with one first P-type semiconductor region 4d. Furthermore, the plurality of first P-type semiconductor regions 4d are spaced apart from the third portion region 8c of the source region 8, meaning that between each pair of adjacent first P-type semiconductor regions 4d projected onto the semiconductor substrate, there is a portion of the source region 8 projected onto the semiconductor substrate.

[0242] In this embodiment, the edge of the orthographic projection of the first P-type semiconductor region onto the first plane is disposed outside the edge of the orthographic projection of the sidewall of the corresponding gate trench onto the first plane. For example, referring to... Figures 13 to 16Each first P-type semiconductor region 4a has its orthographic projection edge on the first plane located outside the orthographic projection edge of the first sidewall S1 of the corresponding gate trench in trench group GK1 on the first plane. Each first P-type semiconductor region 4b has its orthographic projection edge on the first plane located outside the orthographic projection edge of the second sidewall S2 of the corresponding gate trench in trench group GK1 on the first plane. Each first P-type semiconductor region 4c has its orthographic projection edge on the first plane located outside the orthographic projection edge of the first sidewall S1 of the corresponding gate trench in trench group GK2 on the first plane. Each first P-type semiconductor region 4d has its orthographic projection edge on the first plane located outside the orthographic projection edge of the second sidewall S2 of the corresponding gate trench in trench group GK2 on the first plane.

[0243] Alternatively, the edge of the orthographic projection of the first P-type semiconductor region onto the first plane can overlap with the orthographic projection of the sidewall of the corresponding gate trench onto the first plane. For example, when multiple gate trenches are divided into two trench groups, the edge of the orthographic projection of the first P-type semiconductor region on the first plane at the first side of one of the trench groups overlaps with the orthographic projection of the first sidewall of the corresponding gate trench in that trench group onto the first plane. The rest can be deduced similarly, and will not be elaborated further here.

[0244] In this embodiment, when there are multiple first P-type semiconductor regions disposed on the same side of the drift layer, a fourth portion of the active region is disposed between the gate trench and the corresponding first P-type semiconductor region. That is, the orthogonal projection of the active region onto the semiconductor substrate is between the orthogonal projection of the first sidewall S1 and the second sidewall S2 of the gate trench and the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate. For example, referring to… Figures 13 to 16In each gate trench of trench group GK1, a fourth portion region 8d1 of the active region 8 is disposed between the first sidewall S1 and the corresponding first P-type semiconductor region 4a. That is, the orthogonal projection of the first sidewall S1 of each gate trench in trench group GK1 onto the semiconductor substrate 2 and the orthogonal projection of the corresponding first P-type semiconductor region 4a onto the semiconductor substrate have the orthogonal projection of the fourth portion region 8d1 of the active region 8 onto the semiconductor substrate 2. In each gate trench of trench group GK1, a fourth portion region 8d2 of the active region 8 is disposed between the second sidewall S2 and the corresponding first P-type semiconductor region 4b. That is, the orthogonal projection of the fourth portion region 8d2 of the active region 8 onto the semiconductor substrate 2 is the orthogonal projection of the second sidewall S2 of each gate trench in trench group GK1 onto the semiconductor substrate 2 and the orthogonal projection of the corresponding first P-type semiconductor region 4b onto the semiconductor substrate. In each gate trench of trench group GK2, a fourth portion region 8d3 of the active region 8 is disposed between the first sidewall S1 and the corresponding first P-type semiconductor region 4c. That is, the orthogonal projection of the first sidewall S1 of each gate trench in trench group GK2 onto the semiconductor substrate 2 and the orthogonal projection of the corresponding first P-type semiconductor region 4c onto the semiconductor substrate have the orthogonal projection of the fourth portion region 8d3 of the active region 8 onto the semiconductor substrate 2. In each gate trench of trench group GK2, a fourth portion region 8d4 of the active region 8 is disposed between the second sidewall S2 and the corresponding first P-type semiconductor region 4d. That is, the orthogonal projection of the second sidewall S2 of each gate trench in trench group GK2 onto the semiconductor substrate 2 and the orthogonal projection of the corresponding first P-type semiconductor region 4d onto the semiconductor substrate has the orthogonal projection of the fourth portion region 8d4 of the active region 8 onto the semiconductor substrate 2.

[0245] For example, refer to Figure 13 and Figure 14 In this application, the drift layer further includes: a plurality of first shielding trenches 12 spaced apart from each other. Figure 13 Taking a plurality of first shielding trenches disposed between trench group GK1 and trench group GK2 as an example, the plurality of first shielding trenches 12 extend from the top of the drift layer 100 to the first N-type semiconductor region 3 in a third direction Z. Furthermore, the first shielding trenches 12 are disposed on both sides of the drift layer 100, and first P-type semiconductor regions 4 are disposed on the sidewalls and bottom of the first shielding trenches 12. For example, referring to… Figure 13 and Figure 14 In each trench group, a plurality of first shielding trenches 12 are respectively provided on the side of the first sidewall S1 and the second sidewall S2 of the gate trench 01 away from the filled first gate 71. For example, a first shielding trench 12 is provided at the second sidewall S2 of each gate trench 01 in trench group GK1, and a first shielding trench 12 is provided at the first sidewall S1 of each gate trench 01 in trench group GK2.

[0246] For example, refer to Figure 13 and Figure 14 Each first shielding trench 12 has a P-type semiconductor region on its sidewall. That is, each sidewall of each first shielding trench 12 has a P-type semiconductor region. Optionally, the P-type semiconductor region on the sidewall of each first shielding trench 12 in the first direction X can be used as the first P-type semiconductor region. For example, in the first direction, the first shielding trench 12 has a third sidewall S3 and a fourth sidewall S4 disposed opposite to each other. The P-type semiconductor region disposed at the third sidewall S3 of the first shielding trench 12 can be used as the first P-type semiconductor region 4b, and the P-type semiconductor region disposed at the fourth sidewall S4 of the first shielding trench 12 can be used as the first P-type semiconductor region 4c.

[0247] For example, refer to Figure 13 and Figure 14 Each first shielding trench 12 also has a P-type semiconductor region at its bottom. By providing a P-type semiconductor region at the bottom of the first shielding trench 12, this application further effectively shields the gate dielectric layer electric field at the bottom of the gate trench 01, thereby improving the robustness of the device operation.

[0248] For example, the doping concentration of the P-type semiconductor region at the bottom of the first shielding trench 12 is similar to or the same as the doping concentration of the first P-type semiconductor region. Optionally, an ion implantation process can be used to form the P-type semiconductor region at the bottom and sidewalls of the first shielding trench 12 in the same step.

[0249] Exemplarily, in this application, when there are multiple trench groups, adjacent trench groups share a first P-type semiconductor region disposed between the adjacent trench groups. Exemplarily, adjacent trench groups share a first shielding trench disposed between the adjacent trench groups. Further, adjacent trench groups share the third and fourth sidewalls and the bottom of the first shielding trench disposed between the adjacent trench groups. For example, refer to... Figure 13 and Figure 14 The trench group GK1 and the trench group GK2 share the third and fourth sidewalls of the first shielding trench 12 and the P-type semiconductor region at the bottom.

[0250] To prepare Figure 14 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 11 Steps S10 and S30 to S80 can be referred to the description of the preparation method above, and will not be repeated here.

[0251] In this embodiment, step S20 is as follows: First P-type semiconductor regions are formed on both sides of the drift layer, and multiple first P-type semiconductor regions are formed. These multiple first P-type semiconductor regions extend along a third direction from the top of the drift layer into the first N-type semiconductor region. Multiple first N-type semiconductor regions are spaced apart from each other on the same sidewall of each trench group, and a fourth portion of the source region exists between the gate trench and the corresponding first P-type semiconductor region. Furthermore, among the multiple first N-type semiconductor regions disposed on the same side of each trench group, a third portion of the source region exists between two adjacent first N-type semiconductor regions.

[0252] In some examples, step S20 may include:

[0253] First, a drift layer is etched to form a plurality of mutually spaced first shielding trenches extending upward along a third direction into a first N-type semiconductor region. Multiple mutually spaced first shielding trenches are formed on the same sidewall of each trench group, and a fourth portion of the source region is formed between the gate trench and the corresponding first shielding trench. Furthermore, in the plurality of first N-type semiconductor regions formed on the same side of each trench group, a third portion of the source region is formed between two adjacent first shielding trenches. The first and second sidewalls of the gate trenches are respectively provided with first shielding trenches on the side facing away from the corresponding first gate.

[0254] For example, a sixth mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The sixth mask layer is etched using a suitable etching process, either dry or wet, to form a sixth mask opening. This opening exposes the corresponding region in the drift layer where the first shielding trench needs to be formed, while the remaining regions of the drift layer are covered by the retained sixth mask layer. Then, a dry etching process is used to etch the drift layer exposed through the sixth mask opening until it reaches the first N-type semiconductor region. This creates multiple spaced-apart first shielding trenches on the same side of each trench group, and establishes a fourth portion of the source region between the gate trench and the corresponding first shielding trench. Additionally, a third portion of the source region is established between adjacent first shielding trenches on the same sidewall of each trench group.

[0255] Subsequently, an ion implantation process was used to implant P-type impurity ions into the sidewalls and bottom of each of the multiple first shielding trenches to form a P-type semiconductor region.

[0256] For example, using an ion implantation process, the sidewalls and bottom of each first shielding trench are p-type doped with impurities. Then, the sixth mask layer is removed. Afterwards, the semiconductor devices with p-type doped sidewalls and bottom of each first shielding trench are subjected to ion activation annealing and surface cleaning treatments to form the first p-type semiconductor region.

[0257] Figure 17 This illustration shows a partial top view of a semiconductor device provided in another embodiment of the present application. Figure 18 It shows Figure 17 The diagram shows a cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 19 It shows Figure 17 The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 20 It shows Figure 17 The diagram shows a cross-sectional view of the semiconductor device along the VV' tangent direction.

[0258] Reference Figures 17 to 20 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches 01 spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0259] In this embodiment, multiple first P-type semiconductor regions are respectively disposed on the same side of the drift layer, and the multiple first P-type semiconductor regions and the third portion region of the source region are spaced apart from each other. For example, multiple first P-type semiconductor regions are disposed on the same sidewall of multiple gate trenches, and the multiple first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches are spaced apart from each other. The third portion region of the source region is disposed between two adjacent first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches. That is, the third portion region of the source region is projected onto the semiconductor substrate between the orthogonal projections of two adjacent first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches onto the semiconductor substrate.

[0260] For example, refer to Figures 17 to 20In the trench group GK1, a plurality of first P-type semiconductor regions 4a are disposed at the first sidewall S1 of the gate trench, and each first sidewall S1 of the gate trench in the trench group GK1 is provided with one first P-type semiconductor region 4a. Furthermore, each of the plurality of first P-type semiconductor regions 4a has a third portion region 8c of the source region 8 projected onto the semiconductor substrate 2 between each two adjacent first P-type semiconductor regions 4a.

[0261] For example, refer to Figures 17 to 20 In the trench group GK1, a plurality of first P-type semiconductor regions 4b are disposed at the second sidewall S2 of the gate trench, and each second sidewall S2 of the gate trench in the trench group GK1 is provided with one first P-type semiconductor region 4b. Furthermore, each of the plurality of first P-type semiconductor regions 4b has a third portion region 8c of the source region 8 projected onto the semiconductor substrate between the orthogonal projections of two adjacent first P-type semiconductor regions 4b onto the semiconductor substrate.

[0262] For example, refer to Figures 17 to 20 In the trench group GK2, a plurality of first P-type semiconductor regions 4c are disposed at the first sidewall S1 of the gate trench, and each first sidewall S1 of the gate trench in the trench group GK2 is provided with one first P-type semiconductor region 4c. Furthermore, each of the plurality of first P-type semiconductor regions 4c has a third portion region 8c of the source region 8 projected onto the semiconductor substrate between the orthogonal projections of two adjacent first P-type semiconductor regions 4c onto the semiconductor substrate.

[0263] For example, refer to Figures 17 to 20 In the trench group GK2, a plurality of first P-type semiconductor regions 4d are disposed at the second sidewall S2 of the gate trench, and each second sidewall S2 of the gate trench in the trench group GK2 is provided with one first P-type semiconductor region 4d. Furthermore, between each pair of adjacent first P-type semiconductor regions 4d projected onto the semiconductor substrate, there is a third portion region 8c of the source region 8 projected onto the semiconductor substrate.

[0264] In this embodiment, the edge of the orthographic projection of the first P-type semiconductor region in the second direction is disposed outside the edge of the orthographic projection of the sidewall of the corresponding gate trench in the second direction. For example, referring to... Figures 17 to 20Each first P-type semiconductor region 4a has its orthographic projection edge in the second direction located outside the orthographic projection edge of the first sidewall S1 of the corresponding gate trench in trench group GK1 in the second direction. Each first P-type semiconductor region 4b has its orthographic projection edge in the second direction located outside the orthographic projection edge of the second sidewall S2 of the corresponding gate trench in trench group GK1 in the second direction. Each first P-type semiconductor region 4c has its orthographic projection edge in the second direction located outside the orthographic projection edge of the first sidewall S1 of the corresponding gate trench in trench group GK2 in the second direction. Each first P-type semiconductor region 4d has its orthographic projection edge in the second direction located outside the orthographic projection edge of the second sidewall S2 of the corresponding gate trench in trench group GK2 in the second direction.

[0265] In this embodiment, the gate trench contacts the corresponding first P-type semiconductor region through the corresponding gate dielectric layer. That is, the orthogonal projection of the gate dielectric layer disposed at the first sidewall S1 and the second sidewall S2 of the gate trench onto the semiconductor substrate contacts the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate. For example, referring to... Figures 17 to 20 In trench group GK1, the first sidewall S1 of each gate trench is in contact with the corresponding first P-type semiconductor region 4a through the corresponding gate dielectric layer. That is, the orthographic projection of the first sidewall S1 of each gate trench in trench group GK1 onto the semiconductor substrate 2 is in direct contact with the orthographic projection of the corresponding first P-type semiconductor region 4a onto the semiconductor substrate 2. Therefore, there is no orthographic projection of the fourth part of the source region 8 onto the semiconductor substrate between the orthographic projection of the first sidewall S1 of each gate trench in trench group GK1 onto the semiconductor substrate and the orthographic projection of the corresponding first P-type semiconductor region 4a onto the semiconductor substrate.

[0266] The second sidewall S2 of each gate trench in trench group GK1 is in contact with the corresponding first P-type semiconductor region 4b through the corresponding gate dielectric layer. That is, the orthographic projection of the second sidewall S2 of each gate trench in trench group GK1 onto the semiconductor substrate is in direct contact with the orthographic projection of the corresponding first P-type semiconductor region 4b onto the semiconductor substrate. Therefore, there is no orthographic projection of the fourth part of the source region 8 onto the semiconductor substrate between the orthographic projection of the second sidewall S2 of each gate trench in trench group GK1 onto the semiconductor substrate and the orthographic projection of the corresponding first P-type semiconductor region 4b onto the semiconductor substrate.

[0267] The first sidewall S1 of each gate trench in trench group GK2 is in contact with the corresponding first P-type semiconductor region 4c through the corresponding gate dielectric layer. That is, the orthographic projection of the first sidewall S1 of each gate trench in trench group GK2 onto the semiconductor substrate is in direct contact with the orthographic projection of the corresponding first P-type semiconductor region 4c onto the semiconductor substrate. Therefore, there is no orthographic projection of the fourth part of the source region 8 onto the semiconductor substrate between the orthographic projection of the first sidewall S1 of each gate trench in trench group GK2 onto the semiconductor substrate and the orthographic projection of the corresponding first P-type semiconductor region 4c onto the semiconductor substrate.

[0268] The second sidewall S2 of each gate trench in trench group GK2 is in contact with the corresponding first P-type semiconductor region 4d through the corresponding gate dielectric layer. That is, the orthographic projection of the second sidewall S2 of each gate trench in trench group GK2 onto the semiconductor substrate is in direct contact with the orthographic projection of the corresponding first P-type semiconductor region 4d onto the semiconductor substrate. Therefore, there is no orthographic projection of the fourth part of the source region 8 onto the semiconductor substrate between the orthographic projection of the second sidewall S2 of each gate trench in trench group GK2 onto the semiconductor substrate and the orthographic projection of the corresponding first P-type semiconductor region 4d onto the semiconductor substrate.

[0269] To prepare Figure 17 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 11 Steps S10 and S30 to S80 can be referred to the description of the preparation method above, and will not be repeated here.

[0270] In this embodiment, step S20 is:

[0271] On both sides of the drift layer, a first P-type semiconductor region is formed, extending from the top of the drift layer into a first N-type semiconductor region along a third direction. Multiple first shielding trenches are provided at intervals on the same sidewall of each trench group. Furthermore, among the multiple first P-type semiconductor regions provided on the same sidewall of each trench group, a third portion of the source region is located between two adjacent first P-type semiconductor regions.

[0272] In some examples, step S20 may include:

[0273] First, the two sides of the drift layer are etched to form a first shielding trench extending upward along a third direction into the first N-type semiconductor region within the drift layer. Multiple first shielding trenches are spaced apart on the same sidewall of each trench group. Among the multiple first shielding trenches on the same sidewall of each trench group, the third portion of the source region is projected onto the semiconductor substrate between two adjacent first shielding trenches. The first sidewall S1 and the second sidewall S2 of the gate trench each have a first shielding trench on the side opposite to the filled first gate.

[0274] For example, a seventh mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The seventh mask layer is etched using a suitable etching process, either dry or wet, to form a seventh mask opening. This opening exposes the corresponding region in the drift layer where the first shielding trench needs to be formed, while the remaining region of the drift layer is covered by the retained seventh mask layer. Then, a dry etching process is used to etch the drift layer exposed through the seventh mask opening until it reaches the first N-type semiconductor region 3, thus creating multiple spaced-apart first shielding trenches on the same sidewall of each trench group. Furthermore, a portion of the source region is located between two adjacent first shielding trenches on the same sidewall of each trench group.

[0275] Subsequently, an ion implantation process was used to implant P-type impurity ions into the sidewalls and bottom of each of the multiple first shielding trenches to form a P-type semiconductor region.

[0276] For example, using an ion implantation process, the sidewalls and bottom of each first shielding trench are p-type doped with impurities. Then, the seventh mask layer is removed. Afterwards, the semiconductor devices with p-type doped sidewalls and bottom of each first shielding trench are subjected to ion activation annealing and surface cleaning treatments to form the first p-type semiconductor region.

[0277] Figure 21 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application is shown. Figure 22 It shows Figure 21 The diagram shows a partial top view of the semiconductor device. Figure 23 It shows Figure 22 The diagram shows a cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 24 It shows Figure 22 The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 25 It shows Figure 22 The diagram shows a cross-sectional view of the semiconductor device along the VV' tangent direction.

[0278] Reference Figures 21 to 25In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches 01 spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. Furthermore, the drift layer includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0279] In this embodiment, the first P-type semiconductor regions disposed on the same side of the drift layer can be a single, integral region. For example, the first P-type semiconductor regions disposed on the same side of the trench group can be a single, integral region. That is, the first P-type semiconductor regions disposed on the first side of the same trench group are one, and the first P-type semiconductor regions disposed on the second side of the same trench group are also one. The orthogonal projection of each first P-type semiconductor region onto the semiconductor substrate is a strip-shaped region extending along the second direction. Each first P-type semiconductor region extends along the second direction from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench. Furthermore, when there are multiple trench groups, adjacent trench groups share the first P-type semiconductor region disposed between adjacent trench groups. For example, refer to... Figures 21 to 25 A strip-shaped first P-type semiconductor region 4a is provided at the first sidewall S1 of the gate trench in trench group GK1. A strip-shaped first P-type semiconductor region 4b is shared at the second sidewall S2 of the gate trench in trench group GK1 and the first sidewall S1 of the gate trench in trench group GK2. A strip-shaped first P-type semiconductor region 4c is provided at the second sidewall S2 of the gate trench in trench group GK2.

[0280] For example, in this application, a fourth portion of the source region is located between the gate trench and the corresponding first P-type semiconductor region. That is, the fourth portion of the source region is located between the orthogonal projection of the first sidewall S1 and the second sidewall S2 of the gate trench onto the semiconductor substrate and the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate. For example, referring to… Figures 21 to 23In trench group GK1, the gate trench 01 and the corresponding first P-type semiconductor region 4a have a fourth portion region 8d1 of the source region 8. That is, the orthogonal projection of the first sidewall S1 of the gate trench in trench group GK1 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4a onto the semiconductor substrate have the orthogonal projection of the fourth portion region 8d1 of the source region 8 onto the semiconductor substrate. Similarly, in trench group GK1, the gate trench 01 and the corresponding first P-type semiconductor region 4b have a fourth portion region 8d2 of the source region 8. That is, the orthogonal projection of the second sidewall S2 of the gate trench in trench group GK1 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4b onto the semiconductor substrate have the orthogonal projection of the fourth portion region 8d2 of the source region 8 onto the semiconductor substrate. In trench group GK2, the gate trench 01 and the corresponding first P-type semiconductor region 4c have a fourth portion region 8d3 of the source region 8. That is, the orthogonal projection of the first sidewall S1 of the gate trench in trench group GK2 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4b onto the semiconductor substrate have the orthogonal projection of the fourth portion region 8d3 of the source region 8 onto the semiconductor substrate. In trench group GK2, the gate trench 01 and the corresponding first P-type semiconductor region 4d have a fourth portion region 8d4 of the source region 8. That is, the orthogonal projection of the second sidewall S2 of the gate trench in trench group GK2 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4c onto the semiconductor substrate have the orthogonal projection of the fourth portion region 8d4 of the source region 8 onto the semiconductor substrate.

[0281] In this embodiment, the drift layer further includes a second shielding trench, which is disposed on both sides of the drift layer, and the first P-type semiconductor region is disposed within the second shielding trench. Exemplarily, the first P-type semiconductor region can be a P-type epitaxial layer disposed within the second shielding trench. For example, refer to… Figures 21 to 23 The drift layer also includes second shielding trenches 13 (e.g., 13a, 13b, 13c), which are disposed on both sides of the drift layer, and the first P-type semiconductor region is disposed within the second shielding trenches. The second shielding trenches 13 (e.g., 13a, 13b, 13c) extend from the top of the drift layer into the first N-type semiconductor region along a third direction Z. Furthermore, the first sidewall S1 and the second sidewall S2 of the gate trench are respectively provided with second shielding trenches on the side opposite to the corresponding first gate. Each second shielding trench (e.g., 13a, 13b, 13c) is filled with a P-type epitaxial layer, which serves as the first P-type semiconductor region. Exemplarily, the orthogonal projection of the second shielding trenches 13a to 13c onto the semiconductor substrate is a strip-shaped region extending along a second direction. When there are multiple trench groups, adjacent trench groups share the first P-type semiconductor region disposed between adjacent trench groups. Furthermore, two adjacent trench groups share a second shielding trench located between the two adjacent trench groups.

[0282] For example, refer to Figures 21 to 25 In trench group GK1, the first sidewall S1 of the gate trench is provided with a second shielding trench 13a, which is filled with a P-type epitaxial layer, serving as the first P-type semiconductor region 4a. The second sidewall S2 of the gate trench in trench group GK1 and the first sidewall S1 of the gate trench in trench group GK2 share a second shielding trench 13b, which is filled with a P-type epitaxial layer, serving as the first P-type semiconductor region 4b. In trench group GK2, the second sidewall S2 of the gate trench is provided with a second shielding trench 13c, which is filled with a P-type epitaxial layer, serving as the first P-type semiconductor region.

[0283] For example, refer to Figure 23 The distance hd4 between the second shielding trench 13 and the top of the drift layer 100 is greater than the distance hd2 between the gate trench 01 and the top of the drift layer 100. That is, the depth of the second shielding trench 13 in the third direction Z is greater than the depth of the gate trench 01 in the third direction Z. Thus, when the second shielding trench 13 is filled with an epitaxial layer, the depth of the epitaxial layer in the third direction Z can be greater than the depth of the gate trench 01 in the third direction Z, thereby ensuring that the depth of the first P-type semiconductor region in the third direction Z is greater than the depth of the gate trench 01 in the third direction Z.

[0284] This application does not limit the material used to form the P-type epitaxial layer. For example, the material used to form the P-type epitaxial layer may include SiC doped with P-type impurities.

[0285] To prepare Figure 21 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 11 Steps S10 and S30 to S80 can be referred to the description of the preparation method above, and will not be repeated here.

[0286] In this embodiment, step S20 is as follows: a first P-type semiconductor region is formed on both sides of the drift layer. The first P-type semiconductor region extends from the top of the drift layer into the first N-type semiconductor region along a third direction. A strip-shaped first P-type semiconductor region is provided at the same sidewall of each trench group, and a fourth portion of the source region is formed between the first sidewall S1 and the second sidewall S2 of the gate trench and the corresponding first P-type semiconductor region.

[0287] In some examples, step S20 may include:

[0288] First, the two sides of the drift layer are etched to form a second shielding trench extending upward along a third direction into the first N-type semiconductor region. The first sidewall S1 and the second sidewall S2 of the gate trench have a fourth portion of the source region projected onto the semiconductor substrate between their orthogonal projections onto the semiconductor substrate and the corresponding second shielding trench. The second shielding trench is formed on the side of the first sidewall S1 and the second sidewall S2 of the gate trench facing away from the corresponding first gate.

[0289] For example, an eighth mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The eighth mask layer is etched using a suitable etching process, either dry or wet, to form an opening in the eighth mask. This opening exposes the corresponding region in the drift layer where the second shielding trench needs to be formed, while the remaining regions of the drift layer are covered by the retained eighth mask layer. Then, a dry etching process is used to etch the drift layer exposed through the eighth mask opening until it reaches the first N-type semiconductor region 3, creating a strip-shaped second shielding trench on the same sidewall of each trench group. This ensures that the first sidewall S1 and the second sidewall S2 of the gate trench have a fourth portion of the source region between them and the corresponding second shielding trench.

[0290] Subsequently, a P-type epitaxial layer is epitaxially grown on the entire drift layer, and the epitaxial layer fills each of the plurality of second shielding trenches.

[0291] For example, using an epitaxial process, SiC material doped with P-type impurities is epitaxially grown on the entire drift layer where the second shielding trench is formed, and the SiC material doped with P-type impurities fills each of the second shielding trenches as a P-type epitaxial layer. After the second shielding trenches are filled with SiC material doped with P-type impurities, the entire drift layer is covered with a SiC material film doped with P-type impurities.

[0292] Subsequently, a planarization process is used to planarize the epitaxial layer. The process stops when the top of the drift layer (such as the source region of the drift layer) is exposed. The remaining epitaxial layers except the epitaxial layer disposed in the second shielding trench are removed. The epitaxial layer disposed in the second shielding trench then serves as the first P-type semiconductor region.

[0293] For example, planarization processes such as Chemical Mechanical Polishing (CMP) are used to planarize the epitaxial layer. The planarization process is stopped when the top of the drift layer (such as the source region of the drift layer) is exposed, so as to retain the epitaxial layer disposed in the second shielding trench and remove the rest of the epitaxial layer. The retained epitaxial layer can then serve as the first P-type semiconductor region.

[0294] In this application, the second shielding trenches disposed on the same side of the drift layer can also be multiple trenches arranged in a mutually spaced manner. For example, the second shielding trenches disposed on the same side of each trench group can also be multiple trenches arranged in a mutually spaced manner, in which case the epitaxial layer filled in each second shielding trench can serve as a first P-type semiconductor region, thus realizing a scheme in which multiple first P-type semiconductor regions disposed on the same sidewall of multiple gate trenches are spaced apart from each other. The implementation method when the second shielding trenches disposed on the same sidewall of each trench group can also be multiple trenches arranged in a mutually spaced manner can refer to the implementation method described above when the first shielding trenches disposed on the same sidewall of each trench group are also multiple trenches arranged in a mutually spaced manner, and will not be elaborated here.

[0295] Figure 26 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application is shown. Figure 27 It shows Figure 26 The illustrated embodiment provides a partial top view of the semiconductor device. Figure 28 It shows Figure 27 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 29 It shows Figure 27 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 30 It shows Figure 27 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the VV' tangent direction.

[0296] Reference Figures 26 to 30 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches 01 spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. Furthermore, the drift layer includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0297] In this embodiment, instead of setting the first and second shielding trenches in the drift layer, an ion implantation process is used to directly dope the drift layer with P-type impurities to form the first P-type semiconductor region.

[0298] In this embodiment, the first P-type semiconductor regions disposed on the same side of the drift layer can be considered as a single, integral region. For example, the first P-type semiconductor regions disposed on the first side of the same trench group can be considered as a single, integral region, and the first P-type semiconductor regions disposed on the second side of the same trench group can also be considered as a single, integral region. The orthographic projection of each first P-type semiconductor region onto the semiconductor substrate is a strip-shaped region extending along a second direction. Each first P-type semiconductor region extends along the second direction from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench. Furthermore, when there are multiple trench groups, adjacent trench groups share the first P-type semiconductor region disposed between adjacent trench groups. For example, refer to… Figure 27 and Figure 28 A strip-shaped first P-type semiconductor region 4a is provided at the first sidewall S1 of the gate trench in trench group GK1. A strip-shaped first P-type semiconductor region 4b is shared at the second sidewall S2 of the gate trench in trench group GK1 and the first sidewall S1 of the gate trench in trench group GK2. A strip-shaped first P-type semiconductor region 4c is provided at the second sidewall S2 of the gate trench in trench group GK2.

[0299] For example, in this application, a fourth portion of the source region is located between the gate trench and the corresponding first P-type semiconductor region. That is, the fourth portion of the source region is located between the orthogonal projection of the first sidewall S1 and the second sidewall S2 of the gate trench onto the semiconductor substrate and the orthogonal projection of the corresponding first P-type semiconductor region onto the semiconductor substrate. For example, referring to… Figures 27 to 29In trench group GK1, the first sidewall S1 of the gate trench has a fourth portion region 8d1 of the source region between it and the corresponding first P-type semiconductor region 4a. Specifically, the orthogonal projection of the first sidewall S1 of the gate trench in trench group GK1 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4a onto the semiconductor substrate form the orthogonal projection of the fourth portion region 8d1 of the source region 8 onto the semiconductor substrate. Similarly, the second sidewall S2 of the gate trench in trench group GK1 has a fourth portion region 8d2 of the source region between it and the corresponding first P-type semiconductor region 4b. Specifically, the orthogonal projection of the second sidewall S2 of the gate trench in trench group GK1 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4b onto the semiconductor substrate form the orthogonal projection of the fourth portion region 8d2 of the source region 8 onto the semiconductor substrate. In trench group GK2, the first sidewall S1 of the gate trench has a fourth portion region 8d3 of the source region between it and the corresponding first P-type semiconductor region 4b. Specifically, the orthogonal projection of the first sidewall S1 of the gate trench in trench group GK2 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4b onto the semiconductor substrate form the orthogonal projection of the fourth portion region 8d3 of the source region 8 onto the semiconductor substrate. Similarly, in trench group GK2, the second sidewall S2 of the gate trench has a fourth portion region 8d4 of the source region between it and the corresponding first P-type semiconductor region 4c. Specifically, the orthogonal projection of the second sidewall S2 of the gate trench in trench group GK2 onto the semiconductor substrate and the orthogonal projection of the first P-type semiconductor region 4c onto the semiconductor substrate form the orthogonal projection of the fourth portion region 8d4 of the source region 8 onto the semiconductor substrate.

[0300] For example, in this application, when there are multiple trench groups, adjacent trench groups share a first P-type semiconductor region disposed between the adjacent two trench groups. For example, refer to Figures 27 to 29 Trench group GK1 and trench group GK2 share the first P-type semiconductor region 4b.

[0301] To prepare Figure 26 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 11 Steps S10 and S30 to S80 can be referred to the description of the preparation method above, and will not be repeated here.

[0302] In this embodiment, step S20 is as follows: using an ion implantation process, a first P-type semiconductor region extending upward along a third direction into the first N-type semiconductor region is formed on both sides of the drift layer. Each first P-type semiconductor region is projected onto the semiconductor substrate as a strip-shaped region extending along a second direction, and a fourth portion of the source region exists between the first sidewall S1 and the second sidewall S2 of the gate trench and the corresponding first P-type semiconductor region.

[0303] In some examples, step S20 may include:

[0304] A ninth mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The ninth mask layer is etched using a suitable etching process, either dry or wet, to form an opening in the ninth mask. This opening exposes the corresponding region of the drift layer where the first P-type semiconductor region needs to be formed, while the remaining areas of the drift layer are covered by the retained ninth mask layer. Next, an ion implantation process is used to dope the drift layer exposed through the ninth mask opening with P-type impurities. The ninth mask layer is then removed. Finally, the semiconductor device with the P-type impurity-doped drift layer undergoes ion-activated annealing and surface cleaning treatments to form the first P-type semiconductor region.

[0305] In this application, the first P-type semiconductor region disposed on the same side of each drift layer can also be multiple regions disposed in relation to each other. For example, the first P-type semiconductor region disposed on the same sidewall of each trench group can also be multiple regions disposed in relation to each other. The implementation method where the first P-type semiconductor region disposed on the same sidewall of each trench group can also be multiple regions disposed in relation to each other can refer to the implementation method described above where the first P-type semiconductor region disposed on the same sidewall of each trench group is also multiple regions, and will not be elaborated upon here.

[0306] Figure 31 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application is shown. Figure 32 It shows Figure 31 The illustrated embodiment provides a partial top view of the semiconductor device. Figure 33 It shows Figure 32 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 34 It shows Figure 32 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 35 It shows Figure 32 The illustrated embodiment provides a schematic cross-sectional view of the semiconductor device along the VV' tangent direction.

[0307] Reference Figures 31 to 35In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches 01 spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. Furthermore, the drift layer includes: a first N-type semiconductor region 3, a second N-type semiconductor region 14, a first P-type semiconductor region 4, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0308] In this embodiment, the drift layer further includes a second N-type semiconductor region 14, which is disposed between the first N-type semiconductor region 3 and the second P-type semiconductor region 5. Furthermore, the doping concentration of the second N-type semiconductor region 14 is greater than the doping concentration of the first N-type semiconductor region 3, and the doping concentration of the second N-type semiconductor region 14 is less than the doping concentration of the source region 8.

[0309] This application does not limit the doping concentration of the second N-type semiconductor region 14; its doping concentration can meet the above requirements.

[0310] In this application, by providing a second N-type semiconductor region in the drift layer, the diffusion resistance of the current in the device at the upper end of the drift layer can be reduced.

[0311] To prepare Figure 31 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 11 Steps S20 to S80 can be referred to the description of the preparation method above, and will not be repeated here.

[0312] In this embodiment, step S10 is: epitaxially growing a drift layer on an N-type semiconductor substrate, and forming a first N-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate in the drift layer.

[0313] In some examples, step S10 may include:

[0314] First, an epitaxial layer is grown on an N-type semiconductor substrate using an epitaxial process.

[0315] For example, using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate to form a drift layer 100 with a set thickness DS0.

[0316] This application does not limit the specific value of the thickness DS0. In practical applications, the specific value of the thickness DS0 can be determined according to the needs of the actual application environment.

[0317] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer to form a second N-type semiconductor region, a second P-type semiconductor region, and a source region. The regions in the drift layer that are not ion implanted form a first N-type semiconductor region. The formed second P-type semiconductor region is positioned between the second N-type semiconductor region and the source region, and the first N-type semiconductor region is positioned between the second N-type semiconductor region and the semiconductor substrate.

[0318] For example, firstly, an ion implantation process is used to dope the surface of the drift layer with N-type impurities, forming a second N-type semiconductor region. Then, an ion implantation process is used to dope the surface of the drift layer with P-type impurities, forming a second P-type semiconductor region. Next, a tenth mask layer is formed on the drift layer (this tenth mask layer can be a mask formed of silicon dioxide, polysilicon, or silicon nitride). A suitable etching process, either dry or wet, is used to etch the tenth mask layer, forming a tenth mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining tenth mask layer covers the rest of the drift layer. Then, an ion implantation process is used to dope the surface of the drift layer with N-type impurities, forming the source region. Finally, the tenth mask layer is removed.

[0319] Alternatively, first, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form a second N-type semiconductor region. Then, an ion implantation process is used to dope the surface of the drift layer with P-type impurities to form a second P-type semiconductor region. Finally, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region.

[0320] In this application, features in different embodiments may be combined with each other without contradiction.

[0321] This application also provides a power conversion circuit for converting alternating current (AC) and / or direct current (DC) to output direct current (DC). For example, the power conversion circuit can be an AC-to-DC converter and / or a DC-to-DC converter. Exemplarily, the power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. Because the semiconductor devices described above have good performance, the power conversion circuit including these semiconductor devices also has good performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0322] This application also provides a vehicle, which includes a load and a power conversion circuit provided in this application embodiment. The power conversion circuit converts alternating current and / or direct current into direct current before inputting it into the load. Because the power conversion circuit has good performance, the vehicle including the power conversion circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and repeated details will not be elaborated further.

[0323] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized by, Comprise: A semiconductor substrate of N type; A drift layer comprising a first N type semiconductor region, a second P type semiconductor region and a source region, and a first P type semiconductor region, which are sequentially stacked on the semiconductor substrate, the first P type semiconductor region being arranged on both sides of the drift layer, the first P type semiconductor region extending from the top of the drift layer into the first N type semiconductor region along a third direction perpendicular to the plane in which the semiconductor substrate lies; A plurality of gate trenches arranged at intervals from each other, wherein the plurality of gate trenches extend along a first direction parallel to the plane in which the semiconductor substrate lies, and are arranged along a second direction parallel to the plane in which the semiconductor substrate lies, the plurality of gate trenches extending from the top of the drift layer into the first N type semiconductor region along the third direction, and the distance between the bottom of the first P type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the gate trench and the top of the drift layer; A gate comprising a first gate and a second gate in contact with each other, the first gate being arranged in the gate trench through a gate dielectric layer, and the second gate being arranged on the top of the drift layer through the gate dielectric layer; An interlayer dielectric layer covering the side of the gate away from the semiconductor substrate, and covering the gate and a first partial region of the source region, the interlayer dielectric layer being provided with a contact hole extending along the second direction, the contact hole being used to expose the first P type semiconductor region and a second partial region of the source region; A source electrode covering the side of the interlayer dielectric layer away from the semiconductor substrate, and covering the contact hole, the interlayer dielectric layer, the first P type semiconductor region and the second partial region of the source region; A drain electrode arranged on the side of the semiconductor substrate away from the drift layer, and covering the semiconductor substrate; Wherein, the first direction, the second direction and the third direction are arranged at intersections with each other.

2. The semiconductor device of claim 1, wherein, The orthogonal projection of the first P type semiconductor region on a first plane composed of the second direction and the third direction covers the orthogonal projection of the gate trench on the first plane.

3. The semiconductor device of claim 2, wherein, The first P type semiconductor regions arranged on the same side of the drift layer are an integral region; The orthogonal projection of the first P type semiconductor region on the semiconductor substrate is a strip-shaped region extending along the second direction.

4. The semiconductor device of claim 2, wherein, The first P type semiconductor region comprises a plurality of regions arranged on the same side of the drift layer, and a third partial region of the source region is a plurality of regions, the plurality of regions of the first P type semiconductor region and the plurality of regions of the third partial region of the source region being arranged at intervals from each other.

5. The semiconductor device according to any one of claims 1 to 4, wherein The orthogonal projection of the first P type semiconductor region on the semiconductor substrate and the orthogonal projection of the gate trench on the semiconductor substrate do not overlap each other.

6. The semiconductor device of claim 5, wherein, There is a fourth partial region of the source region between the gate trench and the first P type semiconductor region.

7. The semiconductor device of claim 5, wherein, When the first P type semiconductor regions arranged on the same side of the drift layer are a plurality of regions, the gate trench is in contact with the corresponding first P type semiconductor region through the corresponding gate dielectric layer.

8. The semiconductor device according to any one of claims 1 to 4, wherein The drift layer further comprises a first shielding trench. The first shielding trench is arranged on two sides of the drift layer, and a sidewall and a bottom of the first shielding trench are provided with the first P-type semiconductor region.

9. The semiconductor device of claim 8, wherein, The first shielding trench is filled with a material of the gate.

10. The semiconductor device according to any one of claims 1 to 4, wherein The drift layer further comprises a second shielding trench. The second shielding trench is arranged on two sides of the drift layer, and the first P-type semiconductor region is arranged in the second shielding trench.

11. The semiconductor device of claim 10, wherein, The first P-type semiconductor region is a P-type epitaxial layer arranged in the second shielding trench.

12. The semiconductor device according to any one of claims 1 to 4, wherein The plurality of gate trenches are divided into at least one trench group.

13. The semiconductor device of claim 12, wherein, The trench groups are multiple, and two adjacent trench groups share a first P-type semiconductor region arranged between the two adjacent trench groups.

14. The semiconductor device of claim 13, wherein, Two adjacent trench groups share a first shielding trench or a second shielding trench arranged between the two adjacent trench groups.

15. The semiconductor device according to any one of claims 1 to 4, wherein The drift layer further comprises a second N-type semiconductor region arranged between the first N-type semiconductor region and the second P-type semiconductor region. A doping concentration of the second N-type semiconductor region is greater than a doping concentration of the first N-type semiconductor region, and the doping concentration of the second N-type semiconductor region is less than a doping concentration of the source region.

16. The semiconductor device of any one of claims 1-4, wherein, Materials of the semiconductor substrate and the drift layer are SiC.

17. A method of manufacturing a semiconductor device, characterized by, Comprise: An epitaxial growth of a drift layer on an N-type semiconductor substrate, and in the drift layer, a first N-type semiconductor region, a second P-type semiconductor region and a source region are sequentially arranged on the semiconductor substrate; A first P-type semiconductor region is formed on two sides of the drift layer, and the first P-type semiconductor region extends from a top of the drift layer into the first N-type semiconductor region along a third direction perpendicular to a plane in which the semiconductor substrate is located; Etching the drift layer to form a plurality of gate trenches arranged in the drift layer and extending from the top of the drift layer into the first N-type semiconductor region along the third direction, the plurality of gate trenches extend along a first direction parallel to the plane in which the semiconductor substrate is located, and are arranged along a second direction parallel to the plane in which the semiconductor substrate is located; a distance between a bottom of the first P-type semiconductor region and the top of the drift layer is greater than a distance between a bottom of the gate trench and the top of the drift layer; the first direction, the second direction and the third direction are arranged to intersect each other; A gate dielectric layer is formed in the gate trench; A first gate of the gate is formed in the gate trench in which the gate dielectric layer is formed, and a second gate of the gate is formed on the top of the drift layer, and the first gate and the second gate are in contact with each other; An interlayer dielectric layer covering the entire drift layer is formed on the gate; The interlayer dielectric layer is etched to form a contact hole for exposing the first P-type semiconductor region and a second part of the source region, and the interlayer dielectric layer covers a first part of the source region and completely covers the gate; A source is formed on a side of the interlayer dielectric layer away from the semiconductor substrate, the source covering the contact hole and contacting the first P-type semiconductor region and the second part of the source region, and a drain is formed on a side of the semiconductor substrate away from the drift layer.

18. The method of producing a semiconductor device according to Claim 17, wherein The first P-type semiconductor region is formed on both sides of the drift layer, including: The two sides of the drift layer are etched to form a first shielding trench in the drift layer extending into the first N-type semiconductor region in the third direction; The first P-type semiconductor region is formed on both sides of the drift layer by ion implantation process on the sidewall and bottom of the first shielding trench.

19. The method of producing a semiconductor device according to Claim 17, wherein The first P-type semiconductor region is formed on both sides of the drift layer, including: The two sides of the drift layer are etched to form a second shielding trench in the drift layer extending into the first N-type semiconductor region in the third direction; An epitaxial layer of P-type is epitaxially grown on the entire drift layer, and the epitaxial layer fills each of the second shielding trenches; The epitaxial layer is planarized by a planarization process, and the remaining epitaxial layer outside the epitaxial layer disposed in the second shielding trench is removed when the top of the drift layer is exposed; wherein the epitaxial layer disposed in the second shielding trench serves as the first P-type semiconductor region.

20. The method of producing a semiconductor device according to Claim 17, wherein The first P-type semiconductor region is formed on both sides of the drift layer by ion implantation process on both sides of the drift layer extending into the first N-type semiconductor region in the third direction. The power conversion circuit is used to convert alternating current and / or direct current into direct current.

21. A power conversion circuit, characterized by, The power conversion circuit includes a circuit board and one or more semiconductor devices as claimed in any one of claims 1-16, the semiconductor device being connected to the circuit board. The power conversion circuit includes a load and a power conversion circuit as claimed in claim 21, the power conversion circuit being used to convert alternating current and / or direct current into direct current and input to the load.

22. A vehicle characterized by ​

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