A signal processing platform system for implementing time and frequency synchronization

Abstract

A signal processing platform system for realizing time synchronization and frequency synchronization comprises at least one processing system, a GPS module connected with a signal processing module to transmit time information and 1PPS signals, a circularly polarized antenna connected with a radio frequency front-end module through an antenna feed interface, a signal output end of the radio frequency front-end module connected with a signal input end of a radio frequency amplification module, a signal output end of the radio frequency amplification module connected with a signal input end of the signal processing module, and a signal output end of the signal processing module connected with a signal input end of the circularly polarized antenna through an Ethernet interface and an antenna feed interface to transmit signals. The application can effectively capture and monitor spatial spectrum signals, capture and monitor spectrum signals in a specified spatial range, and obtain wireless signals of a specified frequency. Time synchronization and frequency synchronization can be realized under a multi-stage system, so that the time and frequency of the whole system are consistent, and the social and economic benefits are remarkable.

Description

TECHNICAL FIELD

[0001] The present application relates to signal processing, in particular to a signal processing platform system for realizing time synchronization and frequency synchronization. BACKGROUND

[0002] Clock synchronization technology is a very key technology, which has been widely used in communication, military, transportation, industrial automation and other fields. In distributed data systems, the use of this technology can greatly improve the time consistency and accuracy of data collected by each node in the system, thereby improving the stability and reliability of the entire system. There are multiple solutions to related fields at home and abroad, mainly as follows:

[0003] 1. Synchronized clock technology based on time service center, the time service center transmits standard time and frequency signals to each collection point to realize the unification of sampling time and frequency of the entire system. The typical technology is GPS clock synchronization technology, which communicates with the GPS satellite and the ground GPS receiving equipment multiple times, calculates the distance between the GPS receiving equipment and the corresponding satellite, and transmits the time delay parameters and other information generated by the satellite signal to the GPS equipment. Through these parameters, the GPS transmission message is corrected.

[0004] 2. Clock synchronization technology based on NTP network time protocol, its working principle is to add time mark in the application layer. This protocol is flexible and easy to implement.

[0005] The frequency synchronization signal in a general hierarchical system or distributed networking system is the GPS second pulse signal and the signal of the local system clock crystal oscillator. The long-term stability of the GPS second pulse and the short-term stability of the local system clock are used to provide a reliable stable clock for the system. The crystal oscillator generally selects an oven-controlled crystal oscillator (OCXO), but due to the frequency adjustment range of the oven-controlled crystal oscillator, if the frequency adjustment range of the oven-controlled crystal oscillator exceeds the frequency adjustment range required by the design, the frequency calibration cannot be performed correctly, and the frequency synchronization processing cannot be performed, resulting in system failure. SUMMARY

[0006] In view of the above problems, the present application aims to provide a signal processing platform system for realizing time synchronization and frequency synchronization, which can effectively solve the problem that the existing system is easily affected and the frequency synchronization is invalid.

[0007] In order to achieve the above-mentioned purpose, the technical scheme solved by the present application is a signal processing platform system for realizing time synchronization and frequency synchronization, comprising at least one processing system, wherein the processing system comprises a GPS module, a signal processing module, a radio frequency amplification module, a radio frequency front-end module, a circularly polarized antenna and a power module; the GPS module is connected with a signal input end 1 of the signal processing module, and transmits time information and a 1PPS signal; the circularly polarized antenna is connected with a signal input end 1 of the radio frequency front-end module through an antenna feed interface; a signal output end 3 of the radio frequency front-end module is connected with a signal input end 1 of the radio frequency amplification module; a signal output end 3 and a signal output end 4 of the radio frequency amplification module are connected with a signal input end 4 and a signal input end 5 of the signal processing module; a signal output end 2 and a signal output end 3 of the signal processing module are connected with a signal input end 1 of the circularly polarized antenna through an Ethernet interface and the antenna feed interface respectively to transmit signals; and the power module is connected with a power input end 6 of the GPS module, a power input end 2 of the signal processing module, a power input end 2 of the radio frequency amplification module and a power input end 2 of the radio frequency front-end module respectively to supply power.

[0008] The present application can effectively capture and monitor spatial spectrum signals, capture and monitor spectrum signals in a specified spatial range, and acquire wireless signals of a specified frequency. Time synchronization and frequency synchronization can be realized in a multi-stage system, so that the time and frequency of the whole system are consistent, and the social and economic benefits are remarkable. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a system block diagram of the present application.

[0010] Figure 2 is a radio frequency amplification module block diagram of the present application.

[0011] Figure 3 is a radio frequency front-end module block diagram of the present application.

[0012] Figure 4 is a connection block diagram of time and frequency in a multi-stage system of the present application.

[0013] Figure 5 is an algorithm flow chart of time delay compensation of the present application. DETAILED DESCRIPTION

[0014] The specific implementation of the present application is described in detail below in combination with the drawings and examples.

[0015] In combination with the drawings and examples, Figure 1The application discloses a signal processing platform system for realizing time synchronization and frequency synchronization, which comprises at least one processing system, wherein the processing system comprises a GPS module 1, a signal processing module 2, a radio frequency amplification module 3, a radio frequency front-end module 4, a circularly polarized antenna 5 and a power supply module 6; the GPS module 1 is connected with a signal input end 1 of the signal processing module 2 and is used for transmitting time information and a 1PPS signal; the circularly polarized antenna 5 is connected with a signal input end 1 of the radio frequency front-end module 4 through an antenna feed interface; a signal output end 3 of the radio frequency front-end module 4 is connected with a signal input end 1 of the radio frequency amplification module 3; signal output ends 3 and 4 of the radio frequency amplification module 3 are connected with signal input ends 4 and 5 of the signal processing module 2; signal output ends 2 and 3 of the signal processing module 2 are respectively connected with a load through an Ethernet and are connected with a signal input end 1 of the circularly polarized antenna 5 through the antenna feed interface to transmit signals; and the power supply module 6 is connected with power input ends 6 of the GPS module 1 and the signal processing module 2, a power input end 2 of the radio frequency amplification module 3 and a power input end 2 of the radio frequency front-end module 4 to supply power.

[0016] After the circularly polarized antenna 5 detects the frequency spectrum signals in a specified space range, the signals are transmitted to the radio frequency front-end module 4, the selected frequency is filtered and amplified by the radio frequency front-end module 4 and is transmitted to the radio frequency amplification module 3, the radio frequency amplification module 3 receives the data transmitted by the radio frequency front-end module 4 and performs low-noise amplification, the data is transmitted to the signal processing module 2, after being processed by the signal processing module 2, the data is transmitted out through the Ethernet and the circularly polarized antenna 5, and the frequency selection and filtering of the signals are realized.

[0017] The GPS module 1 in the system of the application adopts a UT4B0 module of Hejiantong, which is an ns-level high-precision timing board card, can simultaneously track BDS, GPS, GLONASS, Galileo and other full-system multi-frequency satellite signals and perform multi-frequency anti-interference processing, and significantly improves the stability and reliability of timing. However, it should be noted that the protection scope of the GPS module 1 in the embodiment is not only the UT4B0, but also any GPS module having the same output mode as that described in the application.

[0018] The signal processing module 2 mainly completes the conversion and protocol analysis of network port signals, digital intermediate frequency DDC processing, signal demodulation, time stamp marking, signal capture, zero intermediate frequency receiver, signal direction calculation, signal scanning, correction algorithm of the time of a previous system and the generation of the time of a lower system. The main processor of the signal processing module 2 adopts a chip of the Zu9 series of Xilinx Company. The radio frequency processing chip in the signal processing module 2 adopts an ADRV9009 chip of ADI Company.

[0019] The radio frequency amplification module 3 is mainly composed of a radio frequency switch, a radio frequency filter, a low noise amplification chip and the like. Its main function is to complete the low noise amplification of the uplink received signal (i.e. Figure 2 The middle RFM signal, the signal transmitted by the radio frequency front end module 4). The first radio frequency switch is connected with the RX0 receiving channel and the RX receiving channel respectively. The RX0 receiving channel transmits the signal to the signal processing module 2 through the first radio frequency filter. The RX receiving channel transmits the signal to the signal processing module 2 through the second radio frequency filter and the first low noise amplification chip. The first radio frequency switch is a two-choice radio frequency switch. When the RX0 channel is selected, the pin for controlling the RX0 channel on the first radio frequency switch needs to be added with a high level. At this time, the RX channel must be unselected, that is, the level added to the pin for controlling the opening of the RX channel is a low level. Therefore, the function of the two-choice first radio frequency switch is realized. As shown in Figure 2 The radio frequency amplification module 3 is mainly composed of a radio frequency switch, a radio frequency filter, a low noise amplification chip and the like. Its main function is to complete the low noise amplification of the uplink received signal (i.e. Figure 2 The upper half part of the block diagram), the RX0 receiving channel and the RX receiving channel. Among them, the control module receives the control level signal from the baseband board (the signal processing module 2) to control the on-off of the RX0 receiving channel and the RX receiving channel in the first radio frequency switch. The control level signal generates the RX0 enable signal (controls the on-off of the RX0 channel, the high level is effective) through the triode and the MOS tube buffer, and generates the RX enable signal (controls the on-off of the receiving channel, the high level is effective) through the inverter to control the radio frequency switch, to select the routing and on-off of the signal.

[0020] The radio frequency front end module 4 in the embodiment is mainly composed of a multi-channel radio frequency switch, a radio frequency filter and a low noise amplification chip, and the like. The second radio frequency switch is connected with the 2-way frequency selection channel respectively. The frequency selection channel is composed of the multi-channel radio frequency switch, the radio frequency filter, the low noise amplification chip, the multi-channel radio frequency switch and the low noise amplification chip connected in sequence. The output end of the 2-way frequency selection channel is connected with the third radio frequency switch. The third radio frequency switch transmits the selected frequency to the radio frequency amplification module 3 through the third radio frequency filter and the second low noise amplification chip for filtering and amplification. The main function is to complete the filtering selection and low noise amplification of the uplink signal. The function block diagram is shown in Figure 3 After the radio frequency front end module 4 receives the signal transmitted by the circular polarized antenna 5, the appropriate frequency range is selected by controlling the second radio frequency switch to open and close different channels. The selected frequency is transmitted to the radio frequency amplification module 3 through filtering and amplification.

[0021] The application is used to realize the frequency selection and filtering of the signal. At the same time, the multi-stage processing system can form a cascaded system, and the time synchronization and frequency synchronization functions can be realized under the cascaded system.

[0022] As Figure 4As shown, the time source of the system is provided by the high-precision GPS module 1. The GPS module 1 receives satellite signals, generates corresponding time information, and inputs the time information into the system. The time source of the secondary system in the cascade system is the time sent by the serial port of the FPGA of the primary system, and at this time, the satellite antenna of the secondary system can not be installed.

[0023] The frequency input source of the cascade system mentioned in the embodiment is the 1PPS signal generated by the GPS module 1 in the primary system and the external synchronization signal (1PPS) in the secondary system. In the secondary system, the source of the external synchronization clock is the 1PPS signal generated by the clock generator AD9548 of the primary system, and the 1PPS signal generated by the clock generator AD9548 is used as the frequency synchronization signal of the entire cascade system.

[0024] The cascade system of the application realizes the concept of time synchronization algorithm and frequency synchronization of the system, so that the data transmission and sampling of the system are more accurate and stable. The specific implementation process is as follows:

[0025] Time synchronization:

[0026] As shown in Figure 4 : In the primary system, the time information obtained by the high-precision GPS module 1 is transmitted to the FPGA chip (Field Programmable Gate Array, Field Programmable Gate Array) of the primary system through the UART protocol, and is transmitted to the secondary system through the serial port of the FPGA chip. The FPGA chip of the secondary system performs time delay compensation algorithm, calculates the time delay in the transmission link, and then compensates the delay, thereby realizing the synchronization of the primary system and the secondary system in time. The algorithm process of time delay compensation is shown in Figure 5 :

[0027] (1) The signal processing module (2) of the secondary system sends a time synchronization request data packet REQ to the signal processing module (2) of the primary system, and adds a time stamp T1 on the frame header of the data frame of the data packet REQ;

[0028] (2) The signal processing module (2) of the primary system receives the synchronization request data packet REQ, and the time point of receiving the data packet is recorded as T2;

[0029] (3) The signal processing module (2) of the primary system sends a corresponding data packet RES, and adds a time stamp T3 on the frame header of the data frame of the response data packet RES;

[0030] (4) The signal processing module (2) of the secondary system receives the response data packet, and the time point of receiving the response data packet is recorded as T4;

[0031] (5) Calculate the delay time t of the linkoffset , t offset The calculation formula of t offset = (T2-T1+T3-T4) / 2

[0032] (6) Calculate t offset After that, the time received by the secondary system is added with the offset time t offset , that is, the correction of the time received by the secondary system is realized, and the time synchronization of the primary and secondary systems is realized.

[0033] Frequency synchronization:

[0034] The frequency synchronization scheme of the application avoids using a constant temperature clock as the source of the system clock, and selects to use the good stability of the second pulse as the frequency synchronization signal of the system. The GPS module 1 of the primary system generates a 1PPS second pulse, and after passing through the clock generator AD9548, it generates various clocks used in the system. At the same time, the clock generator AD9548 also locks the generation of the 1PPS second pulse signal. The 1PPS signal generated by the clock generator AD9548 is transmitted by the primary system to the external synchronization input of the secondary system, as the reference signal of the digital phase-locked loop of the clock generator AD9548, and then through the digital phase-locked loop to generate a high-precision system clock synchronized with the reference signal, thereby ensuring the synchronization of the frequency and phase of each node in the cascade system.

[0035] The signal processing platform system can work independently with a set of equipment, or work in the form of a cascade system. The time synchronization and frequency synchronization functions can be realized under the cascade system. The integration is high, and no additional DDS, DA and other related circuits are needed, which reduces the development cost of the system and the size of the design board. The constant temperature crystal oscillator is avoided as the source of the system clock, and only the constant temperature clock is selected as the reference clock of the clock generator AD9548, which does not need real-time adjustment of the frequency, so it is not affected by the frequency range adjustment of the constant temperature crystal oscillator, and the performance requirements of the crystal oscillator are reduced. The time synchronization and frequency synchronization of the signal processing platform are realized, so that the data collected by the system is more accurate, and the stability and reliability of the system are also improved, which has significant social and economic benefits.

Claims

1. A signal processing platform system implementing time synchronization and frequency synchronization, characterized by, The application relates to a multi-level time synchronization system, which comprises at least one processing system, the processing system comprising a GPS module (1), a signal processing module (2), a radio frequency amplification module (3), a radio frequency front-end module (4), a circular polarization antenna (5) and a power module (6), the GPS module (1) being connected with a signal input end 1 of the signal processing module (2) to transmit time information and a 1PPS signal, the circular polarization antenna (5) being connected with a signal input end 1 of the radio frequency front-end module (4) through an antenna feed interface, a signal output end 3 of the radio frequency front-end module (4) being connected with a signal input end 1 of the radio frequency amplification module (3), signal output ends 3 and 4 of the radio frequency amplification module (3) being connected with signal input ends 4 and 5 of the signal processing module (2), and signal output ends 2 and 3 of the signal processing module (2) being connected with a load through an Ethernet and being connected with a signal input end 1 of the circular polarization antenna (5) through an antenna feed interface to transmit signals; and the power module (6) is connected with power input ends 6 of the GPS module (1) and the signal processing module (2), power input ends 2 of the radio frequency amplification module (3) and the radio frequency front-end module (4) to supply power. The primary system and the secondary system connected with the signal processing module (2) realize time synchronization and frequency synchronization, the signal processing module (2) comprises a clock generator AD9548 and an FPGA chip, the GPS module (1) of the primary system transmits received time information to the FPGA chip of the primary system, the FPGA chip transmits the time information to the FPGA chip of the secondary system through a serial port, the FPGA chip of the secondary system performs time delay compensation algorithm, calculates time delay in a transmission link, and then compensates the delay to realize time synchronization of the primary system and the secondary system. The GPS module (1) of the primary system generates a 1PPS second pulse, the clock generator AD9548 generates various clocks used in the primary system and a 1PPS second pulse signal after the 1PPS second pulse, the 1PPS second pulse signal generated by the clock generator AD9548 is transmitted to the clock generator AD9548 of the secondary system to realize external synchronization input, and then a high-precision system clock synchronized with a reference signal is generated through a digital phase-locked loop to ensure synchronization of frequencies and phases of all nodes in a multi-level contact system.

2. The signal processing platform system for achieving time and frequency synchronization according to claim 1, wherein, The radio frequency amplification module (3) comprises a radio frequency switch, a radio frequency filter and a low-noise amplification chip, a first radio frequency switch is connected with an RX0 receiving channel and an RX receiving channel, the RX0 receiving channel transmits signals to the signal processing module (2) through a first radio frequency filter, and the RX receiving channel transmits signals to the signal processing module (2) through a second radio frequency filter and a first low-noise amplification chip.

3. The signal processing platform system for achieving time and frequency synchronization according to claim 1, wherein, The radio frequency front-end module (4) comprises a second radio frequency switch, a multi-channel radio frequency switch, a radio frequency filter and a low-noise amplification chip, the second radio frequency switch is connected with two frequency selection channels, output ends of the two frequency selection channels are connected with a third radio frequency switch, and the third radio frequency switch transmits selected frequencies to the radio frequency amplification module (3) through a third radio frequency filter and a second low-noise amplification chip.

4. The signal processing platform system implementing time and frequency synchronization of claim 1, wherein, The GPS module (1) is a UT4B0 module of Xinxing Tong.

5. The signal processing platform system implementing time and frequency synchronization of claim 1, wherein, The algorithm of the time delay compensation comprises the following steps: (1) the signal processing module (2) of the secondary system sends a time synchronization request data packet REQ to the signal processing module (2) of the primary system, and adds a time stamp T1 on the frame header of the data frame of the data packet REQ; (2) the signal processing module (2) of the primary system receives the synchronization request data packet REQ, and the time point of receiving the data packet is recorded as T2; (3) the signal processing module (2) of the primary system sends a response data packet RES, and adds a time stamp T3 on the frame header of the data frame of the response data packet RES; (4) the signal processing module (2) of the secondary system receives the response data packet, and the time point of receiving the response data packet is recorded as T4; (5) Calculate the delay time t of the link offset , t offset The calculation formula is t offset = (T2-T1+T3-T4) / 2; (6) Calculate t offset After that, the time received by the secondary system is added with the offset time t offset That is, the correction of the time received by the secondary system is realized, and the time synchronization of the primary and secondary systems is realized.

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