Context-based adaptive binary arithmetic codec and related methods

Abstract

The context-based adaptive binary arithmetic code (CABAC) decoder includes a binary code decoding circuit and a context update circuit. The bin decoding circuit supports decoding multiple bins within a single cycle. The multiple binary codes include a first binary code and a second binary code. The bin decoding circuit generates a bin value for the first bin based on a first set of multiple contexts, a first range, and a first offset, and generates a bin value for the second bin based on a second set of multiple contexts, a second range, and a second offset. The context update circuit updates the first set of multiple contexts in response to the bin value of the first bin to generate a first set of updated contexts, and updates the second set of multiple contexts in response to the bin value of the second bin to generate a second set of updated contexts.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 235,828, filed on August 23, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a video decoder design, and more specifically, to a context-based adaptive binary arithmetic code (CABAC) decoder and related decoding method capable of decoding multiple binary codes (hereinafter referred to as bins) in one cycle (stage). Background Technology

[0004] The Universal Video Coding (VVC) standard (also known as the H.266 standard) is the latest video coding standard. Compared to the previous High Efficiency Video Coding (HEVC) standard (also known as the H.265 standard), the main goal of the new VVC standard is to significantly improve compression capabilities. At the same time, VVC includes design features that make it suitable for a wide range of video applications. Like the HEVC standard, the VVC standard also employs Context Adaptive Binary Arithmetic Coding (CABAC) technology to entropy-encode the syntax elements of the coefficients in a transform block. In traditional CABAC decoder designs, hardware-based decoding architectures typically decode only a single bin per cycle. Therefore, an innovative VVC / H.266 CABAC decoder design with improved decoding performance is needed. Summary of the Invention

[0005] One object of the present invention is to provide a context-based adaptive binary arithmetic code (CABAC) decoder and a related decoding method capable of decoding multiple binary codes in one cycle (stage). For example, the CABAC decoder may be a multi-binary VVC / H.266 CABAC decoder.

[0006] According to a first aspect of the invention, an exemplary context-based adaptive binary arithmetic code (CABAC) decoder is disclosed. The exemplary CABAC decoder includes a binary code decoding circuit and a context update circuit. The binary code decoding circuit is configured to support decoding of a plurality of binary codes in at least one cycle, wherein the plurality of binary codes includes a first binary code and a second binary code. The binary code decoding circuit generates a binary code value of the first binary code based on a first set of multiple contexts, a first range, and a first offset, and generates a binary code value of the second binary code based on a second set of multiple contexts, a second range, and a second offset, wherein each of the second range and the second offset depends on decoding the first binary code. The context update circuit is configured to update the first set of multiple contexts in response to the binary code value of the first binary code to generate a first set of multiple updated contexts; and is also arranged to update the second set of multiple contexts in response to the binary code value of the second binary code to generate a second set of multiple updated contexts.

[0007] According to a second aspect of the present invention, an exemplary context-based adaptive binary arithmetic code (CABAC) decoding method is disclosed. The exemplary CABAC decoding method includes: decoding a plurality of binary codes by a binary code decoding circuit in one cycle, wherein the plurality of binary codes includes a first binary code and a second binary code, and a binary code value of the first binary code is decoded according to a first set of multiple contexts, a first range, and a first offset; and a binary code value of the second binary code is decoded according to a second set of multiple contexts, a second range, and a second offset, wherein each of the second range and the second offset depends on the decoding of the first binary code; updating the first set of multiple contexts in response to the binary code value of the first binary code to generate a first set of multiple updated contexts; and updating the second set of multiple contexts in response to the binary code value of the second binary code to generate a second set of multiple updated contexts.

[0008] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating a CABAC decoder according to an embodiment of the present invention.

[0010] Figure 2 This means that in Figure 1 The flowchart shown illustrates the VVC / H.266CABAC decoding process performed at the CABAC decoder.

[0011] Figure 3 This means that in Figure 1The flowchart shown is a renormalization process performed at the CABAC decoder.

[0012] Figure 4 This is a schematic diagram of a first context update circuit design according to an embodiment of the present invention.

[0013] Figure 5 This is a diagram illustrating the context loading operation performed under the condition sel_2nd=1 according to an embodiment of the present invention.

[0014] Figure 6 This is a diagram illustrating the context update and write-back operations performed under the condition sel_2nd=1 according to an embodiment of the present invention.

[0015] Figure 7 This is a schematic diagram illustrating the design of a first binary code decoding circuit according to an embodiment of the present invention.

[0016] Figure 8 The diagram is in Figure 7 A diagram showing an example of VVC / H.266 coefficient decoding performed at the CABAC decoder.

[0017] Figure 9 This means that in Figure 8 The diagram shows the different situations encountered during dual binary VVC / H.266 CABAC decoding performed at the CABAC decoder.

[0018] Figure 10 This is a schematic diagram of the second context update circuit design according to an embodiment of the present invention.

[0019] Figure 11 This is a schematic diagram illustrating another context loading operation performed under the condition sel_2nd=1 according to an embodiment of the present invention.

[0020] Figure 12 This is a schematic diagram illustrating another context update and write-back operation performed under the condition sel_2nd=1 according to an embodiment of the present invention.

[0021] Figure 13 This is a diagram illustrating the design of a second binary code decoding circuit according to an embodiment of the present invention.

[0022] Figure 14 This is a flowchart illustrating a CABAC decoding method according to an embodiment of the present invention. Detailed Implementation

[0023] Certain terms used in the following description and claims refer to specific components. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to a component. This document is not intended to distinguish between components with different names but different functions. In the following description and claims, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as meaning “including, but not limited to…”. Furthermore, the term “coupled” is intended to indicate an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection can be through a direct electrical connection or through an indirect electrical connection via other devices and connections.

[0024] Attached Figure Description Figure 1 This is a diagram illustrating a CABAC decoder according to an embodiment of the present invention. The CABAC decoder 100 may be part of an entropy decoder in a VVC / H.266 decoder. However, this is for illustrative purposes only and is not intended to limit the invention. In practice, any CABAC decoder using the CABAC decoding performance optimization techniques proposed in this invention falls within the scope of this invention. The CABAC decoder 100 may include a barrel shifter 102, a bin decoding circuit 104, a context update circuit 106, a context pool storage 108, a debinarization circuit 110, a local buffer 112, a range memory 114, and an offset memory 116. In this embodiment, the bin decoding circuit 104 supports decoding of multiple bins in one stage and decoding of only a single bin in one stage. For example, the internal control signal en_2bin is set based on whether decoding two bins in one stage is enabled. When decoding two bins in the current stage, the control signal en_2bin is set to 1 (i.e., en_2bin = 1). In another case where only a single bin is decoded in the current cycle (phase), the control signal en_2bin is set to 0 (i.e., en_2bin = 0).

[0025] A barrel shifter 102 is configured to receive bits of the bit stream BS_IN and provide the bits to be decoded to the bin decoding circuit 104. A context pool memory 108 is configured to store the contexts for different syntax elements. The context required for decoding each bin is loaded from the context pool memory 108 and stored in a local buffer 112, and then provided from the local buffer 112 to the bin decoding circuit 104. In this embodiment, decoding of each bin requires a set of multiple contexts (P0, P1), where the probability actually used for CABAC decoding comes from a linear combination of P0 and P1. A range memory 114 is configured to store and provide the range required to decode a bin. An offset memory 116 is configured to store and provide the offset required to decode a binary code.

[0026] Regarding the decoding of multiple binary codes (e.g., a first binary code and a second binary code) in a cycle (stage), the binary code decoding circuit 104 generates a binary code value for a first binary code based on a first set of multiple contexts obtained from a context pool storage 108, a first range obtained from a range memory 114, and a first offset obtained from an offset memory 116; and generates a bin value for a second bin based on a second set of multiple contexts, a second range, and a second offset, wherein each of the second range and the second offset depends on the decoding of the first bin. A debinding circuit 110 is arranged to apply debinding to the bin values ​​of the first bin and the second bin decoded by the bin decoding circuit 104, and generates and outputs the syntax value output SE_OUT. Furthermore, a context update circuit 106 is configured to update the first set of multiple contexts in response to the bin value of the first bin to generate a first set of multiple updated contexts, and is also configured to generate a second set of multiple updated contexts in response to the bin value of the second bin. The context update circuit 106 can write both the first group of multiple update contexts and the second group of multiple update contexts back to the context pool memory 108, or it can write the second group of multiple update contexts back to the context pool memory 108.

[0027] Regarding decoding only a single bin (e.g., the first bin) in a single cycle (phase), bin decoding circuit 104 generates a bin value for the first bin based on a first set of multiple contexts obtained from context pool memory 108, a first range obtained from range memory 114, and a first offset obtained from offset memory 116. Debinarization circuit 110 is arranged to apply debinarization to the bin value of the first bin decoded by bin decoding circuit 104 and generate and output the syntax value output SE_OUT. Furthermore, context update circuit 106 is arranged to update the first set of multiple contexts in response to the bin value of the first bin to generate a first set of multiple updated contexts and write the first set of multiple updated contexts back to context pool memory 108.

[0028] For multi-bit CABAC decoding in a cycle (stage), a second set of multiple contexts for decoding the second bin can be obtained from the context update circuit 106 or from the context pool storage 108 via the local buffer 112. In this embodiment, the internal control signal sel_2nd is set based on whether the decoding of the first bin and the decoding of the second bin select the same context source. For example, if the decoding of the first bin and the decoding of the second bin use the same context index, the control signal sel_2nd is set to 0 (i.e., sel_2nd = 0); if the decoding of the first bin and the decoding of the second bin use different context indices, the control signal sel_2nd is set to 1 (i.e., sel_2nd = 1). Both the bin decoding circuit 104 and the context update circuit 106 are controlled by the control signal sel_2nd.

[0029] To better understand the technical features of this invention, it is assumed below that the CABAC decoder 100 is a VVC / H.266 CABAC decoder. Therefore, the CABAC decoder 100 is capable of performing actions such as... Figure 2The VVC / H.266CABAC decoding process is shown. Steps 202, 204, 206, and 208 pertain to the binary decoding process. A set of two contexts (pStateIdx0, pStateIdx1) is used to calculate the actual probability used to decode the current bin, i.e., pState = pStateIdx1 + 16 * pStateIdx0. The comparison of the offset and range determines whether the decoded bin value for the current bin is set by the MPS (Most Probability Symbol) value or the LPS (Low Probability Symbol) value. When the decoded bin value for the current bin is set by the LPS value, the range and offset are further updated. After decoding the bin value for the current bin, step 210 is executed to handle the context update process (or state transition process). The two contexts (pStateIdx0, pStateIdx1) can be updated by using different fit rates (shift0, shift1). Figure 3 As shown, step 212 pertains to the renormalization process. Step 302 checks if the current range is less than the set threshold of 256. If the current range is found to be less than 256, the range and offset are updated in step 304. If the current range is found to be equal to or greater than 256, renormalization is not applied to the range and offset. ctx_update

[0030] Figure 4 This is a schematic diagram of a first context update circuit design according to an embodiment of the present invention. Figure 1 The context update circuit 106 shown can be generated by Figure 4 The context update circuit 400 shown is used to implement this. The context update circuit 400 employs a 2-bin cascaded design for state transition updates (context updates). For example... Figure 4As shown, the context update circuit 400 includes a context update core circuit 402 and multiple multiplexers 404 and 406. Regarding the decoding of multiple bins (e.g., the first bin and the second bin) within a cycle (stage), a set of multiple contexts (P0_1st, P1_1st) is used for decoding the first bin, and a set of multiple contexts (P0_2nd_in, P1_2nd_in) is used for decoding the second bin. For example, in the VVC / H.266CABAC decoding process of the first bin, a set of multiple contexts (P0_1st, P1_1st) is involved when calculating pState = pStateIdx1 + 16 * pStateIdx0 in step 202. Similarly, in the H.266CABAC decoding process of the VVC / second bin, a set of multiple contexts (P0_2nd_in, P1_2nd_in) is involved when calculating pState = pStateIdx1 + 16 * pStateIdx0 in step 202. In response to the bin value bin_val_1st of the first bin, the bin decoding circuit (e.g.) Figure 1 The bin decoding circuit 104 shown has a context update core circuit 402 that generates an updated set of contexts (P0_1st_o, P1_1st_o) based on a set of multiple contexts (P0_1st, P1_1st) and multiple fitness rates (rate0_1st, rate1_1st). For example, during the VVC / H.266CABAC decoding process of the first bin, a set of multiple contexts (P0_1st, P1_1st) is updated in step 210.

[0031] Multiplexer 404 has two input ports P11 and P12 and one output port P13. Input port P11 is configured to receive a set of multiple updated contexts (P0_1st_o, P1_1st_o) generated from context update core circuit 402. Input port P12 is configured to receive a set of multiple contexts (P0_2nd, P1_2nd) loaded from context pool storage 108. The control signal sel_2nd is used as the control signal for multiplexer 404.

[0032] Multiplexer 406 has two input ports P21 and P22 and one output port P23. Input port P21 is used to receive the set of adaptation rates (rate0_1st, rate1_1st). Input port P22 is configured to receive a set of multiple adaptation rates (rate0_2nd, rate1_2nd). The control signal sel_2nd is used as the control signal for multiplexer 406.

[0033] Consider the case where the bin decoding circuit 104 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin = 1). When the decoding of the first bin and the decoding of the second bin select the same context source (sel_2nd = 0), the multiplexer 404 couples the output port P13 to the input port P11, and the multiplexer 406 couples the output port P23 to the input port P21, such that the multiple context sets (P0_2nd_in, P1_2nd_in) used by the second bin decoding are set by a set of multiple update contexts (P0_1st_o, P1_1st_o), and the multiple adaptive rate sets (rate0_2nd_in, rate1_2nd_in) used by the second bin decoding are set by a set of multiple adaptive rates (rate0_1st, rate1_1st).

[0034] When the decoding of the first bin and the decoding of the second bin select different context sources (sel_2nd=1), the multiplexer 404 couples the output port P13 to the input port P12, and the multiplexer 406 couples the output port P23 to the input port P22, so that the multiple context sets (P0_2nd_in, P1_2nd_in) used for the decoding of the second bin are set by multiple context sets (P0_2nd, P1_2nd), and the multiple adaptive rate sets (rate0_2nd_in, rate1_2nd_in) used for the decoding of the second bin are set by a set of multiple adaptive rates (rate0_2nd, rate1_2nd).

[0035] In response to the bin value bin_val_2nd of the second bin decoded by bin decoding circuit 104, context update core circuit 402 generates a set of multiple update contexts (P0_2nd_o, P1_2nd_o) based on a set of contexts (P0_2nd_in, P1_2nd_in) and a set of multiple adaptive rates (rate0_2nd_in, rate1_2nd_in). For example, during the VVC / H.266CABAC decoding process of the second bin, a set of multiple contexts (P0_2nd_in, P1_2nd_in) is updated in step 210.

[0036] A set of multiple contexts (P0_1st, P1_1st) is set by the stored contexts loaded from the context pool memory 108. When the decoding of the first bin and the decoding of the second bin select the same context source (sel_2nd = 0), the context update core circuit 402 writes the set of multiple updated contexts (P0_2nd_o, P1_2nd_o) back to the context pool memory 108, which is used to update / overwrite the contexts stored in the context pool memory 108 with the set of multiple updated contexts (P0_2nd_o, P1_2nd_o).

[0037] When the decoding of the first bin and the decoding of the second bin select different context sources (sel_2nd=1), a set of multiple contexts (P0_1st, P1_1st) is set by the first stored context loaded from the context pool memory 108, and a set of multiple contexts (P0_2nd, P1_2nd) is set by the second stored context loaded from the context pool memory 108. Figure 5 This is a schematic diagram illustrating a context loading operation performed under the condition sel_2nd = 1 according to an embodiment of the present invention. The context pool memory 108 may include P0 memory and P1 memory. The context index ctx_inc associated with the decoding of the first bin is different from the context index ctx_inc associated with the decoding of the second bin. Figure 5 As shown, the context set (P0_1st, P1_1st) with index ctx_inc=1 is loaded from the context pool storage 108 and stored in the local buffer 112, and the multi-context set (P0_2nd, P1_2nd) with index ctx_inc=4 is loaded from the context pool storage 108 and stored in the local buffer 112.

[0038] Since the decoding of the first binary code and the decoding of the second binary code select different context sources (sel_2nd=1), the context update core circuit 402 writes a set of multiple updated contexts (P0_1st_o, P1_1st_o) back to the context pool storage 108 to update / overwrite the first stored context in the context pool storage 108 with the set of multiple updated contexts (P0_1st_o, P1_1st_o), and further writes a set of multiple updated contexts (P0_2nd_o, P1_2nd_o) back to the context pool storage 108 to update / overwrite the second stored context in the context pool storage 108 with the set of multiple updated contexts (P0_2nd_o, P1_2nd_o). Figure 6This is a schematic diagram illustrating the context update and write-back operations performed under the condition sel_2nd = 1 according to an embodiment of the present invention. Multiple context sets (P0_1st, P1_1st) indexed by ctx_inc = 1 in the context pool memory 108 are updated / overwritten by a set of multiple update contexts (P0_1st_o, P1_1st_o). Furthermore, multiple context sets (P0_2nd, P1_2nd) indexed by ctx_inc = 4 in the context pool memory 108 are updated / overwritten by a set of multiple update contexts (P0_2nd_o, P1_2nd_o).

[0039] When the bin decoding circuit 104 is controlled to operate in a one-bin-one-cycle CABAC decoding mode (en_2bin = 0), the multiple context sets (P0_1st, P1_1st) used to decode only a single bin in one cycle (stage) are set by the stored contexts loaded from the context pool memory 108. Therefore, the context update core circuit 402 writes the multiple updated context sets (P0_1st_o, P1_1st_o) back to the context pool memory 108 for updating / overwriting the stored contexts in the context pool memory 108 by the multiple updated context sets (P0_1st_o, P1_1st_o).

[0040] The context update core circuit 402 is shown as having two processing circuits (labeled "ctx_update") 412 and 414, also referred to as the context update circuit. In one exemplary design, processing circuits 412 and 414 can be separate processing circuits, wherein processing circuit 412 is dedicated to processing updates of multiple contexts (P0_1st, P1_1st) used for decoding the first bin, and processing circuit 414 is dedicated to processing updates of multiple contexts (P0_2nd_in, P1_2nd_in) used for decoding the second bin. In another exemplary design, processing circuits 412 and 414 can be the same processing circuit (i.e., shared processing circuit), which is used to process context updates of multiple context sets (P0_1st, P1_1st) used for decoding the first bin, and is reused to process context updates of multiple context sets (P0_2nd_in, P1_2nd_in) used for decoding the second bin. Briefly, the present invention does not limit the physical implementation of the context update core circuit 402.

[0041] Figure 7 This is a schematic diagram illustrating the design of the first bin decoding circuit according to an embodiment of the present invention. Figure 1 The bin decoding circuit 104 shown can be derived from... Figure 7The binary code (bin) decoding circuit 700 shown is used to implement this. The bin decoding circuit 700 employs a binary cascade design to decode multiple bins within one cycle (stage). For example... Figure 7 As shown, the binary code decoding circuit 700 includes a bin decode core circuit 702 and a multiplexer 704. Regarding the decoding of multiple bins (e.g., the first bin and the second bin) within a cycle (stage), the bin decode core circuit 702 receives a first portion of the bitstream input bs_in_1st and a second portion of the bitstream input bs_in_2nd output from the barrel shifter 102. The bin decode core circuit 702 decodes and generates the bin value bin_val_1st of the first bin based on a set, range, and an offset of multiple contexts (P0_1st, P1_1st). For example, during the VVC / H.266CABAC decoding of the first bin, the bin value bin_val_1st of the first bin is generated in step 206 or step 208. Furthermore, the bin decode core circuit 702 provides a range range_1st_o and an offset offset_1st_o to be used for decoding the second bin within the same cycle (stage). The range output and offset output after decoding the first bin can be the same as or different from the range input and offset input before decoding the first bin. For example, the range_1st_o and offset_1st_o can be obtained by updating the range_1st and offset_1st in step 206 and / or step 212.

[0042] The bin decoding core circuit 702 decodes and generates the bin value bin_val_2nd of the second bin based on a set of multiple contexts (P0_2nd_in, P1_2nd_in), the range range_1st_o, and the offset offset_1st_o. For example, during the VVC / H.266CABAC decoding process of the second bin, the bin value bin_val_2nd of the second bin is generated in step 206 or step 208. Furthermore, the bin decoding core circuit 702 provides the range range_2nd_o and the offset offset_2nd_o. The range output and offset output after the second bin is decoded can be the same as or different from the range input and offset input before the second bin is decoded. For example, the range range_2nd_o and the offset offset_2nd_o can be obtained by updating the range range_1st_o and the offset offset_1st_o in step 206 and / or step 212.

[0043] The multiplexer 704 has two input ports P31 and P32 and one output port P33. The operation of the multiplexer 704 is similar to... Figure 4 The operation of the multiplexer 404 is shown. Input port P31 is arranged to receive data from a context update circuit (e.g., ...). Figure 4 The context update circuit 400 shown generates a set of multiple update contexts (P0_1st_o, P1_1st_o). Input port P32 is used to receive the context set (P0_2nd, P1_2nd) loaded from the context pool memory 108. The control signal sel_2nd is used as the control signal for the multiplexer 704.

[0044] Consider the case where the bin decoding circuit 700 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin = 1). When the decoding of the first bin and the decoding of the second bin select the same context source (sel_2nd = 0), the multiplexer 704 couples the output port P33 to the input port P31, such that multiple updated context sets (P0_1st_o, P1_1st_o) set the multiple context sets (P0_2nd_in, P1_2nd_in) used for the decoding of the second bin. When the decoding of the first bin and the decoding of the second bin select different context sources (sel_2nd = 1), the multiplexer 704 couples the output port P33 to the input port P32, such that the decoding of the second bin is set by a set of multiple contexts (P0_2nd, P1_2nd).

[0045] The bin decoding circuit 700 can also support decoding only a single bin in one cycle (stage). When the bin decoding circuit 700 is controlled to operate in a single-bin-single-cycle CABAC decoding mode (en_2bin = 0), the bin decoding core circuit 702 receives the first part of the bit stream input bs_in_1st from the barrel shifter 102, and decodes and generates the bin value bin_val_1st of the first bin based on the set, range, and offset of multiple contexts (P0_1st, P1_1st), where the range range_1st_o and the offset offset_1st_o are generated after the first bin is decoded.

[0046] The bin decoding core circuit 702 is shown having two processing circuits (labeled "bin_decode") 712 and 714. In one exemplary design, processing circuits 712 and 714 can be separate processing circuits, where processing circuit 712 is dedicated to processing the decoding of the first bin to produce the bin value bin_val_1st, while processing circuit 714 is dedicated to processing the decoding of the second bin to produce the bin value bin_val_2nd. In another exemplary design, processing circuits 712 and 714 can be the same processing circuit (i.e., shared processing circuit) for processing the decoding of the first bin used to generate the bin value bin_val_1st, and reused for processing the decoding of the second bin to generate the bin value bin_val_2nd. In short, the present invention does not limit the physical implementation of the bin decoding core circuit 702.

[0047] After decoding the first bin, the bin decoding core circuit 702 outputs an indicator value shift_bits_no_1st, indicating how many bits were consumed during the CABAC decoding of the first bin, and another indicator value shift_bits_no_2nd, indicating how many bits were consumed during the CABAC decoding of the second bin. The CABAC decoder 100 may also include a multiplexer (MUX) 722 controlled by the control signal en_2bin. When the bin decoding circuit 700 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin = 1), the indicator values ​​shift_bits_no_1st and shift_bits_no_2nd are added to set the indicator value shift_bits_no, which indicates how many bits were consumed in the current cycle (phase). When the bin decoding circuit 700 is controlled to operate in a one-bin-one-cycle CABAC decoding mode (en_2bin = 0), the indicator value shift_bits_no_1st is output as the indicator value shift_bits_no. For each cycle (stage) of CABAC decoding, the barrel shifter 102 operates in response to the indicator value shift_bits_no.

[0048] The CABAC decoder 100 may also include a multiplexer (MUX) 724 controlled by the control signal en_2bin. When the bin decoding circuit 700 is controlled in a two-bin-one-cycle CABAC decoding mode (en_2bin = 1), the range output and offset output (i.e., range_2nd_o and offset_2nd_o) after the second bin is decoded are selected and output by the multiplexer 724 to update the current range recorded in the range memory 114 and the current offset recorded in the offset memory 116, respectively. When the bin decoding circuit 700 is controlled in a one-bin-one-cycle CABAC decoding mode (en_2bin = 0), the range output and offset output (i.e., range_1st_o and offset_1st_o) after the first bin is decoded are selected and output by the multiplexer 724 to update the current range recorded in the range memory 114 and the current offset recorded in the offset memory 116, respectively.

[0049] The CABAC decoder 100 may also include a multiplexer (MUX) 726 controlled by a context index ctx_inc. In this embodiment, the local buffer 112 may be configured to have at least four local buffer units. When the bin decoding circuit 700 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin = 1) and the decoding of the first bin and the decoding of the second bin select the same context source (sel_2nd = 0), the multiplexer 726 controlled by the context index ctx_inc may load only one set of multiple contexts (P0_1st, P1_1st) from the context pool storage 108 into two local buffer units of the local buffer 112. When the bin decoding circuit 700 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin=1) and when the decoding of the first bin and the second bin select different context sources (sel_2nd=1), the multiplexer 726 controlled by the context index ctx_inc can load both the context sets (P0_1st, P1_1st) and the context sets (P0_2nd, P1_2nd) from the context pool memory 108 into the four local buffer units of the local buffer 112. When the bin decoding circuit 700 is controlled to operate in a one-bin-one-cycle CABAC decoding mode (en_2bin=0), the multiplexer 726 controlled by the context index ctx_inc can load only the multiple context sets (P0_1st, P1_1st) from the context pool memory 108 into the two local buffer units of the local buffer 112.

[0050] In some multi-bin CABAC decoding scenarios, the context selection for the second bin may depend on the bin value of the first bin. This may require preloading two sets of contexts (P0_2nd_c0, P1_2nd_c0) and (P0_2nd_c1, P1_2nd_c1) before decoding the second bin. Please refer to Figures 8 and 9 for further explanation. Figure 8 This is a schematic diagram illustrating an example of VVC / H.266 coefficient decoding. Figure 9This diagram illustrates the different scenarios encountered during dual-binary VVC / H.266 CABAC decoding. The decoding order can be the reverse diagonal scan order specified in the VVC / H.266 standard. The syntax element `sig_coeff_flag` (marked as "SIG") for coefficient position (scan position) indicates whether the absolute value of the coefficient level is greater than 0. The syntax element `abs_level_gt1_flag` (marked as "GT1") for coefficient position (scan position) indicates whether the absolute value of the coefficient level is greater than 1. It is important to note that the syntax element `abs_level_gt1_flag` is only decoded when the absolute value of the coefficient level indicated by the syntax element `sig_coeff_flag` is not equal to 0. Therefore, regarding decoding two bins within a cycle (phase), the first bin can be decoded to obtain the syntax value of the syntax element sig_coeff_flag at the current coefficient position (current scan position), and the second bin can be decoded to obtain the value of the syntax element sig_coeff_flag at the next coefficient position (next scan position), i.e., case 0, as shown. Figure 9 The subgraph (A) shows scenario 0. Specifically, when the bin value of the first bin is equal to 0 (i.e., SIG = 0), a SIG-SIG 2-bin decoding operation is performed in one cycle (phase). Alternatively, regarding decoding two bins in one cycle (phase), the first bin can be decoded to obtain the syntax value of the syntax element sig_coeff_flag at the current coefficient position (current scan position), and the second bin can be decoded to obtain the syntax value of the syntax element abs_level_gt1_flag at the same coefficient position (scan position), i.e. Figure 9 Subgraph (B) shows scenario 1. Specifically, when the bin value of the first bin is equal to 1 (i.e., SIG = 1), the SIG-GT1 2-bin decoding operation is performed in one cycle (stage). To handle the above-mentioned situation where the context selection of the second bin depends on the bin value of the first bin, embodiments of the present invention can employ a CABAC decoder design that provides two paths associated with the decoding of the second bin. Further explanation follows with reference to the accompanying drawings.

[0051] Figure 10 This is a schematic diagram of the second context update circuit design according to an embodiment of the present invention. Figure 1 The context update circuit 106 shown can be generated by Figure 10 The context update circuit 1000 shown is used to implement this. The main difference between context update circuits 400 and 1000 is that context update circuit 1000 also includes two multiplexers 1002 and 1004.

[0052] Multiplexer 1002 has two input ports P41 and P42 and one output port P43. Input port P41 is configured to receive multiple contexts (P0_2nd_c0, P1_2nd_c0) loaded from context pool memory 108. Input port P42 is configured to receive multiple contexts (P0_2nd_c1, P1_2nd_c1) loaded from context pool memory 108. The control signals of multiplexer 1002 are set according to the bin value bin_val_1st of the first bin.

[0053] Multiplexer 1004 has two input ports P51 and P52 and one output port P53. Input port P51 is configured to receive a set of adaptation rates (rate0_2nd_c0, rate1_2nd_c0). Input port P52 is configured to receive a set of multiple adaptation rates (rate0_2nd_c1, rate1_2nd_c1). The control signals for multiplexer 1004 are set based on the bin value bin_val_1st of the first bin.

[0054] Considering the case where the bin decoding circuit 104 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin=1), the decoding of the first bin and the decoding of the second bin select different context sources (sel_2nd=1), and the bin value bin_val_1st of the first bin is equal to 0 (bin_val_1st=0). Multiplexer 1002 selects a set of multiple contexts (P0_2nd_c0, P1_2nd_c0) and outputs them to input port P12 of multiplexer 404. Multiplexer 404 selects and outputs a set of multiple contexts (P0_2nd_c0, P1_2nd_c0) as a set of multiple contexts (P0_2nd_c0, P1_2nd_c0). The multiplexer 1004 selects and outputs a set of multiple adaptive rates (rate0_2nd_c0, rate1_2nd_c0) to port P22 of the input multiplexer 406. The multiplexer 406 selects and outputs a set of multiple adaptive rates (rate0_2nd_c0, rate1_2nd_c0) as a set of multiple adaptive rates (rate0_2nd_in, rate1_2nd_in). The context update core circuit 402 generates multiple update contexts (P0_2nd_o, P1_2nd_o) based on the context set (P0_2nd_c0, P1_2nd_c0) and the adaptive rate set (rate0_2nd_c0, rate1_2nd_c0).

[0055] Consider another scenario where the bin decoding circuit 104 is controlled to operate in a two-bin-one-cycle CABAC decoding mode (en_2bin = 1). The decoding of the first bin and the second bin select different context sources (sel_2nd = 1), and the bin value bin_val_1st of the first bin is equal to 1 (bin_val_1st = 1). Multiplexer 1002 selects a set of multiple contexts (P0_2nd_c1, P1_2nd_c1) and outputs them to the input port P12 of multiplexer 404. Multiplexer 404 selects and outputs multiple contexts (P0_2nd_c1, P1_2nd_c1) as multiple contexts (P0_2nd_in). Multiplexer 1004 selects and outputs an adaptive rate set (rate0_2nd_c1, rate1_2nd_c1) to port P22 of input multiplexer 406. Multiplexer 406 selects and outputs the adaptive rate set (rate0_2nd_c1, rate1_2nd_c1) as a set of multiple adaptive rates (rate0_2nd_in, rate1_2nd_in). The context update core circuit 402 generates a set of multiple update contexts (P0_2nd_o, P1_2nd_o) based on the multiple context sets (P0_2nd_c1, P1_2nd_c1) and the multiple adaptive rate sets (rate0_2nd_c1, rate1_2nd_c1).

[0056] A set of multiple contexts (P0_1st, P1_1st) is set by a first stored context loaded from context pool memory 108. A set of multiple contexts (P0_2nd_c0, P1_2nd_c0) is set by a second stored context loaded from context pool memory 108, and a set of multiple contexts (P0_2nd_c1, P1_2nd_c1) is set by a third stored context loaded from context pool memory 108. Figure 11 This is a schematic diagram illustrating another context loading operation performed under the condition sel_2nd = 1 according to an embodiment of the present invention. The context pool memory 108 may include P0 memory and P1 memory. The context index ctx_inc associated with the decoding of the first bin is different from the context index ctx_inc associated with the decoding of the second bin. (Refer to...) Figure 11A set of multiple contexts (P0_1st, P1_1st) indexed by ctx_inc=1 is loaded from context pool memory 108 and stored in local buffer 112. A set of multiple contexts (P0_2nd_c0, P1_2nd_c0) indexed by ctx_inc=4 is loaded from context pool memory 108 and stored in local buffer 112. A set of multiple contexts (P0_2nd_c1, P1_2nd_c1) indexed by ctx_inc=5 is loaded from context pool memory 108 and stored in local buffer 112.

[0057] Figure 12 This is a schematic diagram illustrating another context update and write-back operation performed under the condition sel_2nd=1 according to an embodiment of the present invention. Since the decoding of the first bin and the decoding of the second bin selected different context sources (sel_2nd=1), the context update core circuit 402 writes a set of multiple updated contexts (P0_1st_o, P1_1st_o) back to the context pool storage 108 for updating / overwriting the first stored context in the context pool storage 108 by multiple updated contexts (P0_1st_o, P1_1st_o). If val_bin_1st equals 0, multiple updated contexts (P0_2nd_o, P1_2nd_o) are written back to the context pool storage 108 for updating / overwriting the second stored context. If val_bin_1st equals 1, multiple updated contexts (P0_2nd_o, P1_2nd_o) are written back to the context pool storage 108 for updating / overwriting the third context stored in the context pool storage 108. Specifically, a set of multiple contexts (P0_1st, P1_1st) indexed by ctx_inc = 1 in the context pool memory 108 is replaced with a set of multiple update contexts (P0_1st_o, P1_1st_o). Furthermore, if val_bin_1st equals 0, a set of multiple contexts (P0_2nd_c0, P1_2nd_c0) indexed by ctx_inc = 4 in the context pool memory 108 is replaced with a set of multiple update contexts (P0_2nd_o, P1_2nd_o), and if val_bin_1st equals 1, a context (P0_2nd_c1, P1_2nd_c1) indexed by ctx_inc = 5 in the context pool memory 108 is replaced with multiple update contexts (P0_2nd_o, P1_2nd_o).

[0058] Figure 13 This is a diagram illustrating the design of the second bin decoding circuit according to an embodiment of the present invention. Figure 1The bin decoding circuit 104 shown can be derived from... Figure 13 The bin decoding circuit 1300 shown is used to implement this. Figure 7 The embodiment can be modified to replace the bin decoding circuit 700 with the bin decoding circuit 1300. Figure 7 Only the circuit components relevant to the alternative bin decoding circuit design are shown. Like bin decoding circuit 700, bin decoding circuit 1300 is capable of decoding multiple binary data in one cycle (stage). Figure 13 As shown, the bin decoding circuit 1300 includes a bin decoding circuit (or bin decoding core circuit) 1302 and multiple multiplexers 1304, 1306, 1308, 1309, and 1310. The main difference between bin decoding circuits 1300 and 1300 is that bin decoding circuit 1300 includes an additional decoding path for a second bin. The bin decoding core circuit 1302 receives data from a barrel shifter (e.g., ...). Figure 7 The first part of the bitstream input (bs_in_1st) and the second part of the bitstream input (bs_in_2nd) are output by the barrel shifter 102 shown. The bin decoding core circuit 1302 decodes and generates the bin value bin_val_1st of the first bin based on multiple contexts (P0_1st, P1_1st), range, and offset. For example, during the VVC / H.266CABAC decoding of the first bin, the bin value bin_val_1st of the first bin is generated in step 206 or step 208. Furthermore, the bin decoding core circuit 1302 provides the range_1st_o and offset_1st_o to be used for decoding the second bin in the same cycle (stage). The range output and offset output after decoding the first bin can be the same as or different from the range input and offset input before decoding the first bin. For example, the range_1st_o and offset_1st_o can be obtained by updating the range_1st and offset_1st in step 206 and / or step 212.

[0059] The bin decoding core circuit 1302 decodes and generates a bin value bin_val_2nd_c0 for the second bin based on a set of multiple contexts (P0_2nd_in, P1_2nd_in), a range_1st_o, and an offset_1st_o. For example, during the VVC / H.266CABAC decoding process of the second bin, the bin value bin_val_2nd_c0 for the second bin is generated in step 206 or step 208. Furthermore, the bin decoding core circuit 1302 provides the range_2nd_c0 and the offset_2nd_c0. For example, the range_2nd_c0 and the offset_2nd_c0 can be the same as the range_1st_o and the offset_1st_o, respectively, or they can be obtained by updating the range_1st_o and the offset_1st_o in step 206 and / or step 212.

[0060] The bin decoding core circuit 1302 further decodes and generates another bin value bin_val_2nd_c1 for the second bin based on a set of multiple contexts (P0_2nd_in', P1_2nd_in'), range_1st_o, and offset_1st_o. For example, during the VVC / H.266CABAC decoding process of the second bin, the bin value bin_val_2nd_c1 of the second bin is generated in step 206 or step 208. Furthermore, the bin decoding core circuit 1302 provides the range_2nd_c1 and the offset_2nd_c1. For example, the range_2nd_c1 and the offset_2nd_c1 can be the same as the range_1st_o and the offset_1st_o, respectively, or they can be obtained by updating the range_1st_o and the offset_1st_o in step 206 and / or step 212.

[0061] The multiplexer 1304 has two input ports P61 and P62 and one output port P63. Input port P61 is configured to receive data from a context update circuit (e.g., ...). Figure 4 The context update circuit 400 shown generates multiple update contexts (P0_1st_o, P1_1st_o). Input port P62 is used to receive the context set (P0_2nd_c0, P1_2nd_c0) loaded from the context pool memory 108. The control signal sel_2nd is used as the control signal for the multiplexer 1304.

[0062] The multiplexer 1306 has two input ports P71 and P72 and one output port P73. Input port P71 is configured to receive data from a context update circuit (e.g., ...). Figure 4 The context update circuit 400 shown generates a set of multiple updated contexts (P0_1st_o, P1_1st_o). Input port P72 is used to receive multiple contexts (P0_2nd_c1, P1_2nd_c1) loaded from the context pool memory 108. The control signal sel_2nd is used as the control signal for the multiplexer 1306.

[0063] Consider the case where the bin decoding circuit 1300 is controlled to operate in a dual-bin single-cycle CABAC decoding mode (en_2bin = 1), and the decoding of the first bin and the second bin select different context sources (sel_2nd = 1). Multiplexer 1304 couples output port P63 to input port P62, such that a set of multiple contexts (P0_2nd_in, P1_2nd_in) is set by a set of multiple contexts (P0_2nd_c0, P1_2nd_c0). Multiplexer 1306 couples output port P73 to input port P72, such that a set of multiple contexts (P0_2nd_in', P1_2nd_in') is set by a set of multiple contexts (P0_2nd_c1, P1_2nd_c1). The control signal of multiplexer 1310 is set based on the bin value bin_val_1st of the first bin. When the bin value bin_val_1st of the first bin is equal to 0, the multiplexer 1310 selects and outputs the bin value bin_val_2nd_c0 as the value to be used in the debinarization circuit (e.g., Figure 7 The bin value bin_val_2nd of the second bin is debinded at the debinding circuit 110 shown. When the bin value bin_val_1st of the first bin is equal to 1, the multiplexer 1310 selects and outputs the bin value bin_val_2nd_c1 as the value to be debinded in the debinding circuit (e.g., the debinding circuit 110). Figure 7 The binary code value bin_val_2nd of the second bin is debinded at the debinding circuit 110 shown.

[0064] Furthermore, the bin decoding core circuit 1302 provides a range_2nd_c0 and an offset_2nd_c0, wherein the range_2nd_c0 and the offset_2nd_c0 can be the same as the range_1st_o and the offset_1st_o, respectively, or can be obtained by updating the range_1st_o and the offset_1st_o in step 206 and / or step 212. Similarly, the bin decoding core circuit 1302 provides a range_2nd_c1 and an offset_2nd_c1, wherein the range_2nd_c1 and the offset_2nd_c1 can be the same as the range_1st_o and the offset_1st_o, or can be obtained by updating the range_1st_o and the offset_1st_o in step 206 and / or step 212. The control signals of the multiplexer 1308 are set based on the bin value bin_val_1st of the first bin. When the bin value bin_val_1st of the first bin is equal to 0, the multiplexer 1308 selects and outputs the range range_2nd_c0 and offset_2nd_c0 as the range range_2nd_o and offset_2nd_o, respectively. When the bin value bin_val_1st of the first bin is equal to 1, the multiplexer 1308 selects and outputs the range range_2nd_c1 and offset_2nd_c1 as the range range_2nd_o and offset_2nd_o, respectively. In this case, the range range_2nd_o will be stored in the range memory (e.g., ...). Figure 7 The range memory 114 shown is used, and the offset offset_2nd_o will be stored in the offset memory (e.g., Figure 7 The offset memory 116 shown in the figure.

[0065] Consider another case where the bin decoding circuit 1300 is controlled to operate in a cyclic two-bin CABAC decoding mode (en_2bin = 1), and the decoding of the first bin and the second bin selects the same context source (sel_2nd = 0). A set of multiple contexts (P0_2nd_in, P1_2nd_in) and a set of multiple contexts (P0_2nd_in', P1_2nd_in') are both set by the same set of multiple updated contexts (P0_1st_o, P1_1st_o). Therefore, the bin value bin_val_2nd_c0 is the same as the bin value bin_val_2nd_c1, and the multiplexer 1310 selects and outputs one of the bin values ​​bin_val_2nd_c0 and bin_val_2nd_c1 as the bin that will undergo debining at the debining circuit (e.g., ...). Figure 7 The bin value bin_val_2nd of the second bin of the debinarization circuit 110 shown. Additionally, the range range_2nd_c0 is the same as the range range_2nd_c1, and the offset offset_2nd_c0 is the same as the offset offset_2nd_c1. Multiplexer 1308 selects and outputs one of the ranges range_2nd_c0 and range_2nd_c1 as the range range_2nd_o, and selects and outputs one of the offsets offset_2nd_c0 and range_2nd_c1 as the offset offset_2nd_o. In this case, the range range_2nd_o will be stored in the range memory (e.g., ...). Figure 7 The range memory 114 shown is used, and the offset offset_2nd_o will be stored in the offset memory (e.g., Figure 7 The offset memory 116 shown in the figure.

[0066] The bin decoding circuit 1300 can also support decoding only a single bin in one cycle (stage). When the bin decoding circuit 1300 is controlled to operate in a single-bin-single-cycle CABAC decoding mode (en_2bin = 0), the binary decoding core circuit 1302 receives the first part of the bitstream input bs_in_1st from the barrel shifter 102, and decodes and generates the bin value bin_val_1st_c0 of the first bin based on multiple contexts (P0_1st, P1_1st), range, and offset, where the range range_1st_o and the offset offset_1st_o are generated after the first bin is decoded. In this case, the range range_1st_o will be stored in the range memory (e.g., Figure 7The range memory 114 shown is used, and the offset offset_1st_o will be stored in the offset memory (e.g., Figure 7 The offset memory 116 shown in the figure.

[0067] The bin decoding core circuit 1302 is shown having three processing circuits (labeled "bin decoding") 1312, 1314, and 1316. In one exemplary design, processing circuits 1312, 1314, and 1316 can be separate processing circuits, wherein processing circuit 1312 is dedicated to processing the decoding of the first bin to produce the bin value bin_val_1st, processing circuit 1314 is dedicated to processing the decoding of the second bin to produce the bin value bin_val_2nd_c0, and processing circuit 1316 is dedicated to processing the decoding of the second bin to generate the bin value bin_val_2nd_c1. In another exemplary design, processing circuits 1312, 1314, and 1316 can be the same processing circuit (i.e., shared processing circuit) used to process the decoding of the first bin for generating the bin value bin_val_1st, and are reused to process the decoding of the second bin to generate the bin values ​​bin_val_2nd_c0 and bin_val_2nd_c1. In short, the present invention does not limit the physical implementation of the bin decoding core circuit 1302.

[0068] The bin decoding core circuit 1302 further outputs an indicator value `shift_bits_no_1st`, indicating how many bits were consumed during CABAC decoding of the first bin; another indicator value `shift_bits_no_2nd_c0`, indicating how many bits were consumed during CABAC decoding of the second bin on one decoding path; and another indicator value `shift_bits_no_2nd_c1`, indicating how many bits were consumed during CABAC decoding of the second bin on another decoding path. The control signal of the multiplexer 1309 is set based on the bin value `bin_val_1st` of the first bin. When the bin value `bin_val_1st` of the first bin equals 0, the multiplexer 1309 selects and outputs the indicator value `shift_bits_no_2nd_c0` as the indicator value `shift_bits_no_2nd`. When the bin value `bin_val_1st` of the first bin equals 1, the multiplexer 1309 selects and outputs the indicator value `shift_bits_no_2nd_c1` as the indicator value `shift_bits_no_2nd`.

[0069] When the bin decoding circuit 1300 is controlled to operate in the dual-bin single-cycle CABAC decoding mode (en_2bin = 1), the indicator values ​​shift_bits_no_1st and shift_bits_no_2nd are added together to set the barrel shifter (e.g., Figure 7 The indicator value shift_bits_no is referenced by the barrel shifter 102 shown. When the bin decoding circuit 1300 is controlled to operate in a single-bin single-cycle CABAC decoding mode (en_2bin = 0), the indicator value shift_bits_no_1st is output by the barrel shifter (e.g., in...). Figure 7 The indicated value shift_bits_no is referenced by the barrel shifter 102 shown.

[0070] Furthermore, local buffer 112 can be configured to include at least six local buffer units. When the bin decoding circuit 1300 is controlled to operate in a dual-bin-single-cycle CABAC decoding mode (en_2bin = 1) and the decoding of the first bin and the decoding of the second bin select the same context source (sel_2nd = 0), the multiplexer 1318 controlled by the context index ctx_inc can load only one set of multiple contexts (P0_1st, P1_1st) from the context pool storage 108 into two local buffer units of local buffer 112. When the bin decoding circuit 1300 is controlled to operate in the dual-bin single-cycle CABAC decoding mode (en_2bin=1) and when the decoding of the first bin and the second bin select different context sources (sel_2nd=1), the multiplexer 1318 controlled by the context index ctx_inc can load all of multiple contexts (P0_1st, P1_1st), multiple contexts (P0_2nd_c0, P1_2nd_c0), and multiple contexts (P0_2nd_c1, P1_2nd_c1) from the context pool memory 108 into the six local buffer units of the local buffer 112. When the bin decoding circuit 1300 is controlled to operate in the single-bin single-cycle CABAC decoding mode (en_2bin=0), the multiplexer 1318 controlled by the context index ctx_inc can load only multiple (P0_1st, P1_1st) from the context pool memory 108 into the two local buffer units of the local buffer 112.

[0071] Figure 14 This is a flowchart illustrating a CABAC decoding method according to an embodiment of the present invention. The CABAC decoding method can be... Figure 1 The CABAC decoder 100 shown employs a bin decoding circuit 104 that can be derived from... Figure 7The bin decoding circuit 700 shown or Figure 13 The bin decoding circuit 1300 shown is implemented, and the context update circuit 106 can be implemented by... Figure 4 The context update circuit 400 shown or Figure 10 The context update circuit 1000 shown is used for implementation. If the results are essentially the same, it is not necessary to follow the steps outlined. Figure 14 These steps are performed in the exact order shown. In step 1402, the context required for the CABAC decoding process is loaded. For example, the number of contexts actually loaded from the context pool memory 108 may depend on whether decoding two bins in one cycle (stage) is enabled, whether the decoding of the first bin and the decoding of the second bin select the same context source, and / or whether the context selection of the second bin depends on the bin value of the first bin. In step 1404, the CABAC decoding process in one cycle (stage) may generate bin_val_1st, range_1st_0, offset_1st_o, P0_1st_o, P1_1st_o for a single_bin_single_cycle mode, or may generate bin_val_1st, bin_val_2nd, range_1st_0, range_2nd_0, offset_1st_o, offset_2nd_o, P0_1st_o, P1_1st_o, P0_2nd_o, and P1_2nd_o for a multi_bin_single_cycle mode. In step 1408 or 1412, the range recorded in the range memory 114 and the offset recorded in the offset memory 116 are updated. In step 1410, 1416, or 1418, the context stored in the context pool memory 108 is updated. This is readily understood by those skilled in the art. Figure 14 Details of the steps shown are provided below. For brevity, further descriptions are omitted here after reading the above paragraphs regarding the proposed CABAC decoder design.

[0072] Those skilled in the art will readily observe that many modifications and alterations can be made to the apparatus and methods while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the limits and scope of the appended claims.

Claims

1. A context-based adaptive binary arithmetic coding (CABAC) decoder comprising: a bin decoding circuit to support decoding of at least a first bin and a second bin in a cycle, wherein the bin decoding circuit generates a bin value for the first bin according to a first plurality of contexts, a first range, and a first offset, and generates a bin value for the second bin according to a second plurality of contexts, a second range, and a second offset, wherein each of the second range and the second offset depends on the decoding of the first bin; and a context update circuit to update the first plurality of contexts in response to the bin value of the first bin to generate a first plurality of updated contexts, and further arranged to update the second plurality of contexts in response to the bin value of the second bin to generate a second plurality of updated contexts; wherein the context update circuit is arranged to: generate the first plurality of updated contexts according to the first plurality of contexts, the bin value of the first bin, and a first plurality of adaptation rates; and generate the second plurality of updated contexts according to the second plurality of contexts, the bin value of the second bin, and a second plurality of adaptation rates; a first multiplexer circuit having a first input port to receive the first plurality of updated contexts, a second input port to receive a third plurality of contexts, and a first output port to output a second plurality of contexts to the context update circuit, wherein the first multiplexer circuit is arranged to couple the first output port to one of the first input port and the second input port; and a second multiplexer circuit having a third input port arranged to receive the first plurality of adaptation rates, a fourth input port arranged to receive a third plurality of adaptation rates, and a second output port arranged to output the second plurality of adaptation rates to the context update circuit, wherein the second multiplexer circuit is arranged to couple the second output port to one of the third input port and the fourth input port. the context update circuit comprises a plurality of separate processing circuits, the plurality of separate processing circuits comprising a first processing circuit dedicated to processing context updates of the first plurality of contexts and a second processing circuit dedicated to processing context updates of the second plurality of contexts. the context update circuit is a shared processing circuit to process context updates of the first plurality of contexts and reused to process context updates of the second plurality of contexts. the decoding of the first bin and the decoding of the second bin select a same context source, the first multiplexer circuit couples the first output port to the first input port, and the second multiplexer circuit couples the second output port to the third input port.

2. The CABAC decoder of claim 1, wherein, further comprising:

3. The CABAC decoder of claim 1, wherein, a context pool storage; 4. The CABAC decoder of claim 1, wherein, ​ 5. The CABAC decoder of claim 4, wherein, ​ ​ wherein the first plurality of contexts are set from stored contexts loaded from the context pool storage, and the context update circuit is further arranged to write the second plurality of updated contexts back into the context pool storage for updating the stored contexts in the context pool storage with the second plurality of updated contexts.

6. The CABAC decoder of claim 4, wherein, Further comprising: a context pool storage; wherein the first plurality of contexts are set from stored contexts loaded from the context pool storage, and the third plurality of contexts are set from stored contexts loaded from the context pool storage.

7. The CABAC decoder of claim 1, wherein, The decoding of the first binary code and the decoding of the second binary code select different context sources, the first multiplexer circuit couples the first output port to the second input port, and the second multiplexer circuit couples the second output port to the fourth input port.

8. The CABAC decoder of claim 7, wherein, Further comprising: a context pool storage; wherein the first plurality of contexts are set from stored contexts loaded from the context pool storage, and the third plurality of contexts are set from stored contexts loaded from the context pool storage.

9. The CABAC decoder of claim 1, wherein The context update circuit further comprises: a third multiplexer circuit having a fifth input port arranged to receive a fourth plurality of contexts, a sixth input port arranged to receive a fifth plurality of contexts, and a third output port arranged to output the third plurality of contexts to the second input port of the first multiplexer circuit, wherein the third multiplexer circuit is arranged to couple the third output port to one of the fifth input port and the sixth input port; and a fourth multiplexer circuit having a seventh input port arranged to receive a fourth plurality of multiple adaptation rates, an eighth input port arranged to receive a fifth plurality of multiple adaptation rates, and a fourth output port arranged to output the third plurality of multiple adaptation rates to the fourth input port of the second multiplexer circuit, wherein the fourth multiplexer circuit is arranged to couple the fourth output port to one of the seventh input port and the eighth input port.

10. The CABAC decoder of claim 9, wherein, The control signals of each of the third multiplexer circuit and the fourth multiplexer circuit are set based on a binary code value of the first binary code.

11. The CABAC decoder of claim 1, wherein The binary code decoding circuit comprises: a binary code decoding core circuit for decoding and generating a binary code value of the first binary code and one binary code value of the second binary code; and a third multiplexer circuit having a fifth input port arranged to receive a first plurality of updated contexts, a sixth input port arranged to receive a third plurality of contexts, and a third output port arranged to output a second plurality of contexts to the binary decoding core circuit, wherein the third multiplexer circuit is arranged to couple the third output port to one of the fifth input port and the sixth input port.

12. The CABAC decoder of claim 11, wherein, The binary code decoding core circuit includes a plurality of separate processing circuits, including a first processing circuit and a second processing circuit, the first processing circuit being dedicated to processing decoding of binary values of the first binary code, and the second processing circuit being dedicated to processing decoding of one binary value of the second binary code.

13. The CABAC decoder of claim 11, wherein, The binary decoding core circuit is a shared processing circuit for processing decoding of binary values of the first binary code and reused for processing decoding of binary values of the second binary code.

14. The CABAC decoder of claim 11, wherein, The control signal of the third multiplexer circuit is set based on whether the decoding of the first binary code and the decoding of the second binary code select the same context source.

15. The CABAC decoder of claim 11, wherein The binary code decoding circuit further comprises: a fourth multiplexer circuit having a seventh input port configured to receive a first set of updated plurality of contexts, an eighth input port configured to receive a fourth set of plurality of contexts, and a fourth output port configured to output a fifth set of plurality of contexts to the binary decoding core circuit, wherein the fourth multiplexer circuit is arranged to couple the fourth output port to one of the seventh input port and the eighth input port, and the binary decoding core circuit is further arranged to decode and generate another binary value of the second binary code according to the fifth set of plurality of contexts; and a fifth multiplexer circuit having a ninth input port configured to receive one binary value of the second binary code, a tenth input port configured to receive another binary value of the second binary code, and a fifth output port configured to output binary values of the second binary code, wherein the fifth multiplexer circuit is arranged to couple the fifth output port to one of the ninth input port and the tenth input port.

16. The CABAC decoder of claim 15, wherein, The control signal of each of the third multiplexer circuit and the fourth multiplexer circuit is set based on whether the decoding of the first binary code and the decoding of the second binary code select the same context source.

17. The CABAC decoder of claim 15, wherein, The control signal of the fifth multiplexer circuit is set based on the binary values of the first binary code.

18. The CABAC decoder of claim 1, wherein, The binary code decoding circuit is further arranged to support decoding of only a single binary in one cycle.

19. A context-based adaptive binary arithmetic coding (CABAC) decoding method, comprising: performing, by a binary code decoding circuit, decoding of a plurality of binary codes in one cycle, wherein the plurality of binary codes includes a first binary code and a second binary code, and a binary value of the first binary code is decoded according to a first set of plurality of contexts, a first range, and a first offset, and one binary value of the second binary code is decoded according to a second set of plurality of contexts, a second range, and a second offset, wherein each of the second range and the second offset depends on the decoding of the first binary code; generating a first set of updated plurality of contexts according to the first set of plurality of contexts, the first binary value of the first binary code, and a first set of plurality of adaptation rates; and generating a second plurality of updated contexts from the second plurality of contexts, a second binary code value of the second binary code, and a second plurality of adaptation rates; receiving a first plurality of updated contexts and a third plurality of contexts, outputting the second plurality of contexts, and selectively outputting the first plurality of updated contexts or the third plurality of contexts as the second plurality of contexts; and receiving a first plurality of multiple adaptation rates and a third plurality of multiple adaptation rates, outputting the second plurality of multiple adaptation rates, and selectively outputting the first plurality of multiple adaptation rates or the third plurality of multiple adaptation rates as the second plurality of multiple adaptation rates.

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