Semiconductor structure and manufacturing method thereof

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises: providing a substrate; forming a conductive layer on the substrate, wherein in the process of forming the conductive layer, dust impurity particles are mixed in, so that the upper surface of the conductive layer comprises a first protrusion and other flat areas, and the projection of the first protrusion on the substrate at least partially overlaps with the projection of the dust impurity particles on the substrate; forming a first insulating layer covering the conductive layer, wherein the thickness of the first insulating layer is not greater than the height difference of the first protrusion relative to the other flat areas; forming a second insulating layer on the first insulating layer; removing the second insulating layer, comprising: performing an etching process on the second insulating layer to expose the first insulating layer, and the first insulating layer at least covers the first protrusion; wherein the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer; and performing a cleaning process using a cleaning liquid to remove etching residues or byproducts generated in the process of removing the second insulating layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor structure generally includes a substrate and a multi-layer structure on the substrate. However, during the manufacturing process of the semiconductor structure, some tiny particles are often attached to the surface of the substrate or any layer structure on the substrate. With the development of semiconductor technology towards miniaturization and high integration, the influence of these tiny particles on subsequent semiconductor processes will become more and more significant, ultimately leading to the reduction of the performance and stability of the semiconductor structure. SUMMARY

[0003] Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, comprising:

[0004] providing a substrate;

[0005] forming a conductive layer on the substrate, wherein during the formation of the conductive layer, a tiny dust impurity particle is mixed in, so that an upper surface of the conductive layer includes a first protrusion and other flat areas, and a projection of the first protrusion on the substrate at least partially coincides with a projection of the tiny dust impurity particle on the substrate;

[0006] forming a first insulating layer on the conductive layer, wherein the first insulating layer covers the upper surface of the conductive layer, and a thickness of the first insulating layer is not greater than a height difference of the first protrusion relative to the other flat areas;

[0007] forming a second insulating layer on the first insulating layer;

[0008] removing the second insulating layer, comprising: performing an etching process on the second insulating layer to expose the first insulating layer, and the first insulating layer at least covers the first protrusion; wherein an etching rate of the second insulating layer is greater than an etching rate of the first insulating layer;

[0009] performing a cleaning process using a cleaning solution to remove etching residues or byproducts generated during the removal of the second insulating layer.

[0010] In some embodiments, a material of the conductive layer includes tungsten.

[0011] In some embodiments, the cleaning solution includes a dilute hydrofluoric acid solution or a mixed solution of dilute sulfuric acid and hydrogen peroxide.

[0012] In some embodiments, a volume ratio of sulfuric acid, hydrogen peroxide and water in the mixed solution of dilute sulfuric acid and hydrogen peroxide is 1:2:20-1:2:100.

[0013] In some embodiments, the volume ratio of hydrofluoric acid to water in the dilute hydrofluoric acid solution is between 1:100 and 1:200.

[0014] In some embodiments, the material of the first insulating layer is nitride and the material of the second insulating layer is oxide.

[0015] In some embodiments, the second insulating layer includes a second portion and a first portion on the second portion; removing the second insulating layer includes:

[0016] performing a planarization process on the second insulating layer to remove the first portion of the second insulating layer;

[0017] performing an etching process on the remaining second portion of the second insulating layer to remove the remaining second insulating layer and expose the first insulating layer.

[0018] In some embodiments, the ratio of the thickness of the first portion of the second insulating layer to the thickness of the second portion of the second insulating layer is between 5:1 and 100:1.

[0019] In some embodiments, after performing the planarization process on the first portion of the second insulating layer, before performing the etching process on the remaining second portion of the second insulating layer, the method further includes: performing an additional cleaning process using the cleaning solution to remove residues or byproducts generated in performing the planarization process.

[0020] In some embodiments, the substrate includes an isolation structure and an active region separated by the isolation structure; forming the conductive layer on the substrate includes:

[0021] etching the substrate to form a recess in the substrate that exposes the active region, the portion of the active region exposed by the recess defining a contact region, and forming a first conductive layer on the substrate, wherein the first conductive layer includes a first sub-layer and a second sub-layer, the first sub-layer filling the recess and electrically connected to the contact region, and the second sub-layer covering the first sub-layer and an upper surface of the substrate.

[0022] forming a second conductive layer on the second sub-layer, the first conductive layer and the second conductive layer constituting the conductive layer.

[0023] In some embodiments, after removing the second insulating layer, the method further includes:

[0024] etching the first insulating layer to form a bit line cap layer and etching the second conductive layer and the second sub-layer to form a bit line layer.

[0025] In some embodiments, the method further comprises:

[0026] The first sub-layer not covered by the bit line layer is removed to form a bit line plug, and the bit line plug is formed with a gap on both sides.

[0027] In some embodiments, the method further comprises:

[0028] A third insulating layer is formed, covering the top surface and sidewall of the bit line cover layer, the sidewall of the bit line layer, and the sidewall of the bit line plug, and filling the gap.

[0029] The embodiments of the present disclosure also provide a semiconductor structure made by any of the above manufacturing methods.

[0030] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure, wherein the manufacturing method comprises: providing a substrate; forming a conductive layer on the substrate, wherein some dust impurity particles are mixed in the process of forming the conductive layer, so that the upper surface of the conductive layer comprises a first protrusion and other flat areas, and the projection of the first protrusion on the substrate at least partially overlaps with the projection of the dust impurity particles on the substrate; forming a first insulating layer on the conductive layer, wherein the first insulating layer covers the upper surface of the conductive layer, and the thickness of the first insulating layer is not greater than the height difference of the first protrusion relative to the other flat areas; forming a second insulating layer on the first insulating layer; removing the second insulating layer, comprising: performing an etching process on the second insulating layer to expose the first insulating layer, and the first insulating layer at least covers the first protrusion; wherein the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer; and performing a cleaning process by using a cleaning liquid to remove the etching residues or by-products generated in the process of removing the second insulating layer. In the embodiments of the present disclosure, when some dust impurity particles are mixed in the process of forming the conductive layer in the manufacturing process of the semiconductor structure, the first protrusion will be generated on the upper surface of the conductive layer due to the existence of the dust impurity particles. In the embodiments of the present disclosure, the first insulating layer is formed on the conductive layer, the first insulating layer covers the first protrusion, the second insulating layer is formed on the first insulating layer, and the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer. Therefore, when the second insulating layer is etched to expose the first insulating layer, the damage of the etching process to the first insulating layer can be avoided or reduced, so that the first protrusion of the conductive layer is not exposed, and the subsequent process will not cause damage to the conductive layer. Meanwhile, after the second insulating layer is removed by etching, the cleaning process is performed by using the cleaning liquid to remove the etching residues or by-products generated in the process of removing the second insulating layer. The cleaning liquid is difficult to react with the conductive layer. Therefore, even if the first protrusion of the conductive layer is exposed due to the damage of the first insulating layer when the second insulating layer is removed, the cleaning liquid will not cause damage to the conductive layer.

[0031] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description, drawings and claims. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0033] Figure 1A flow chart of a method for manufacturing a semiconductor structure is provided for embodiments of the present disclosure.

[0034] Figures 2 to 10 A process flow diagram of a method for manufacturing a semiconductor structure is provided for embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] Example embodiments of the present disclosure will be described herein below with reference to drawings. While example embodiments of the present disclosure are illustrated in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate this disclosure. In the description of the present disclosure, the terms "couple" and "coupled" refer to an operational coupling, whether mechanical, electrical, magnetic, or the like, between two components.

[0037] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0038] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature is oriented "above" or "over" the other element or feature. Thus, the exemplary term "below" or "beneath" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] A semiconductor structure generally includes a substrate and a multi-layer structure on the substrate. However, during the manufacturing process of the semiconductor structure, some tiny particles are often attached to the surface of the substrate or any layer structure on the substrate. As the semiconductor technology develops towards miniaturization and high integration, the influence of these tiny particles on the subsequent semiconductor process will become more and more significant, eventually leading to the reduction of the performance and stability of the semiconductor structure.

[0042] For example, when a conductive layer is formed on a substrate and a thicker insulating layer is formed on the conductive layer, then a planarization process is used to remove part of the insulating layer, and the insulating layer and the conductive layer are etched to form a bit line cap layer and a bit line layer, respectively, some dust and impurity particles are easily mixed in the process of forming the conductive layer. Due to the presence of the particles, a protruding structure is formed on the upper surface of the conductive layer. When the planarization process is used to remove part of the insulating layer, the thickness of the insulating layer that is usually reserved is less than the height difference of the protruding structure relative to the flat area of the conductive layer, which will cause the protruding structure on the surface of the conductive layer to be exposed, thereby causing the conductive layer to be damaged in the subsequent process, and causing the subsequently formed bit line to be defective and tilted or collapsed.

[0043] Therefore, the following technical solutions of the embodiments of the disclosure are proposed.

[0044] The present disclosure provides a method for manufacturing a semiconductor structure. Figure 1 As shown in the figure, the method includes the following steps:

[0045] Step 101: providing a substrate;

[0046] Step 102: forming a conductive layer on a substrate, wherein fine dust particles are mixed into the conductive layer during the formation process, so that the upper surface of the conductive layer includes a first protrusion and other flat areas, and the projection of the first protrusion on the substrate at least partially overlaps with the projection of the fine dust particles on the substrate;

[0047] Step 103: forming a first insulating layer on the conductive layer, wherein the first insulating layer covers the upper surface of the conductive layer, and the thickness of the first insulating layer is no greater than the height difference between the first protrusion and the other flat areas;

[0048] Step 104: forming a second insulating layer on the first insulating layer;

[0049] Step 105: removing the second insulating layer, including: performing an etching process on the second insulating layer to expose the first insulating layer, wherein the first insulating layer at least covers the first protrusion; wherein the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer;

[0050] Step 106 : Perform a cleaning process using a cleaning solution to remove residues generated during the removal of the second insulating layer.

[0051] In an embodiment of the present disclosure, during the manufacturing process of a semiconductor structure, when some dust and impurity particles are mixed in during the process of forming a conductive layer, a first protrusion will be generated on the upper surface of the conductive layer due to the presence of the dust and impurity particles. In this embodiment of the present disclosure, a first insulating layer is formed on the conductive layer, the first insulating layer covering the first protrusion, and a second insulating layer is formed on the first insulating layer, and the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer. In this way, when the second insulating layer is etched to expose the first insulating layer, damage to the first insulating layer caused by the etching process can be avoided or reduced, thereby preventing the first protrusion of the conductive layer from being exposed, and further preventing subsequent processes from damaging the conductive layer. At the same time, after etching and removing the second insulating layer, a cleaning process is performed using a cleaning solution to remove etching residues or byproducts generated during the removal of the second insulating layer. The cleaning solution is unlikely to react with the conductive layer. Therefore, even if the first insulating layer is damaged during the removal of the second insulating layer, resulting in the first protrusion of the conductive layer being exposed, the cleaning solution will not damage the conductive layer.

[0052] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure can be used to form a dynamic random access memory (DRAM). However, the method is not limited to this, and any semiconductor structure can be manufactured by the method provided by the embodiments of the present disclosure.

[0053] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

[0054] Figures 2 to 10 The process flow chart of the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure is shown in FIG. 1. The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure will be described in detail below with reference to FIG. 1. Figures 2 to 10 The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure will be described in detail below with reference to FIG. 1.

[0055] First, step 101 is performed, as shown in FIG. 1, a substrate 20 is provided. Figure 2

[0056] The substrate can be a semiconductor substrate, and can include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate is a silicon substrate, which can be doped or undoped.

[0057] In one embodiment, the substrate 20 includes an isolation structure 21 and an active area AA separated by the isolation structure 21. Specifically, the number of active areas AA is multiple, the multiple active areas AA are arranged in parallel, and the isolation structure 21 is located between the multiple active areas AA. The material of the isolation structure 21 includes one or more of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride).

[0058] In one embodiment, the substrate 20 further includes a dielectric layer 22 on the surface, and the dielectric layer 22 can have a multi-layer structure, for example, the dielectric layer 22 can include an oxide layer (e.g., silicon oxide) and a nitride layer (e.g., silicon nitride layer) on the oxide layer.

[0059] ​In actual operation, the isolation structure and the dielectric layer can be formed in the following way: first, etching the substrate to form isolation trenches, the isolation trenches define the substrate into a plurality of discrete active regions; then, using a chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other process to deposit dielectric material in the isolation trenches and on the surface of the substrate, the dielectric material in the trenches is defined as the isolation structure, and the dielectric material on the surface of the substrate is defined as the dielectric layer.

[0060] Next, step 102 is performed, as shown in FIG. 1C, a conductive layer L is formed on the substrate 20, and in the process of forming the conductive layer L, the dust impurity particles 23 are mixed in, so that the upper surface of the conductive layer L includes a first protrusion 281 and other flat areas, and the projection of the first protrusion 281 on the substrate 20 at least partially coincides with the projection of the dust impurity particles 23 on the substrate 20. Figures 3 to 4

[0061] The conductive layer L can be a single-layer structure or a multi-layer structure. In some embodiments, the conductive layer L includes a first conductive layer 26 and a second conductive layer 28. Specifically, the conductive layer L is formed on the substrate 20, including:

[0062] The substrate 20 is etched to form a groove T in the substrate 20 that exposes the active region AA, the portion of the active region AA exposed by the groove T is defined as a contact region 34, and a first conductive layer 26 is formed on the substrate 20, wherein the first conductive layer 26 includes a first sub-layer 24 and a second sub-layer 25, the first sub-layer 24 fills the groove and is electrically connected to the contact region 34, and the second sub-layer 25 covers the first sub-layer 24 and the upper surface of the substrate 20;

[0063] The second conductive layer 28 is formed on the second sub-layer 25, and the first conductive layer 26 and the second conductive layer 28 constitute the conductive layer L.

[0064] In an embodiment, the second sub-layer 25 can be formed after the first sub-layer 24 is formed. For example, the first sub-layer 24 and the second sub-layer 25 can be formed by the following method: first, a mask pattern (not shown) is formed on the substrate 20, the mask pattern (not shown) covers the dielectric layer 22; then, the substrate 20 is etched with the mask pattern (not shown) as a mask, and part of the dielectric layer 22, part of the active region AA and part of the isolation structure 21 on both sides of the active region AA are removed to form a groove T; then, the first sub-layer 24 is formed in the groove T; then, the mask pattern (not shown) is removed, and the second sub-layer 25 is formed, covering the surface of the dielectric layer 22 and the first sub-layer 24.

[0065] ​However, the first sub-layer and the second sub-layer can be formed by other methods. For example, a first initial sub-layer is formed on the substrate, the first initial sub-layer and the substrate are etched to form an opening in the first initial sub-layer and a recess in the substrate under the opening, and a conductive material is formed in the opening and the recess, the conductive material in the recess defines the first sub-layer, and the conductive material in the opening and the remaining second initial sub-layer define the second sub-layer.

[0066] In one embodiment, the material of the conductive layer L includes tungsten. Specifically, the material of the second conductive layer 28 includes tungsten. In practice, the second conductive layer 28 can be formed on the substrate 20 by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or the like.

[0067] The material of the first sub-layer 24 and the second sub-layer 25 can be the same or different. The material of the first sub-layer 24 and the second sub-layer 24 includes silicon, silicon germanium, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. In one embodiment, the material of the first sub-layer 24 and the second sub-layer 25 is the same, for example, polysilicon, which can be doped or undoped. In practice, the first sub-layer 24 and the second sub-layer 25 can be formed on the substrate 20 by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or the like.

[0068] In practice, some dust particles can be mixed in during the formation of the conductive layer and adhere to the substrate. Specifically, some mask pattern layers can be formed on the substrate during the formation of the conductive layer and used as etching masks. The material of the mask pattern layers can be oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), photoresist, or the like. After the target layer is etched to form a target pattern using the mask pattern layers as etching masks, the mask pattern layers can be removed by ashing or the like. During the removal of the mask pattern layers, some residues (e.g., ashing residues) can be generated and adhere to the semiconductor structure. Alternatively, some etching byproducts or residues can be generated and adhere to the semiconductor structure during the etching of the target layer.

[0069] As shown in FIG. 1, the semiconductor structure 10 includes a substrate 20, a first sub-layer 24, a second sub-layer 25, a first dielectric layer 26, a second dielectric layer 27, and a second conductive layer 28. Figure 3 and Figure 4As shown, in the process of forming the conductive layer L, due to the mixing of the dust impurity particles 23, the upper surface of the conductive layer L is formed with the first protrusion 281. Specifically, when the dust impurity particles 23 are attached to the surface of the dielectric layer 22 before the formation of the second sub-layer 25, due to the presence of the dust impurity particles 23, the second protrusion 251 is formed on the surface of the second sub-layer 25, and the projection of the second protrusion 251 on the substrate 20 at least partially overlaps with the projection of the dust impurity particles 23 attached to the surface of the dielectric layer 22 on the substrate 20; when the dust impurity particles 23 are attached to the surface of the second sub-layer 25 after the formation of the second sub-layer 25, due to the presence of the dust impurity particles 23 and the second protrusion 251, the first protrusion 281 is formed on the surface of the second conductive layer 28.

[0070] Next, step 103 is performed, as shown in FIG. 1C. Figure 5 As shown, the first insulating layer 29 is formed on the conductive layer L, the first insulating layer 29 covers the upper surface of the conductive layer L, and the thickness of the first insulating layer 29 is not greater than the height difference of the first protrusion 281 relative to other flat areas.

[0071] The first insulating layer 29 can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0072] As shown, in an embodiment, the first insulating layer 29 also covers the first protrusion 281, and the first insulating layer 29 is used to protect the second conductive layer 28 from being contaminated or damaged in subsequent process steps. In some embodiments, due to the presence of the first protrusion 281, when the first insulating layer 29 is formed, the third protrusion 291 will be formed on the upper surface of the first insulating layer 29 and above the position of the dust impurity particles 23, and the projection of the third protrusion 291 on the substrate 20 at least partially overlaps with the projection of the dust impurity particles 23 on the substrate 20.

[0073] In the embodiments of the present disclosure, the thickness of the first insulating layer 29 is not greater than the height difference of the first protrusion 281 relative to other flat areas, that is, the upper surface of the first protrusion 281 is higher than the upper surface of the flat area of the first insulating layer 29.

[0074] Next, step 104 is performed, as shown in FIG. 1D. Figure 6 As shown, the second insulating layer 31 is formed on the first insulating layer 29.

[0075] In actual operation, the second insulating layer 31 can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0076] In one embodiment, the second insulating layer 31 includes a second portion 312 and a first portion 311 located on the second portion 312. In some embodiments, the ratio of the thickness of the first portion 311 of the second insulating layer 31 to the thickness of the second portion 312 of the second insulating layer 31 is in a range of 5:1 to 100:1, for example, 5:1, 10:1, 20:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, or 100:1. In a specific embodiment, the material of the first portion 311 of the second insulating layer 31 is the same as the material of the second portion 312 of the second insulating layer 31.

[0077] Next, execute step 105, as Figures 7 to 8 As shown, removing the second insulating layer 31 includes: performing an etching process on the second insulating layer 31 to expose the first insulating layer 29, and the first insulating layer 29 at least covers the first protrusion 281; wherein the etching rate of the second insulating layer 31 is greater than the etching rate of the first insulating layer 29.

[0078] Specifically, removing the second insulating layer 31 includes:

[0079] performing a planarization process on the second insulating layer 31 to remove the first portion 311 of the second insulating layer 31 ;

[0080] An etching process is performed on the remaining second portion 312 of the second insulating layer 31 to remove the remaining second insulating layer 31 and expose the first insulating layer 29 .

[0081] However, the present invention is not limited thereto. Alternatively, only an etching process may be used to remove the second insulating layer 31 to expose the first insulating layer 29 .

[0082] In the embodiment of the present disclosure, the thickness of the first insulating layer 29 is not greater than the height difference between the first protrusion 281 and the other flat areas. That is, the upper surface of the first protrusion 281 is higher than the upper surface of the flat area of ​​the first insulating layer 29. If the etching process is performed first and then the planarization process is performed, or only the planarization process is performed to remove the second insulating layer 31, when the planarization process is performed to remove the second insulating layer 31, it is easy to cause the third protrusion 291 located on the upper surface of the first insulating layer 29 to also be planarized, thereby exposing the first protrusion 281 located on the upper surface of the conductive layer L, which may cause the subsequent etching of the conductive layer L to form the bit line layer 32 (see Figure 9 ) produces defects, the bit line layer 32 (see Figure 9) collapse or tilt. The embodiments of the present disclosure avoid or reduce damage to the first insulating layer 29, and thus avoid or reduce damage to the conductive layer L, especially the first protrusion 281, by performing the planarization process before the etching process, or performing the etching process to remove the second insulating layer 31, instead of performing the etching process before the planarization process, or performing the planarization process to remove the second insulating layer 31. Meanwhile, in the embodiments of the present disclosure, the etching process on the second insulating layer 31 can be performed by using a dry or wet process, and under a preset etching condition, the etching rate of the second insulating layer 31 is greater than the etching rate of the first insulating layer 29, which further avoids damaging the first insulating layer 29 when removing the second insulating layer 31, thereby avoiding or reducing defects in the subsequently formed bit line layer 32 (see Figure 9 ). In the embodiments of the present disclosure, after removing the second insulating layer 31, the first insulating layer 29 still covers the first protrusion 281, which protects the conductive layer L. In a specific embodiment, the material of the first insulating layer 29 is nitride (for example, silicon nitride), and the material of the second insulating layer 31 is oxide (for example, silicon oxide).

[0083] Next, step 106 is performed, and a cleaning process is performed by using a cleaning liquid to remove residues generated in the process of removing the second insulating layer 31.

[0084] In an embodiment, after performing the planarization process on the first portion 311 of the second insulating layer 31, before performing the etching process on the second portion 312 of the remaining second insulating layer 31, an additional cleaning process is further performed by using a cleaning liquid to remove residues or byproducts generated in the planarization process. In the embodiments of the present disclosure, the cleaning process is performed by using a cleaning liquid including hydrofluoric acid or a cleaning liquid including dilute sulfuric acid and hydrogen peroxide, which is difficult to react with the second conductive layer 28, so that even if the first insulating layer 29 is damaged in the process of performing the planarization process or the etching process to remove the second insulating layer 31, and the first protrusion 281 on the upper surface of the second conductive layer 28 is exposed, the cleaning liquid will not damage the protrusion structure. However, it is not limited thereto, and any cleaning liquid that is difficult to react with the second conductive layer 28 can be used as the cleaning liquid for removing residues generated in the planarization or etching process in the embodiments of the present disclosure.

[0085] In an embodiment, the cleaning solution includes a dilute hydrofluoric acid solution or a dilute sulfuric acid and hydrogen peroxide mixed solution. When the cleaning process is performed using a cleaning solution including dilute sulfuric acid and hydrogen peroxide, the ratio of the concentration of the sulfuric acid to the concentration of the hydrogen peroxide in the cleaning solution should not be too small or too large; if the ratio of the concentration of the sulfuric acid to the concentration of the hydrogen peroxide in the cleaning solution is too small, the concentration of the hydrogen peroxide in the cleaning solution is large, the oxidizing property of the cleaning solution is strong, and when the second conductive layer 28 is exposed in the process of removing the second insulating layer 31, the second conductive layer 28 is easily oxidized and removed by the sulfuric acid, which causes great damage to the second conductive layer 28; if the ratio of the concentration of the sulfuric acid to the concentration of the hydrogen peroxide in the cleaning solution is too small, the effect of removing the residue is poor. In a specific embodiment, the volume ratio of the sulfuric acid, the hydrogen peroxide, and the water in the dilute sulfuric acid and hydrogen peroxide mixed solution is 1:2:20-1:2:100, for example, 1:2:20, 1:2:30, 1:2:40, 1:2:50, 1:2:60, 1:2:70, 1:2:80, 1:2:90, or 1:2:100.

[0086] When the cleaning process is performed using a dilute hydrofluoric acid solution, the concentration of the hydrofluoric acid should not be too large or too small; if the concentration of the hydrofluoric acid is too small, the cleaning effect is poor; if the concentration of the hydrofluoric acid is too large, the hydrofluoric acid solution easily damages the conductive layer L when the second conductive layer 28 is exposed in the process of removing the second insulating layer 31. In some embodiments, the volume ratio of the hydrofluoric acid and the water in the dilute hydrofluoric acid solution is 1:100-1:200, for example, 1:100, 1:110, 1:120, 1:130, 1:140, 1:150, 1:160, 1:170, 1:180, 1:190, or 1:200.

[0087] Next, as shown in FIG. 3B, after the second insulating layer 31 is removed, the method further includes: Figure 9

[0088] The first insulating layer 29 is etched to form a bit line cap layer 33, and the second conductive layer 28 and the second sub-layer 25 are etched to form a bit line layer 32.

[0089] In an embodiment, the second conductive layer 28 and the second sub-layer 25 are etched to form the bit line layer 32, including: etching the second conductive layer 28 to form a first bit line sub-layer 321; etching the second sub-layer 25 to form a second bit line sub-layer 322, and the first bit line sub-layer 321 and the second bit line sub-layer 322 constitute the bit line layer 32.

[0090] Referring again to FIG. 3B, the method further includes: removing the first sub-layer 24 that is not covered by the bit line layer 32 to form a bit line plug 241, and gaps are formed on both sides of the bit line plug 241. Figure 9

[0091] ​​In the actual process, the first insulating layer 29 can be etched from top to bottom in the direction perpendicular to the substrate 20 in the same process to form the bit line cap layer 33, the second conductive layer 28 and the second sub-layer 25 are etched to form the bit line layer 32, and the first sub-layer 24 is continuously etched to form the bit line plug 241 with the bit line cap layer 33 and the bit line layer 32 as a mask. The lower end of the bit line layer 32 is electrically connected with the bit line plug 241, and the lower end of the bit line plug 241 is electrically connected with the contact region 34.

[0092] It can be seen that, in the embodiments of the present disclosure, although the dust impurity particles 23 generated in the manufacturing process of the semiconductor structure may still remain in the bit line layer 32, the embodiments of the present disclosure remove the second insulating layer 31 by performing the planarization process first and then performing the etching process, or only performing the etching process, and adopt the cleaning process including the dilute hydrofluoric acid solution or the dilute sulfuric acid and hydrogen peroxide mixed solution in the process of removing the second insulating layer 31, thereby avoiding or reducing the damage to the conductive layer L, minimizing the influence of the dust impurity particles 23 on the bit line layer 32, and further minimizing the influence of the dust impurity particles 23 on the performance and stability of the semiconductor structure.

[0093] Next, referring to Figure 10 , the method further includes: forming a third insulating layer 35, the third insulating layer 35 covering the top surface and the sidewall of the bit line cap layer 33, the sidewall of the bit line layer 32, and the sidewall of the bit line plug 241, and filling the gap. In actual operation, the third insulating layer 35 can be formed by using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or the like. The material of the third insulating layer 35 includes one or more of an oxide (such as silicon oxide), a nitride (such as silicon nitride), and an oxynitride (such as silicon oxynitride). In a specific embodiment, the material of the third insulating layer 35 is silicon nitride.

[0094] It should be noted that the skilled in the art can make possible changes between the above-mentioned step sequences without departing from the protection scope of the present disclosure.

[0095] The embodiments of the present disclosure also provide a semiconductor structure, which is manufactured by using any one of the above-mentioned manufacturing methods.

[0096] It should be noted that the above-mentioned is only a preferred embodiment of the present application, and is not used to limit the protection scope of the present application, and any modification, equivalent replacement, and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a conductive layer on the substrate, wherein fine dust and foreign particles are mixed into the conductive layer during the formation of the conductive layer, so that the upper surface of the conductive layer includes a first protrusion and other flat areas, and a projection of the first protrusion on the substrate at least partially overlaps with a projection of the fine dust and foreign particles on the substrate; forming a first insulating layer on the conductive layer, wherein the first insulating layer covers the upper surface of the conductive layer, and a thickness of the first insulating layer is no greater than a height difference between the first protrusion and the other flat areas; forming a second insulating layer on the first insulating layer; Removing the second insulating layer includes: performing an etching process on the second insulating layer to expose the first insulating layer, wherein the first insulating layer at least covers the first protrusion; wherein the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer; A cleaning process is performed using a cleaning solution to remove etching residues or by-products generated during the process of removing the second insulating layer.

2. The manufacturing method according to claim 1, characterized in that The conductive layer is made of tungsten.

3. The manufacturing method according to claim 2, characterized in that The cleaning solution includes a dilute hydrofluoric acid solution or a mixed solution of dilute sulfuric acid and hydrogen peroxide.

4. The manufacturing method according to claim 3, characterized in that The volume ratio of sulfuric acid, hydrogen peroxide and water in the mixed solution of dilute sulfuric acid and hydrogen peroxide is 1:2:20 to 1:2:

100.

5. The manufacturing method according to claim 3, characterized in that The volume ratio of hydrofluoric acid to water in the dilute hydrofluoric acid solution is 1:100 to 1:

200.

6. The manufacturing method according to claim 1, characterized in that The material of the first insulating layer is nitride, and the material of the second insulating layer is oxide.

7. The manufacturing method according to claim 1, characterized in that The second insulating layer includes a second portion and a first portion located on the second portion; Removing the second insulating layer includes: performing a planarization process on the second insulating layer to remove the first portion of the second insulating layer; An etching process is performed on the remaining second portion of the second insulating layer to remove the remaining second insulating layer and expose the first insulating layer.

8. The manufacturing method according to claim 7, characterized in that A ratio of a thickness of the first portion of the second insulating layer to a thickness of the second portion of the second insulating layer is in a range of 5:1 to 100:

1.

9. The manufacturing method according to claim 7, characterized in that: After performing a planarization process on the first portion of the second insulating layer, and before performing an etching process on the remaining second portion of the second insulating layer, the method further includes: performing an additional cleaning process using the cleaning solution to remove residues or by-products generated during the planarization process.

10. The manufacturing method according to claim 1, characterized in that The substrate includes an isolation structure and an active area separated by the isolation structure; forming a conductive layer on the substrate, comprising: Etching the substrate to form a groove in the substrate exposing the active area, wherein the portion of the active area exposed by the groove is defined as a contact area, and forming a first conductive layer on the substrate, wherein the first conductive layer includes a first sublayer and a second sublayer, the first sublayer fills the groove and is electrically connected to the contact area, and the second sublayer covers the first sublayer and the upper surface of the substrate; A second conductive layer is formed on the second sub-layer, and the first conductive layer and the second conductive layer constitute the conductive layer.

11. The manufacturing method according to claim 10, characterized in that: After removing the second insulating layer, the method further includes: The first insulating layer is etched to form a bit line capping layer, and the second conductive layer and the second sub-layer are etched to form a bit line layer.

12. The manufacturing method according to claim 11, characterized in that: The method further comprises: The first sub-layer not covered by the bit line layer is removed to form a bit line plug, with gaps formed on both sides of the bit line plug.

13. The manufacturing method according to claim 12, characterized in that: The method further comprises: A third insulating layer is formed, where the third insulating layer covers the top surface and sidewalls of the bit line capping layer, the sidewalls of the bit line layer, and the sidewalls of the bit line plug, and fills the gap.

14. A semiconductor structure, characterized in that The semiconductor structure is manufactured by the manufacturing method according to any one of claims 1 to 13.

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