Semiconductor devices and their fabrication methods

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes a substrate, at least one stacked layer, a first metal layer, a second metal layer, a channel structure, and a barrier layer. The stacked layer is disposed on the substrate, and the first and second metal layers are disposed on the substrate, respectively below and above the stacked layer. The channel structure is disposed on the substrate, partially overlapping the second metal layer, the stacked layer, and a portion of the first metal layer. The barrier layer is disposed within the second metal layer, wherein the barrier layer is sandwiched between the second metal layer and the channel structure, and its maximum width in the horizontal direction is greater than the maximum width of the channel structure. Therefore, the barrier layer effectively prevents the diffusion of metal ions contained in the second metal layer from contaminating the channel structure. This improves the structural reliability and performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a vertical channel structure and a method for manufacturing the same. Background Technology

[0002] Improvements in process technology, circuit design, programming algorithms, and fabrication methods can shrink planar semiconductor devices to even smaller sizes. However, as the feature size of semiconductor devices approaches its lower limit, the fabrication methods for these devices become extremely challenging and costly. Currently, the development of planar semiconductor devices has reached a bottleneck. To address the density limitations of planar semiconductor devices, three-dimensional semiconductor devices have become the mainstream development trend. Semiconductor memory devices such as 3D NAND flash memory and related fabrication processes are constantly being improved to maintain good device performance while simplifying the fabrication process. Summary of the Invention

[0003] The present invention aims to provide a semiconductor device that additionally provides a barrier layer between the channel structure and the metal layer to prevent the channel structure from directly contacting the metal layer. Thus, the barrier layer effectively prevents metal ions from diffusing from the metal layer to the channel structure and contaminating it. This improves the structural reliability and performance of the semiconductor device.

[0004] The present invention aims to provide a method for fabricating a semiconductor device, wherein a barrier layer is additionally provided between the channel structure and the metal layer to prevent the channel structure from directly contacting the metal layer. The barrier layer effectively prevents metal ions within the metal layer from diffusing and contaminating the channel structure. Thus, the resulting semiconductor device possesses optimized structural reliability and performance.

[0005] The present invention aims to provide a semiconductor device comprising a substrate, at least one stacked layer, a first metal layer and a second metal layer, a channel structure, and a barrier layer. The at least one stacked layer is disposed on the substrate. The first metal layer and the second metal layer are disposed on the substrate, respectively below and above the at least one stacked layer. The channel structure is disposed on the substrate, partially overlapping the second metal layer, the at least one stacked layer, and a portion of the first metal layer. The barrier layer is disposed within the second metal layer, wherein the barrier layer is sandwiched between the second metal layer and the channel structure, and the maximum width of the barrier layer in the horizontal direction is greater than the maximum width of the channel structure.

[0006] The present invention aims to provide a method for fabricating a semiconductor device, comprising the following steps: First, a substrate is provided, and at least one stacked layer is formed on the substrate. A first metal layer and a second metal layer are formed on the substrate, the first metal layer being located below and the second metal layer being located above the at least one stacked layer, respectively. Next, a channel structure is formed on the substrate, partially overlapping the second metal layer, the at least one stacked layer, and a portion of the first metal layer. Then, a barrier layer is formed on the substrate, the barrier layer being formed within the second metal layer, wherein the barrier layer is sandwiched between the second metal layer and the channel structure, and the maximum width of the barrier layer in the horizontal direction is greater than the maximum width of the channel structure. Attached Figure Description

[0007] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 8 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein:

[0009] Figure 1 This is a schematic cross-sectional view of a semiconductor device after a via has been formed.

[0010] Figure 2 This is a schematic cross-sectional view of a semiconductor device after the formation of a barrier material layer.

[0011] Figure 3 This is a cross-sectional view of a semiconductor device after planarization fabrication.

[0012] Figure 4 This is a schematic cross-sectional view of a semiconductor device after another via has been formed.

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor device after another barrier material layer has been formed.

[0014] Figure 6 This is a cross-sectional view of a semiconductor device after another planarization fabrication process.

[0015] Figure 7 This is a schematic cross-sectional view of a semiconductor device after the formation of a via; and

[0016] Figure 8 This is a schematic cross-sectional view of a semiconductor device after the channel structure has been formed.

[0017] Figure 9 The illustration is a schematic diagram of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0018] Figure 10 The illustration is a schematic diagram of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0019] Figure 11 The illustration is a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0020] Figure 12 The diagram shown is a schematic diagram of a semiconductor device according to a preferred embodiment of the present invention.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 100 substrate

[0023] 110 First Metal Layer

[0024] 112, 142 through holes

[0025] 114, 144 mask layers

[0026] 116, 146 Photoresist Layer

[0027] 118, 148 barrier material layers

[0028] 120 Barrier Material Layer

[0029] 122, 222 Another barrier layer

[0030] 130 stacked layers

[0031] 140 Second metal layer

[0032] 150 barrier material layers

[0033] Barrier layers 152 and 252

[0034] 160 and 260 channel holes

[0035] 162 Channel Layer

[0036] 164 Insulation Layer

[0037] 166 conductive layer

[0038] 170, 170a, 370 channel structures

[0039] 180 insulation layer

[0040] 200, 200a, 201 Semiconductor Devices

[0041] 300 Three-Dimensional NAND Storage Devices

[0042] 310-digit contact plug

[0043] 332 Conductor Layer

[0044] 334 Dielectric Layer

[0045] 362 Insulation Layer

[0046] 364 Channel Layer

[0047] 366 Insulation Layer

[0048] P1 Surface Treatment Manufacturing Process

[0049] Maximum width of W1, W2, W3 Detailed Implementation

[0050] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0051] Figures 1 to 8 The illustration is a schematic diagram of a method for fabricating a semiconductor device 200 according to a first embodiment of the present invention. First, please refer to... Figure 1 As shown, a substrate 100 is provided, which may be, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials. Those skilled in the art will readily understand that various desired semiconductor components may be further formed on or within the substrate 100 according to actual device requirements, such as transistors with the same or different conductivity types, such as P-type transistors (PMOS), N-type transistors (NMOS), memory, or interconnect structures.

[0052] Next, a first metal layer 110 is formed on the substrate 100, and a through-hole 112 is formed within the first metal layer 110 through a mask structure formed on the first metal layer 110. Specifically, the mask structure includes a mask layer 114 and a photoresist layer 116 sequentially stacked on the first metal layer 110. A patterning process is performed using the mask structure to sequentially transfer the pattern of the photoresist layer 116 onto the underlying mask layer 114 and the first metal layer 110, thereby forming the through-hole 112 within the first metal layer 110 and exposing a portion of the substrate 100. In one embodiment, the first metal layer 110 includes conductive metal materials such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), and copper (Cu), the mask layer 114 includes dielectric materials such as silicon nitride, silicon carbonitride, and silicon oxynitride, and the photoresist layer 116 includes, for example, a suitable photoresist material, but is not limited thereto.

[0053] like Figure 2 As shown, after removing the photoresist layer 116, a barrier material layer 118 is formed on the substrate 100 using a deposition process, filling the vias 112 and further covering the mask layer 114. It should be noted that the barrier material layer 118 includes, for example, a conductive material, preferably selected from the group consisting of indium aluminum zinc oxide (InAlZnO), indium tin oxide (ITO), doped indium gallium zinc oxide (IGZO), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). In this embodiment, the barrier material layer 118 may selectively have a single-layer structure or a composite layer structure, but is not limited thereto.

[0054] like Figure 3 As shown, a planarization process is performed to remove the barrier material layer 118 covering the mask layer 114, and then further remove the mask layer 114 to form a barrier material layer 120, which is located within the first metal layer 110. The top surface of the barrier material layer 120 is flush with the top surface of the first metal layer 110.

[0055] Then, as Figure 4As shown, at least one stacked layer 130, a second metal layer 140, and another mask structure are sequentially formed on the barrier material layer 120 and the first metal layer 110. A through-hole 142 is formed within the second metal layer 140 through the other mask structure. Specifically, the other mask structure includes a mask layer 144 and a photoresist layer 146 sequentially stacked on the second metal layer 140. A patterning process is performed using the other mask structure to sequentially transfer the pattern of the photoresist layer 146 onto the underlying mask layer 144 and the second metal layer 140, thereby forming the through-hole 142 within the second metal layer 140 and exposing a portion of the stacked layer 130. The through-hole 142 is formed, for example, aligned with the underlying barrier material layer 120. Figure 4 As shown.

[0056] It should be noted that the stacked layer 130 may include any suitable material and thickness. In this embodiment, although the stacked layer 130 is described as a single film layer, under actual device requirements, the stacked layer 130 may also include multiple stacked film layers. Figure 4 The examples shown are for illustrative purposes only. In addition, the second metal layer 140 may also include conductive metal materials such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper, the mask layer 144 may include dielectric materials such as silicon nitride, silicon carbonitride, and silicon oxynitride, and the photoresist layer 146 may include, for example, a suitable photoresist material, but is not limited thereto.

[0057] like Figure 5 As shown, after removing the photoresist layer 146, a barrier material layer 148 is formed on the substrate 100 using a deposition process, filling the vias 142 and further covering the mask layer 144. It should be noted that the barrier material layer 148 also includes a conductive material, preferably selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride. In one embodiment, the barrier material layer 148 and the barrier material layer 120 may include the same conductive material, but this is not a limitation. Furthermore, the barrier material layer 148 may selectively have a single-layer structure or a composite layer structure, but this is not a limitation.

[0058] like Figure 6 As shown, another planarization process is performed, removing the barrier material layer 148 covering the mask layer 144, and further removing the mask layer 144 to form a barrier material layer 150, which is located within the second metal layer 140. The top surface of the barrier material layer 150 is flush with the top surface of the second metal layer 140.

[0059] like Figure 7As shown, a channel hole 160 is formed on the substrate 100, sequentially penetrating the second metal layer 140, the stacked layer 130, and a portion of the first metal layer 110. It should be noted that the channel hole 160 is formed just through the barrier material layer 150 located in the second metal layer 140 (e.g., ...). Figure 6 (as shown) and the barrier material layer 120 located within the first metal layer 110 (as shown) Figure 6 As shown), barrier layer 152 and another barrier layer 122 can be formed simultaneously. It should be noted that barrier layer 152 and the other barrier layer 122 are located at the top and bottom of the channel hole 160, respectively, and directly contact the top and bottom surfaces of the stacked layer 130. Those skilled in the art will readily understand that, although in Figure 7 In the cross-sectional schematic diagram shown, barrier layer 152 is located on the two opposite sidewalls at the top of channel hole 160, and another barrier layer 122 is located on the two opposite sidewalls and bottom of channel hole 160. However, from a top view (not shown), barrier layer 152 should be surrounding the sidewalls of channel hole 160, while the other barrier layer 122 is integrally covering the bottom of channel hole 160, but this is not a limitation.

[0060] Then, as Figure 8 As shown, a channel structure 170 is formed, filling the channel hole 160. The channel structure 170 includes a functional layer sequentially formed on the inner wall of the channel hole 160 and a filling layer filling the remaining space of the channel hole 160. In this embodiment, the functional layer includes a channel layer 162 and an insulating layer 164 sequentially stacked on the inner wall of the channel hole 160, while the filling layer includes a conductive layer 166. The channel layer 162 includes, for example, indium aluminum zinc oxide, indium tin oxide, or other suitable conductive materials. The insulating layer 164 includes, for example, high dielectric constant dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), or titanium oxide (TiO2). The conductive layer 166 includes low resistivity metallic materials such as aluminum, titanium, copper, or tungsten, but is not limited thereto.

[0061] In this configuration, the channel structure 170 can form a vertically arranged gate structure, sequentially passing through the second metal layer 140, the stacked layer 130, and partially passing through the first metal layer 110. The channel structure 170, the first metal layer 110, and the second metal layer 140 together form a transistor. Thus, the conductive layer 166 can serve as a gate, with a vertically columnar insulating layer 164 and a channel layer 162 sequentially surrounding the outer wall of the conductive layer 166, serving as the gate dielectric layer and gate channel, respectively. This allows the gate to achieve an effect similar to a gate-all-around (GAA) gate. Furthermore, the second metal layer 140 through which the channel structure 170 passes and the first metal layer 110 through which it partially passes can respectively serve as the source / drain (S / D) of the gate. A barrier layer 152 is sandwiched between the second metal layer 140 and the channel structure 170, and another barrier layer 122 is sandwiched between the first metal layer 110 and the channel structure 170. These barrier layers can block metal ions that diffuse from the second metal layer 140 and / or the first metal layer 110 to the channel layer 162, thereby preventing contamination of the channel layer 162 of the channel structure 170.

[0062] Thus, the semiconductor device 200 of this embodiment is completed. According to the fabrication method of this embodiment, another barrier layer 122 and barrier layer 152 are additionally provided between the first metal layer 110, the second metal layer 140 and the channel structure 170 to prevent the channel layer 162 in the channel structure 170 from directly contacting the first metal layer 110 or the second metal layer 140. This can block the diffusion of metal ions from the second metal layer 140 and / or the first metal layer 110 and prevent them from contaminating the channel layer 162, thereby improving problems such as the drop in transistor start-up voltage caused by the diffusion of the metal ions. It should be noted that the material of the other barrier layer 122 and / or barrier layer 152 is selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride, to serve as a contact layer between the gate and the gate dielectric layer or as an RC reduce layer to reduce resistance-capacitance delay, sandwiched between the first metal layer 110 or the second metal layer 140 and the channel structure 170, wherein the first metal layer 110 may further surround the bottom of the channel structure 170. Thus, the semiconductor device 200 of this embodiment can have optimized structural reliability and achieve good device performance.

[0063] Furthermore, those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication method of the present invention may also have other forms, and are not limited to those described above. The following will further describe other embodiments or variations of the method for fabricating the semiconductor device of the present invention. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same aspects. In addition, the same components in the various embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0064] Please refer to Figure 9 The diagram illustrates the steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention. The overall structure of the semiconductor device in this embodiment is largely the same as that of the semiconductor device 200 in the first embodiment described above; the similarities will not be repeated here. The main difference between this embodiment and the first embodiment is that, instead of depositing a barrier material layer first, a barrier layer 252 and another barrier layer 222 are formed directly through a surface treatment process P1.

[0065] In detail, the foregoing embodiments are omitted in this embodiment. Figures 1 to 5 The steps shown directly form a first metal layer 110, a stacked layer 130, and a second metal layer 140 sequentially stacked on a substrate 100, and form a channel hole 260 penetrating the second metal layer 140, the stacked layer 130, and partially penetrating the first metal layer 110 to partially expose the surfaces of the second metal layer 140, the stacked layer 130, and the first metal layer 110, as shown. Figure 9 As shown. Then, a surface treatment process P1 is performed, such as a nitriding process, to nitrid the exposed surfaces of the second metal layer 140 and the first metal layer 110 to form a barrier layer 252 and another barrier layer 222, respectively. These are located at the top and bottom of the channel hole 260 and can directly contact the top and bottom surfaces of the stacked layer 130. It should be noted that the barrier layer 252 and the other barrier layer 222 are respectively composed of nitrides of the materials of the second metal layer 140 and the first metal layer 110. For example, if the second metal layer 140 and the first metal layer 110 are composed of metal materials such as titanium, tantalum, or tungsten, the barrier layer 252 and the other barrier layer 222 are composed of materials such as titanium nitride, tantalum nitride, or tungsten nitride, but are not limited thereto.

[0066] Thus, in subsequent manufacturing processes, the same as in the aforementioned embodiment can be formed in the channel hole 260. Figure 7The channel structure shown allows barrier layer 252 and another barrier layer 222 to be respectively sandwiched between the first metal layer 110 or the second metal layer 140 and the channel structure, preventing metal ions from the second metal layer 140 and / or the first metal layer 110 from diffusing and contaminating the channel structure. Therefore, the semiconductor device fabricated according to the method of this embodiment also possesses optimized structural reliability and achieves good device performance.

[0067] Please refer to Figure 10 The diagram illustrates the steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention. The overall structure of the semiconductor device 200a in this embodiment is largely the same as that of the semiconductor device 200 in the first embodiment described above; the similarities will not be repeated here. The main difference between this embodiment and the first embodiment is that an additional isolation layer 180 is provided between the barrier layer 152 and the channel structure 170.

[0068] In detail, in this embodiment, such a structure is formed within the second metal layer 140. Figure 6 After the barrier material layer 150 shown, an additional isolation material layer (not shown) is formed on the second metal layer 140 and the barrier material layer 150. For example, it includes a conductive material selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride, preferably including the same conductive material as the barrier material layer 150.

[0069] Thus, in the subsequent formation of such Figure 7 When the channel hole 160 is shown, the insulating material layer is partially removed to form an insulating layer 180, which is sandwiched between the subsequently formed channel structure 170 and the barrier layer 152. Herein, the insulating layer 180 further prevents metal ions from the second metal layer 140 from diffusing and contaminating the channel structure 170. The maximum width W1 of the channel structure 170 in the horizontal direction can be greater than the maximum width W2 of the barrier layer 152 in the horizontal direction, allowing the top of the channel structure 170 to partially overlap the second metal layer 140 in the vertical direction. It should be noted that in embodiments where the insulating layer 180 and the barrier layer 152 include the same conductive material, the insulating layer 180 can be considered an extension of the barrier layer 152, such that the barrier layer (including, for example, ...) Figure 10 The maximum width W1 of the barrier layer 152 and the isolation layer 180 shown is greater than the maximum width W2 of the other barrier layer 122. Therefore, the semiconductor device 200a fabricated according to the method of this embodiment can also have optimized structural reliability and achieve good device performance.

[0070] Please refer to Figure 11The diagram illustrates the steps of a method for fabricating a semiconductor device according to a fourth embodiment of the present invention. The overall structure of the semiconductor device 201 in this embodiment is largely the same as that of the semiconductor device 200 in the first embodiment described above; the similarities will not be repeated here. The main difference between this embodiment and the first embodiment is that the vertical sidewall at the top of the channel structure 170a falls within the range of the barrier layer 152.

[0071] In detail, in this embodiment, when forming the channel structure 170a, the top of the channel structure 170a is intentionally kept from contacting the second metal layer 140. Thus, the maximum width W3 of the channel structure 170a in the horizontal direction is smaller than the maximum width W2 of the barrier layer 152 in the same horizontal direction. This further prevents metal ions from the second metal layer 140 from diffusing and contaminating the channel structure 170a. Therefore, the semiconductor device 201 fabricated according to the method of this embodiment also possesses optimized structural reliability and achieves good device performance.

[0072] In general, this invention utilizes deposition or surface treatment processes to additionally create a barrier layer between the channel layer and the metal layer containing the metal material. This barrier layer prevents the channel layer from directly contacting the metal layer, thus blocking the diffusion of metal ions from the metal layer to the channel layer. This effectively prevents the channel layer from being contaminated by metal ions and improves problems such as transistor start-up voltage drop caused by metal ion diffusion. Furthermore, the material of the barrier layer can be freely selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride. It can further serve as a contact layer between the gate and the gate dielectric layer or as a buffer layer to reduce resistance-capacitance delay, enabling the semiconductor device of this invention to have optimized structural reliability and achieve good device performance.

[0073] Therefore, the fabrication method and / or semiconductor device of the present invention can be applied to semiconductor structures having vertical columnar channel layers, such as conductive pillars and plugs, to improve the structural reliability and performance of the channel layer. Please refer to... Figure 12 The diagram shown is a cross-sectional schematic of a semiconductor device according to a preferred embodiment of the present invention. In this embodiment, the semiconductor device is, for example, a three-dimensional NAND memory device 300, including a substrate 100, at least one stacked layer 130 disposed on the substrate 100, and a plurality of channel structures 370 penetrating the stacked layer structure 130.

[0074] In detail, the stacked layer 130 of this invention includes a plurality of alternating conductor layers 332 and a plurality of dielectric layers 334. Each dielectric layer 334 includes, for example, the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, while each conductor layer 332 includes, for example, the same conductive material, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, but is not limited thereto. It should be noted that any conductor layer 332 and the dielectric layer 334 above it together constitute a set of conductive-dielectric layer pairs, and the conductive-dielectric layer pairs are stacked as follows: Figure 12 The staircase structure shown serves as a memory stack structure. Thus, the three-dimensional NAND memory device 300 can be electrically connected to the word line contact plugs 310 by fan-outing each word line (i.e., each conductor layer 332) through the staircase structure on both sides.

[0075] In this embodiment, the channel structure 370 also includes a functional layer sequentially formed on the inner wall of the channel aperture (not shown) and a filling layer filling the remaining space of the channel aperture. The functional layer includes an insulating layer 362 and a channel layer 364 sequentially stacked on the inner wall of the channel aperture. The insulating layer 362 includes, for example, a dielectric material, such as a composite layer structure comprising an oxide-nitride-oxide (ONO, not shown). The channel layer 364 includes, for example, a semiconductor material, such as silicon or polysilicon, but is not limited thereto. Furthermore, the filling layer includes an insulating layer 366, which may have, for example, a dielectric material such as silicon oxide, but is not limited thereto.

[0076] In this configuration, the channel structure 370, stacked layer 130, first metal layer 110, and second metal layer 140 (serving as source and drain, respectively) can jointly form a transistor. The intersection of each channel structure 370 and each conductor layer 332 serves as a memory cell, and each conductor layer 332 serves as a word line to control the writing and reading of data in each memory cell. It should be noted that an additional barrier layer 152 and another barrier layer 122 are provided between the channel structure 370 and the first metal layer 110 and the second metal layer 140 to prevent the channel structure 370 from directly contacting the first metal layer 110 or the second metal layer 140, thus preventing the diffusion of metal ions from the second metal layer 140 and / or the first metal layer 110 and contamination of the channel layer 364. Therefore, the three-dimensional NAND memory device 300 of this embodiment also possesses a relatively reliable channel structure 370 and performance.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized by, The application relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate; at least one stack layer disposed on the substrate; a first metal layer and a second metal layer disposed on the substrate and respectively below and above the at least one stack layer; a channel structure disposed on the substrate and partially overlapping the second metal layer, the at least one stack layer, and part of the first metal layer; and a barrier layer disposed in the second metal layer, wherein the barrier layer is sandwiched between the second metal layer and the channel structure, the barrier layer has a maximum width in a horizontal direction greater than a maximum width of the channel structure, and the barrier layer is made of a material selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride.

2. The semiconductor device according to claim 1, wherein The semiconductor structure further comprises: an isolation layer disposed between the barrier layer and the channel structure.

3. The semiconductor device of claim 2, wherein, The barrier layer and the isolation layer are made of the same material.

4. The semiconductor device of claim 1, wherein The semiconductor structure further comprises: another barrier layer disposed in the first metal layer and partially overlapping a bottom portion of the channel structure.

5. The semiconductor device of claim 4, wherein, The barrier layer and the other barrier layer have different maximum widths in the horizontal direction.

6. The semiconductor device of claim 4, wherein The barrier layer and the other barrier layer directly contact the at least one stack layer.

7. The semiconductor device of claim 4, wherein The other barrier layer is made of a material selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride.

8. The semiconductor device of claim 1, wherein The channel structure comprises a functional layer and a filling layer, wherein the filling layer comprises a metal material or an insulating material.

9. The semiconductor device of claim 8, wherein, The functional layer comprises a channel layer made of indium gallium zinc oxide or indium tin oxide and an insulating layer made of a high-dielectric-constant dielectric material.

10. The semiconductor device of claim 8, wherein, The functional layer comprises an insulating layer and a channel layer made of silicon or polysilicon, and the insulating layer comprises an oxide layer-nitride layer-oxide layer.

11. A method of fabricating a semiconductor device, comprising: The manufacturing method comprises: providing a substrate; forming at least one stack layer on the substrate; forming a first metal layer and a second metal layer on the substrate, the first metal layer and the second metal layer being respectively below and above the at least one stack layer; and forming a channel structure on the substrate and partially overlapping the second metal layer, the at least one stack layer, and part of the first metal layer. The manufacturing method further comprises: forming a barrier layer on the substrate and in the second metal layer, wherein the barrier layer is sandwiched between the second metal layer and the channel structure, and the barrier layer has a maximum width in a horizontal direction greater than a maximum width of the channel structure. The manufacturing method further comprises:

12. The method of fabricating a semiconductor device according to Claim 11, wherein forming a channel hole on the substrate and penetrating the second metal layer, the at least one stack layer, and part of the first metal layer. The manufacturing method further comprises, before the channel hole is formed:

13. The method of fabricating a semiconductor device according to Claim 12, wherein forming a first barrier material layer in the second metal layer; and partially removing the first barrier material layer when the channel hole is formed to form the barrier layer. The manufacturing method further comprises, before the channel hole is formed:

14. The method of fabricating a semiconductor device according to Claim 13, wherein forming an isolation material layer on the second metal layer and the first barrier material layer; and ​ partially removing the barrier layer and the second barrier layer during formation of the via holes.

15. The method of fabricating a semiconductor device according to Claim 13, wherein The method further comprises, before the via holes are formed: forming a second barrier material layer in the first metal layer, wherein the second barrier material layer is partially removed during formation of the via holes to form another barrier layer in the first metal layer, wherein the another barrier layer overlaps with a bottom portion of the via structure.

16. The method of fabricating a semiconductor device according to Claim 15, wherein The forming of the second barrier material layer and the first barrier material layer further comprises: forming a via hole in the second metal layer and the first metal layer through a mask structure; and performing a deposition fabrication process on the substrate; and performing a planarization fabrication process to form the first barrier material layer filling the via hole in the second metal layer and the second barrier material layer filling the via hole in the first metal layer, respectively.

17. The method of fabricating a semiconductor device according to Claim 12, wherein The method further comprises, after the via holes are formed: performing a nitridation fabrication process in the via holes to partially nitride the second metal layer and the first metal layer to form the barrier layer and the another barrier layer.

18. The method of fabricating a semiconductor device according to Claim 17, wherein The barrier layer and the another barrier layer comprise nitrides of materials of the second metal layer and the first metal layer.

19. The method of fabricating a semiconductor device of claim 12, wherein, forming the via structure in the via holes after the via holes are formed, the via structure comprising a functional layer and a filling layer disposed in the via holes in sequence, wherein the filling layer comprises a metal material or an insulating material.

20. The method of fabricating a semiconductor device according to Claim 19, wherein The functional layer comprises a channel layer comprising indium gallium zinc oxide or indium tin oxide, and an insulating layer comprising a high-k dielectric material disposed between the channel layer and the filling layer.

Images