Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a substrate, a light-emitting layer located on one side of the substrate, the light-emitting layer comprising a plurality of sub-pixels, and a plurality of adjacent sub-pixels forming a repeating unit; a wiring layer located between the substrate and the light-emitting layer, the wiring layer comprising a plurality of first wires arranged at intervals along a first direction; at least part of the first wires is provided with a first partition region; at least part of the first wires is provided with a second partition region, the first wires located on both sides of the second partition region in the length direction of the first wires are electrically connected through a bridge portion, and the bridge portion is provided in a layer different from the first wires; in the first direction, a first sub-pixel in the first repeating unit covers the first partition region; a second sub-pixel in the second repeating unit covers the second partition region. The first sub-pixel and the second sub-pixel are correspondingly arranged. In the above manner, the application can reduce the large-viewing-angle color deviation.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, display panels are increasingly moving towards narrower bezels. To better achieve narrow bezels, related technologies employ FIAA (fanout in AA, i.e., fan-out within the display area) technology to lay out the data cables.

[0003] Currently, when using FIAA technology to lay out data lines, a first partition area is set below the anod of certain sub-pixels. The introduction of this first partition area causes significant differences in the anod flatness of the entire display panel, resulting in color shift at large viewing angles and affecting the display panel's display effect. Summary of the Invention

[0004] This application provides a display panel and a display device to reduce the anode flatness difference of the display panel and reduce the large viewing angle color deviation.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a display panel, comprising: a substrate; a light-emitting layer located on one side of the substrate, the light-emitting layer comprising a plurality of sub-pixels, and adjacent plurality of sub-pixels forming a repeating unit; a wiring layer located between the substrate and the light-emitting layer, the wiring layer comprising a plurality of first traces arranged at intervals along a first direction on the same layer; at least a portion of the first traces are provided with a first partition region, and the first traces located on both sides of the first partition region in the length direction of the first traces are mutually insulated; at least a portion of the first traces are provided with a second partition region, and the first traces located on both sides of the second partition region in the length direction of the first traces are electrically connected through a bridging portion, and the bridging portion is disposed on a different layer from the first traces;

[0006] In the first direction, the light-emitting layer includes a first repeating unit and a second repeating unit. The first repeating unit includes a first sub-pixel, and the second repeating unit includes a second sub-pixel. The first sub-pixel and the second sub-pixel are correspondingly disposed. The orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the first partition region on the substrate at least partially overlap. The orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the second partition region on the substrate at least partially overlap.

[0007] The first repeating unit and the second repeating unit are adjacent to each other.

[0008] In the first direction, each pair of adjacent first traces forms a first trace pair. A first trace pair passes through a plurality of sub-pixels spaced apart along its length direction. The orthographic projection of the sub-pixels on the substrate overlaps with the orthographic projection of each first trace in the first trace pair on the substrate. At least one of the first traces in a portion of the first trace pairs has the first partition area.

[0009] Preferably, one of the first traces in the same first trace pair is a signal line, and the other first trace is a virtual line, with at least a portion of the virtual line having the first isolation area.

[0010] In the first direction, the first partition area and the second partition area are symmetrically arranged.

[0011] In one of the first repeating units and the plurality of consecutively arranged second repeating units, the lengths of the plurality of second partitions at the positions of the plurality of second repeating units gradually increase in the direction pointing to the first repeating unit.

[0012] The wiring layer further includes: a plurality of second traces, which intersect with the first traces and are disposed in different layers; wherein at least a portion of the virtual lines include the first partition area, and a first sub-trace and a second sub-trace located on both sides of the first partition area; a signal line in one of the first trace pairs is electrically connected to the first sub-trace in another of the first trace pairs through one of the second traces.

[0013] The second sub-trace has a fixed potential.

[0014] The bridging section is located on the same layer as the second routing line.

[0015] The repeating units are arranged in an array along the first direction and a second direction intersecting the first direction; one repeating unit corresponds to at most one first partition area, and adjacent first partition areas are arranged along a third direction intersecting the first direction and the second direction; preferably, the second direction is parallel to the length direction.

[0016] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a display device, which includes the display panel mentioned in any of the above embodiments.

[0017] Unlike existing technologies, the beneficial effects of this application are as follows: In this application, the anode flatness of the second sub-pixel is adapted to the anode flatness adjustment of the first sub-pixel, so that the anode flatness of the second repeating unit where the second sub-pixel is located can be adapted to the anode flatness adjustment of the first repeating unit where the first sub-pixel is located. The anode flatness of the first repeating unit with the first partition area and the anode flatness of the second repeating unit will not differ significantly, so that the anode flatness of the entire display panel remains relatively consistent, improving the color shift problem at large viewing angles of the display panel and improving the uniformity of sub-pixel light emission and the consistency of in-plane display. In addition, in this application, a repeating unit composed of multiple sub-pixels is used as an adjustment unit. This design can result in a better display effect for the entire display panel. Furthermore, the second repeating unit adapted for adjustment and the first repeating unit are arranged adjacent to each other in the first direction. This method can reduce the difficulty of process fabrication and reduce the impact on the original layout of multiple first traces and multiple sub-pixels. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0019] Figure 1 This is a schematic diagram of one embodiment of the display panel;

[0020] Figure 2a for Figure 1 An enlarged schematic diagram of one embodiment of the central partial display area;

[0021] Figure 2b for Figure 1 A cross-sectional view of one embodiment at the location of section line AA in the middle;

[0022] Figure 3 This is an enlarged schematic diagram of one embodiment of a partial display area of ​​this application;

[0023] Figure 4 This is an enlarged schematic diagram of one embodiment of the partial display area of ​​this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] like Figure 1 As shown, Figure 1 This is a schematic diagram of one embodiment of a display panel. The display panel can be an OLED display panel, a Micro-LED display panel, etc.; it generally includes a display area AA and a non-display area CC located around the display area AA, and a bonding area CC1 is provided in the non-display area CC. Generally, fan-out lines connected to data lines in the display panel can... Figure 1 The non-display areas CC on the left and right sides extend into the bonding area CC1. Obviously, this fan-out method will occupy the non-display areas CC on the left and right sides, which is not conducive to reducing the width of the non-display areas CC on the left and right sides, that is, it is not conducive to narrow bezels.

[0026] To reduce the narrow bezel, FIAA technology was developed. Its main approach is to lay out at least a portion of the fan-out lines connected to at least a portion of the data lines in a specific layout. Figure 1 The display area AA in the text. Specifically, as shown... Figure 2a and Figure 2b As shown, Figure 2a for Figure 1 An enlarged schematic diagram of one embodiment of the central partial display area. Figure 2b for Figure 1 A cross-sectional view of one embodiment at the AA section line. The display panel includes a substrate 14 ( Figure 2a (Not shown in the diagram) A light-emitting layer 10 located on one side of the substrate 14, and a wiring layer 12 located between the substrate 14 and the light-emitting layer 10; that is, the display panel includes a substrate 14, a wiring layer 12 and a light-emitting layer 10 stacked in sequence.

[0027] The light-emitting layer 10 includes multiple sub-pixels 100, such as Figure 2a As shown, the sub-pixel 100 can be a red sub-pixel R, a blue sub-pixel B, or a green sub-pixel G. Optionally, as... Figure 2b As shown, the light-emitting layer 10 also includes a pixel definition layer 106, which has multiple openings (not shown), and each opening corresponds to a sub-pixel 100. Furthermore, the display panel provided in this application also includes an anode 16, located on the side of the pixel definition layer 106 facing the substrate 14, and the orthographic projection of the sub-pixel 100 onto the anode 16 is located within the anode 16. The flatness of the anode 16, which is in direct contact with the sub-pixel 100, will affect the large viewing angle color shift of the display panel.

[0028] like Figure 2aAs shown, the wiring layer 12 includes a plurality of first traces 120 spaced apart along a first direction X, and at least a portion of the first traces 120 have a first partition region 1200 in their length direction Y, and the first traces 120 located on both sides of the first partition region 1200 in the length direction X of the first traces 120 are mutually insulated. Optionally, the orthographic projection of the sub-pixel 100 on the substrate 14 overlaps with the orthographic projection of the first trace 120 on the substrate 14. Alternatively, in the first direction X, every two adjacent first traces 120 form a first trace pair 122, and the orthographic projection of a first trace pair 122 on the light-emitting layer 10 can pass through a plurality of sub-pixels 100 spaced apart along its length direction Y, and the orthographic projection of the sub-pixel 100 on the substrate 14 overlaps with the orthographic projection of each first trace 120 in the first trace pair 122 on the substrate 14; and at least a portion of the first traces 120 in the first trace pair 122 has a first partition region 1200.

[0029] In this configuration, one of the first traces 120 in the first trace pair 122 can be considered a signal line 120a, such as a data line, while the other first trace 120 can be considered a virtual line 120b. At least a portion of the virtual line 120b has a first partition region 1200. The signal line 120a can be electrically connected to the pixel driving circuits of the multiple sub-pixels 100 that it passes through in the length direction Y. The virtual line 120b serves a fan-out function, etc. Optionally, in the first direction X, the multiple first traces 120 are arranged alternately and sequentially in the manner of virtual lines 120b and signal lines 120a to reduce the difficulty of fabrication.

[0030] In addition to multiple first traces 120, wiring layer 12 also includes multiple second traces 124, with the second traces 124 intersecting the first traces 120. The second traces 124 and first traces 120 are located on different layers; for example, the extension direction of the second traces 124 is parallel to the first direction X. These second traces 124 primarily function as fan-out traces. For example, as... Figure 2a As shown, Figure 2a The diagram illustrates three signal channels, each represented by a bold line. At least a portion of the virtual line 120b, which has a first isolation zone 1200, passes through a portion of the second wiring 124 and then connects to the signal line 120a. This method is known as FIAA technology.

[0031] like Figure 2aAs shown, a portion of the virtual line 120b includes a first sub-trace 1202 and a second sub-trace 1204 spaced apart along its length direction Y, with only the first sub-trace 1202 serving a fan-out function. Considering factors such as the overall anode flatness of the display panel and the difficulty of the manufacturing process, the aforementioned second sub-trace 1204, which does not serve a fan-out function, is retained in the display panel, thus forming the first partition area 1200. To reduce electrical floating and ensure display quality, the second sub-trace 1204 can be assigned a fixed potential, such as the power supply voltage VDD or VSS.

[0032] Furthermore, the first partition area 1200 is generally located below the sub-pixel 100. The arrangement of multiple first partition areas 1200 is irregular. The first partition area 1200 will cause the anod flatness at the corresponding sub-pixel 100 position to differ significantly from the surrounding anod flatness. The display panel will have a large viewing angle deviation problem due to the large difference in anod flatness.

[0033] To solve the above technical problems, such as Figure 3 As shown, Figure 3 This is an enlarged schematic diagram of a partial display area embodiment of this application. In this application, multiple adjacent sub-pixels 100 constitute a repeating unit 102. Generally, multiple sub-pixels 100 of different colors can constitute a pixel, and a repeating unit 102 can contain at least one pixel; for example, Figure 3 In a pixel, an adjacent blue sub-pixel B, a red sub-pixel R, and two green sub-pixels G constitute a pixel, and two adjacent pixels constitute a repeating unit 102. In the first direction X, the light-emitting layer 10 includes a first repeating unit 102a and a second repeating unit 102b. The first repeating unit 102a includes a first sub-pixel 100a, and the second repeating unit 102b includes a second sub-pixel 100b. The first sub-pixel 100a and the second sub-pixel 100b are correspondingly configured. This corresponding configuration can be understood as follows: the first sub-pixel 100a and the second sub-pixel 100b have the same light-emitting color and shape, and the position of the first sub-pixel 100a in the first repeating unit 102a is the same as the position of the second sub-pixel 100b in the second repeating unit 102b. For example, Figure 3 If the first sub-pixel 100a is located at the lower right corner of the corresponding first repeating unit 102a, then the corresponding second sub-pixel 100b is also located at the lower right corner of the corresponding second repeating unit 102b.

[0034] Furthermore, the orthographic projection of the first sub-pixel 100a in the first repeating unit 102a onto the substrate 14 at least partially overlaps with the orthographic projection of the first partition region 1200 onto the substrate 14; the anode flatness of the second sub-pixel 100b is adapted to the anode flatness adjustment of the first sub-pixel 100a. Specifically, at least a portion of the first trace 120 is provided with a second partition region (not shown), and the first traces 120 located on both sides of the second partition region in the length direction Y of the first trace 120 are electrically connected by a bridging portion 1208, and the bridging portion 1208 is disposed on a different layer from the first trace 120. For example, at least one first trace 120 includes two body portions 1206 spaced apart and a bridging portion 1208 bridging the two body portions 1206, and the two body portions 1206 are electrically connected by the bridging portion 1208; wherein, the body portions 1206 and the bridging portion 1208 are disposed on a different layer. For example, the bridging portion 1208 can be disposed on the same layer as the second trace 124 to reduce the difficulty of fabrication. Furthermore, the second sub-pixel 100b in the second repeating unit 102b covers the aforementioned second partition area (that is, covers the bridging portion 1208), meaning that the orthographic projection of the second sub-pixel 100b on the substrate 14 and the orthographic projection of the second partition area (or bridging portion 1208) on the substrate 14 at least partially overlap.

[0035] This design method allows for the interruption and replacement of at least one first trace 120 at the corresponding second sub-pixel 100b position without altering the overall layout of the original light-emitting layer 10 and wiring layer 12. This reduces manufacturing complexity while maintaining relatively consistent anodized flatness across the entire display panel. In summary, in this design, the anodized flatness of the second sub-pixel 100b adapts to the adjustment of the anodized flatness of the first sub-pixel 100a, ensuring that the anodized flatness of the second repeating unit 102b containing the second sub-pixel 100b adapts to the adjustment of the anodized flatness of the first repeating unit 102a containing the first sub-pixel 100a. The anodized flatness of the first repeating unit 102a with the first partition area 1200 does not differ significantly from that of the second repeating unit 102b, thus maintaining relatively consistent anodized flatness across the entire display panel. This improves the large-viewing-angle color shift problem of the display panel and enhances the uniformity of sub-pixel light emission and in-plane display consistency. Furthermore, in this application, a repeating unit 102 composed of multiple sub-pixels is used as an adjustment unit. This design can improve the display effect of the entire display panel. Moreover, the second repeating unit 102b adapted for adjustment and the first repeating unit 102a are arranged adjacent to each other in the first direction X. This method can reduce the difficulty of process fabrication and reduce the impact on the original layout of multiple first traces 120 and multiple sub-pixels 100.

[0036] Optionally, by using the above-described interruption and line-changing method, the difference between the anode flatness of the second sub-pixel 100b and the anode flatness of the first sub-pixel 100a can be greater than or equal to 0 micrometers and less than or equal to 1 micrometer. For example, the difference can be 0.2 micrometers, 0.5 micrometers, 0.7 micrometers, etc. This method of setting the difference can, under the conditions of existing manufacturing processes, make the flatness of adjacent repeating units 102 as similar as possible, so as to keep the anode flatness relatively consistent throughout the entire display panel.

[0037] Alternatively, such as Figure 3 As shown, the first repeating unit 102a and the second repeating unit 102b are arranged adjacent to each other. This design allows the display effects of multiple adjacent repeating units 102 to be similar, reducing color shift. Of course, in other embodiments, the first repeating unit 102a and the second repeating unit 102b can also be arranged at intervals in the first direction X, as long as the interval distance is not too far.

[0038] Optionally, multiple repeating units 102 are arranged in an array along a first direction X and a second direction Y1 intersecting the first direction X; one repeating unit 102 corresponds to at most one first partition region 1200, and adjacent multiple first partition regions 1200 are arranged along a third direction Z intersecting the first direction X and the second direction Y1. Optionally, the second direction Y1 is parallel to the length direction Y. The arrangement of the adjacent multiple first partition regions 1200 along the third direction Z facilitates the arrangement of the second trace 124 electrically connected to the first trace 120 corresponding to the first partition region 120.

[0039] Alternatively, such as Figure 3 As shown by the two rectangular dashed boxes, the number of second sub-pixels 100b adjusted to accommodate the current first sub-pixel 100a is one. At this time, in the first direction X, the bridging portion 1208 and the first partition area 1200 are symmetrically positioned on the substrate in the two first trace pairs 122 passing through the first sub-pixel 100a and the second sub-pixel 100b. This symmetry is not only reflected in their positional symmetry but also in the fact that the bridging portion 1208 and the first partition area 1200 extend to the same length in the length direction Y. This design allows for more consistent anode flatness among adjacent repeating units 102, resulting in similar display effects. For example, as... Figure 3 As shown, within the same rectangular dashed frame, the first partition area 1200 is located on the first trace 120 on the left side of the corresponding first trace pair 122, while the bridging part 1208 is located on the first trace 120 on the right side of the corresponding first trace pair 122.

[0040] Of course, in other embodiments, the number of second sub-pixels 100b that are adapted to the adjustment of the current first sub-pixel 100a can also be two. In this case, there are multiple second repeating units 102b in the first direction X. For example, a second repeating unit 102b is provided on the left and right sides of the first repeating unit 102a respectively. Then, there is a second sub-pixel 100b on the left and right sides of the first sub-pixel 100a respectively, and one of the first traces 120 at the position of each second sub-pixel 100b is configured to have a bridging portion 1208.

[0041] Another option, such as Figure 3 As shown, in the first direction X, the orthographic projection of each first trace 120 in the first trace pair 122 onto the sub-pixel 100 at least partially coincides with the sub-pixel 100. For example, the center point of the first trace pair 122 coincides with the center point of the corresponding sub-pixel 100. This design can reduce the flatness difference between adjacent repeating units 102, resulting in better display performance.

[0042] In another implementation, please refer to Figure 4 , Figure 4 This is an enlarged schematic diagram of a partial display area embodiment of this application. When the number of second repeating units 102b is multiple (e.g., Figure 4 (Two are shown in the diagram). When multiple second repeating units 102b are consecutively arranged on one side of the first repeating unit 102a, the length of the bridging portion 1208 (i.e., the second partition area) at the position of the multiple second repeating units 102b gradually increases in the length direction Y in the direction pointing towards the first repeating unit 102a. This design can reduce the abrupt flatness of the first sub-pixel 100a relative to the surrounding second sub-pixels 100b caused by the introduction of the first partition area 1200, so that the anodized flatness of the entire display panel can be approximately consistent, reducing the probability of large viewing angle color deviation.

[0043] Preferably, the length of the bridging portion 1208 (i.e. the second partition region) at the position of the second sub-pixel 100b at the position of the plurality of second repeating units 102b in the length direction Y is less than or equal to the length of the first partition region 1200 at the position of the first sub-pixel 100a of the first repeating unit 102a in the length direction Y.

[0044] In addition, this application also provides a display device, which includes the display panel mentioned in any of the above embodiments, and the display device can be a mobile phone, television, etc.

[0045] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A light-emitting layer is located on one side of the substrate. The light-emitting layer includes multiple sub-pixels, and multiple adjacent sub-pixels form a repeating unit. A wiring layer is located between the substrate and the light-emitting layer. The wiring layer includes a plurality of first traces arranged at intervals along a first direction in the same layer. At least a portion of the first traces are provided with a first partition region, and the first traces located on both sides of the first partition region in the length direction of the first traces are mutually insulated. At least a portion of the first traces are provided with a second partition region, and the first traces located on both sides of the second partition region in the length direction of the first traces are electrically connected by a bridging portion, and the bridging portion is disposed on a different layer from the first traces. In the first direction, the light-emitting layer includes a first repeating unit and a second repeating unit. The first repeating unit includes a first sub-pixel, and the second repeating unit includes a second sub-pixel. The first sub-pixel and the second sub-pixel are correspondingly disposed. The orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the first partition region on the substrate at least partially overlap. The orthographic projection of the second sub-pixel on the substrate and the orthographic projection of the second partition region on the substrate at least partially overlap. The wiring layer further includes: a plurality of second traces, which intersect with the first traces and are disposed on different layers. The bridging portion is disposed on the same layer as the second traces. In the first direction, each pair of adjacent first traces constitutes a first trace pair. A first trace pair passes through a plurality of sub-pixels spaced apart along its length direction, and the orthographic projection of the sub-pixels on the substrate overlaps with the orthographic projection of each first trace in the first trace pair on the substrate. At least one of the first traces in a portion of the first trace pairs has the first isolation region. One of the first traces in the same first trace pair is a signal line, and the other first trace is a virtual line. At least a portion of the virtual line has the first isolation region. At least a portion of the virtual line includes the first isolation region, and first and second sub-traces located on both sides of the first isolation region. The signal line in one of the first trace pairs is electrically connected to the first sub-traces in another first trace pair through one of the second traces. The difference between the anode flatness of the second sub-pixel and the anode flatness of the first sub-pixel is less than or equal to 1 micrometer.

2. The display panel according to claim 1, characterized in that, The first repeating unit and the second repeating unit are adjacent to each other.

3. The display panel according to claim 1, characterized in that, In the first direction, the first partition area and the second partition area are arranged symmetrically to each other.

4. The display panel according to claim 1 or 2, characterized in that, In one of the first repeating units and a plurality of consecutively arranged second repeating units, the lengths of the plurality of second partitions at the positions of the plurality of second repeating units gradually increase in the direction pointing to the first repeating unit.

5. The display panel according to claim 1, characterized in that, The second sub-trace has a fixed potential.

6. The display panel according to claim 1, characterized in that, The multiple repeating units are arranged in an array along the first direction and a second direction intersecting the first direction; one repeating unit corresponds to at most one first partition area, and the multiple adjacent first partition areas are arranged along a third direction intersecting the first direction and the second direction.

7. The display panel according to claim 6, characterized in that, The second direction is parallel to the length direction.

8. A display device, characterized in that, The display panel comprising any one of claims 1-7.

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