Display module and display device

Abstract

The application discloses a display module and a display device, and relates to the technical field of display. At least one chip set (20) and a group of first PLG wires (30) corresponding to each chip set (20) are arranged in a first binding area (121). Each chip set (20) comprises at least two groups of chip units (21), each group of chip units (21) comprises at least one gate drive chip (211), each group of first PLG wires (30) comprises a first wire (31) and at least one second wire (32), the power supply pins of any two adjacent gate drive chips (211) are connected through the first wire (31), each second wire (32) passes through each gate drive chip (211), and the first wire (31) connected to the power supply pin of the last gate drive chip (211) in the last group of chip units (21) is connected in parallel with any second wire (32) and is connected to the power supply pin of the first gate drive chip (211) in the next group of chip units (21), so that the brightness difference of the pixels driven by the gate drive chips (211) in each group of chip units (21) is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display module and a display device. BACKGROUND

[0002] In the display device, in view of the problems of narrow frame and cost reduction of the display panel, the gate driving chip is not provided with a separate PCB (Printed Circuit Board), but a PLG (Propel Link Gate) trace is arranged in the display panel, an input end of the PLG trace is connected with a power signal end on the side of the DP (Data Pad), and the power signal input by the power signal end is provided to each gate driving chip through the PLG trace. SUMMARY

[0003] Some embodiments of the present disclosure provide the following technical solutions:

[0004] In a first aspect, a display module is provided, comprising: a display panel, the display panel comprising a display area and a non-display area surrounding the display area, the non-display area comprising a first binding area located on at least one side of the display area;

[0005] At least one chip group and a group of first PLG traces corresponding to each chip group are arranged in the first binding area on each side; each chip group comprises at least two groups of chip units, and each group of chip units comprises at least one gate driving chip; each group of first PLG traces comprises a first trace and at least one second trace, and the input end of the first trace and each second trace is connected with the same power signal end.

[0006] Wherein, the power pins of any two adjacent gate driving chips are connected through the first trace, and each second trace passes through each gate driving chip; and from the direction close to the power signal end to the direction away from the power signal end, the first trace connected with the power pin of the last gate driving chip in the previous group of chip units and any one second trace are connected in parallel to the power pin of the first gate driving chip in the next group of chip units.

[0007] In a second aspect, a display device is provided, comprising the display module described above.

[0008] In the embodiment of the present application, by dividing the chip set into at least two groups of chip units, and connecting the first wire connected to the power pin of the last gate drive chip in the previous group of chip units and any one of the second wires in parallel to the power pin of the first gate drive chip in the next group of chip units, the wire resistance between each gate drive chip in each group of chip units is more balanced, therefore, the voltage difference of the power supply signal provided to each gate drive chip in each group of chip units is reduced, and the brightness difference of the pixels driven by the gate drive chips in each group of chip units is also reduced, thereby reducing the display horizontal lines of the display panel.

[0009] The above description is only a summary of the technical solutions of the present disclosure, in order to more clearly understand the technical means of the present disclosure, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following specific embodiments of the present disclosure are listed. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0011] Figure 1 The structure of a display module according to an embodiment of the present application is schematically shown;

[0012] Figure 2 The connection between the first gate drive chip and the first PLG wire is schematically shown;

[0013] Figure 3 The connection between the second gate drive chip and the first PLG wire is schematically shown;

[0014] Figure 4 The connection between the third gate drive chip and the first PLG wire is schematically shown;

[0015] Figure 5 The connection between the fourth gate drive chip and the first PLG wire is schematically shown; Figure 2 The equivalent circuit diagram corresponding to the wiring mode shown;

[0016] Figure 6 The connection between the fourth gate drive chip and the first PLG wire is schematically shown; Figure 3 The equivalent circuit diagram corresponding to the wiring mode shown;

[0017] Figure 7 The connection between the fourth gate drive chip and the first PLG wire is schematically shown; Figure 4The wiring mode shown corresponds to an equivalent circuit diagram;

[0018] Figure 8 A structural schematic diagram of the first COF is schematically shown;

[0019] Figure 9 A connection diagram of the touch display driving chip and the data line and the touch signal line is schematically shown;

[0020] Figure 10 A pin distribution diagram of the first touch display driving chip is schematically shown;

[0021] Figure 11 A pin distribution diagram of the second touch display driving chip is schematically shown;

[0022] Figure 12 A pin distribution diagram of the third touch display driving chip is schematically shown. EMBODIMENTS

[0023] In order to make the objectives, technical solutions, and superiorities of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.

[0024] In the related art, the PLG wiring only includes one wire, and the input end of the PLG wiring is connected with the power signal end on the DP side. The power signal input from the power signal end is sequentially provided to each gate driving chip through the PLG wiring.

[0025] Since the PLG wiring has resistance, there is a large voltage drop from the input end to the far end of the PLG wiring, so that the power signal provided through the PLG wiring is attenuated. In a large-size display panel, the distances of each gate driving chip to the power signal end are different, so the lengths of the PLG wiring used when each gate driving chip is connected with the power signal end are different. Therefore, the voltage values of the power signal provided to each gate driving chip through the PLG wiring are different, and the power signal is a low-level power signal VGL. Moreover, the voltage value of the power signal affects the gate low-level signal output by the gate driving chip, and the gate low-level signal affects the brightness of the pixels in the display area. Therefore, when the voltage values of the power signal provided to each gate driving chip are different, the brightness of the pixels driven by each gate driving chip is different, thereby causing display horizontal lines.

[0026] Therefore, the application divides the chip group into at least two chip units, and the first wire connected to the power pin of the last gate drive chip in the previous chip unit and any second wire are connected in parallel to the power pin of the first gate drive chip in the next chip unit, so that the wire resistance between the gate drive chips in each chip unit is more balanced, the voltage difference of the power supply signal provided to the gate drive chips in each chip unit is reduced, and the brightness difference of the pixels driven by the gate drive chips in each chip unit is also reduced, thereby reducing the display horizontal lines of the display panel.

[0027] Referring to Figure 1 , a structure schematic diagram of a display module of an embodiment of the application is shown, Figure 2 , a connection schematic diagram of a first gate drive chip and a first PLG wire is shown, Figure 3 , a connection schematic diagram of a second gate drive chip and a first PLG wire is shown, Figure 4 , a connection schematic diagram of a third gate drive chip and a first PLG wire is shown.

[0028] An embodiment of the application provides a display module, as shown in Figure 1 , the display module comprises a display panel 10, the display panel 10 comprises a display area 11 and a non-display area surrounding the display area 11, and the non-display area comprises a first binding area 121 located on at least one side of the display area 11.

[0029] As shown in Figures 2 to 4 , at least one chip group 20 and a group of first PLG wires 30 corresponding to each chip group 20 are arranged in the first binding area 121 of each side; each chip group 20 comprises at least two chip units 21, each chip unit 21 comprises at least one gate drive chip 211; each group of first PLG wires 30 comprises a first wire 31 and at least one second wire 32, and the input ends of the first wire 31 and each second wire 32 are connected to the same power signal end; wherein the power pins of any two adjacent gate drive chips 211 are connected through the first wire 31, and each second wire 32 passes through each gate drive chip 211; and from the direction close to the power signal end to the direction away from the power signal end, the first wire 31 connected to the power pin of the last gate drive chip 211 in the previous chip unit 21 and any second wire 32 are connected in parallel to the power pin of the first gate drive chip 211 in the next chip unit 21.

[0030] In the actual product, the display panel 10 includes a display area 11 and a non-display area surrounding the display area 11, the display area 11 is provided with a plurality of pixel units, each pixel unit includes a plurality of sub-pixels; and the non-display area includes at least one first binding area 121 located on the opposite side of the display area 11, as shown in Figure 1 The non-display area includes two first binding areas 121, which are respectively located on the opposite sides of the display area 11, and in fact, the two first binding areas 121 are respectively located on the GP side and the GPO side of the display area 11. The GP side refers to the Gate Pad side, that is, the side of the gate line crimping area (such as the left side in Figure 1 ), and the GPO side refers to the Gate Pad Opposite side, that is, the opposite side of the gate line crimping area (such as the right side in Figure 1 ). Of course, the non-display area can also include only one first binding area 121 located on either side of the display area 11, that is, the first binding area 121 can be located on the GP side or the GPO side of the display area 11.

[0031] For each first binding area 121, at least one chip set 20 and a group of first PLG wires 30 corresponding to each chip set 20 are provided, that is, the chip set 20 and the first PLG wire 30 are one-to-one corresponding; each chip set 20 includes at least two groups of chip units 21, and each group of chip units 21 includes at least one gate drive chip 211. As shown in Figure 2 Each first binding area 121 is provided with one chip set 20 and a group of first PLG wires 30, each chip set 20 includes four groups of chip units 21, and each group of chip units 21 includes two gate drive chips 211; as shown in Figure 3 and Figure 4 Each first binding area 121 is provided with two chip sets 20 and two groups of first PLG wires 30, each chip set 20 includes four groups of chip units 21, and each group of chip units 21 includes one gate drive chip 211.

[0032] And each group of first PLG wires 30 includes a first wire 31 and at least one second wire 32, as shown in Figures 2 to 4 Each group of first PLG wires 30 includes one first wire 31 and three second wires 32. The input end of the first wire 31 and each second wire 32 is connected with the same power signal end, which refers to the low-level power signal end, and the first signal line 31 and the second signal line 32 extend in the direction away from the power signal end.

[0033] The power supply pins of any two adjacent gate drive chips 211 are connected by the first wire 31, the power supply pin of the gate drive chip 211 refers to the low-level power supply pin, the low-level power supply signal end inputs the low-level power supply signal VGL to the low-level power supply pin of each gate drive chip 211 through the first wire 31; and each second wire 32 passes through each gate drive chip 211, that is, each second wire 32 has no connection relationship with each gate drive chip 211.

[0034] And, from the direction from the power supply signal end close to the power supply signal end, the first wire 31 connected to the power supply pin of the last gate drive chip 211 in the last chip unit 21 is connected in parallel to any one second wire 32 and is connected to the power supply pin of the first gate drive chip 211 in the next chip unit 21.

[0035] Because the first PLG wire in the related art has a voltage drop from the direction from the power supply signal end close to the power supply signal end, the voltage value of the power supply signal provided to each gate drive chip is greatly different, thereby causing the display horizontal line problem. Therefore, when the first wire 31 connected to the last chip unit 21 is connected in parallel to any one second wire 32 and is connected to the first chip unit 21, the wire resistance between each gate drive chip 211 in each chip unit 21 is more balanced, therefore, the voltage value of the power supply signal provided to each gate drive chip 211 in each chip unit 21 is reduced, and the brightness difference of the pixels driven by the gate drive chip 211 in each chip unit 21 is also reduced, thereby reducing the display horizontal line of the display panel 10.

[0036] It should be noted that the first PLG wire 30 described above only refers to the PLG wire for transmitting the low-level power supply signal VGL; in the actual product, there are other PLG wires connected to the gate drive chip 211 in the first binding area 121, such as the PLG wire for transmitting the timing control signal, but the voltage drop of these PLG wires will not affect the brightness of the pixels, therefore, these PLG wires only include one wire, and each gate drive chip 211 is connected in series, only the first PLG wire 30 in the embodiment of the application needs to include one first wire 21 and at least one second wire 32, and the first wire 31 connected to the power supply pin of the last gate drive chip 211 in the last chip unit 21 is connected in parallel to any one second wire 32 and is connected to the power supply pin of the first gate drive chip 211 in the next chip unit 21, so as to reduce the resistance of the first wire 31 after parallel connection.

[0037] In the actual product, the gate drive chip 211 is connected with the gate line connected with each row of sub-pixels in the display area 11, and provides a gate signal to the gate line. When the non-display area includes the first binding area 121 located on the opposite sides of the display area 11, and each first binding area 121 is provided with the gate drive chip 211, the same gate line is connected with the gate drive chip 211 located in the two first binding areas 121 respectively, that is, the same gate line is driven by the gate drive chip 211 located in the two first binding areas 121.

[0038] In addition, the first PLG wire 30 is made of the same material as the gate layer in the display area 11, and is formed at the same time by using the same patterning process. The gate layer in the display area 11 includes the gate line, the gate of the transistor, etc.

[0039] In an optional embodiment of the present application, as shown in Figure 1 and Figure 2 , one chip set 20 and a group of first PLG wires 30 are arranged in each first binding area 121 on one side. The non-display area further includes a second binding area 122 located on any one of the opposite sides of the display area 11, the side where the second binding area 122 is located is adjacent to the side where the first binding area 121 is located, and the power signal end connected with the first PLG wire 30 is located in the second binding area 122.

[0040] At this time, the non-display area includes the second binding area 122 located on any one of the opposite sides of the display area 11. The second binding area 122 can be located on the DP side of the display area 11 or the DPO side of the display area 11. The DP side refers to the Data Pad side, that is, the side of the data line crimping area (such as the lower side in Figure 1 ), and the DPO side refers to the opposite side of the Data Pad side, that is, the opposite side of the data line crimping area (such as the upper side in Figure 1 ).

[0041] Specifically, the PCB is arranged in the second binding area 122 on the DP side or the second binding area 122 on the DPO side, and the first PLG wire 30 is connected with the PCB through the gold finger. Therefore, the power signal end connected with the first PLG wire 30 is provided by the PCB arranged in the second binding area 122.

[0042] Next, the connection relationship between the gate drive chip 211 and the first PLG wire 30 will be introduced by taking a large-size display panel with a resolution of 3840*2160 as an example. At this time, the power signal end connected with the first PLG wire 30 is located in the second binding area 122 on the DP side.

[0043] The channel number of the gate drive chip 211 capable of driving the large-size display panel is less than or equal to 270, the display panel with a resolution of 3840*2160 is driven by 16 gate drive chips 211, 8 gate drive chips 211 are arranged in each first binding area 121 on each side, and each gate drive chip 211 can drive 270 gate lines. Therefore, each chip group 20 is divided into 4 chip units 21, each chip unit 21 includes 2 gate drive chips 211, and each first PLG wire 30 includes 1 first wire 31 and 3 second wires 32.

[0044] The 3 second wires 32 are sequentially referred to as a VGL wire 1, a VGL wire 2 and a VGL wire 3, the VGL wire 3 is the second wire 32 closest to the first wire 31, the VGL wire 1 is the second wire 32 farthest from the first wire 31, and the VGL wire 2 is located between the VGL wire 1 and the VGL wire 3; and in the direction from the DP side to the DPO side, the 8 gate drive chips 211 are respectively a gate drive chip 1 (IC1), a gate drive chip 2 (IC2), a gate drive chip 3 (IC3), a gate drive chip 4 (IC4), a gate drive chip 5 (IC5), a gate drive chip 6 (IC6), a gate drive chip 7 (IC7) and a gate drive chip 8 (IC8), the gate drive chip 1 and the gate drive chip 2 are a chip unit 21, the gate drive chip 3 and the gate drive chip 4 are a chip unit 21, the gate drive chip 5 and the gate drive chip 6 are a chip unit 21, and the gate drive chip 7 and the gate drive chip 8 are a chip unit 21.

[0045] The input ends of the first wire 31, the VGL wire 1, the VGL wire 2 and the VGL wire 3 are connected with the same power supply signal end, the first wire 31 is further connected with the power supply pin of the gate drive chip 1, the gate drive chip 1 is driven by the power supply signal provided by the first wire 31, and the VGL wire 1, the VGL wire 2 and the VGL wire 3 pass through the gate drive chip 1 without being connected with the power supply pin of the gate drive chip 1; then, the first wire 31, the VGL wire 1, the VGL wire 2 and the VGL wire 3 passing through the gate drive chip 1 reach the position of the gate drive chip 2 after a distance, the first wire 31 continues to be connected with the power supply pin of the gate drive chip 2, the gate drive chip 2 is driven by the power supply signal provided by the first wire 31, and the VGL wire 1, the VGL wire 2 and the VGL wire 3 continue to pass through the gate drive chip 2.

[0046] The first wire 31, the VGL wire 1, the VGL wire 2 and the VGL wire 3 pass through the gate drive chip 2, wherein the VGL wire 3 is connected in parallel with the first wire 31 to form a first wire 31 after first parallel connection, at this time, the first PLG wire 30 only remains 3 wires, the first wire 31 after first parallel connection, the VGL wire 1 and the VGL wire 2 pass through a distance to reach the position of the gate drive chip 3, the first wire 31 after first parallel connection is connected with the power pin of the gate drive chip 3, the gate drive chip 3 is driven by the power signal provided by the first wire 31 after first parallel connection, and the VGL wire 1 and the VGL wire 2 pass through the gate drive chip 3; then, the first wire 31 after first parallel connection, the VGL wire 1 and the VGL wire 2 passing through the gate drive chip 3 pass through a distance to reach the position of the gate drive chip 4, the first wire 31 after first parallel connection continues to be connected with the power pin of the gate drive chip 4, the gate drive chip 4 is driven by the power signal provided by the first wire 31 after first parallel connection, and the VGL wire 1 and the VGL wire 2 continue to pass through the gate drive chip 4.

[0047] The first wire 31 after first parallel connection, the VGL wire 1 and the VGL wire 2 pass through the gate drive chip 4, wherein the VGL wire 2 is connected in parallel with the first wire 31 after first parallel connection again to form a second wire 31 after second parallel connection, at this time, the first PLG wire 30 only remains 2 wires, the second wire 31 after second parallel connection and the VGL wire 1 pass through a distance to reach the position of the gate drive chip 5, the second wire 31 after second parallel connection is connected with the power pin of the gate drive chip 5, the gate drive chip 5 is driven by the power signal provided by the second wire 31 after second parallel connection, and the VGL wire 1 passes through the gate drive chip 5; then, the second wire 31 after second parallel connection and the VGL wire 1 passing through the gate drive chip 5 pass through a distance to reach the position of the gate drive chip 6, the second wire 31 after second parallel connection continues to be connected with the power pin of the gate drive chip 6, the gate drive chip 6 is driven by the power signal provided by the second wire 31 after second parallel connection, and the VGL wire 1 continues to pass through the gate drive chip 6.

[0048] After the second parallel connection, the first trace 31 and VGL trace 1 pass through the gate driver chip 6. VGL trace 1 and the first trace 31 after the second parallel connection are connected in parallel again to form a first trace 31 after the third parallel connection. At this time, only one trace remains in the first PLG trace 30. The first trace 31 after the third parallel connection reaches the position of the gate driver chip 7 after a certain distance and is connected to the power supply pin of the gate driver chip 7. The gate driver chip 7 is driven by the power signal provided by the first trace 31 after the third parallel connection. Then, the first trace 31 after the third parallel connection passes through the gate driver chip 7 and reaches the position of the gate driver chip 8 after a certain distance. The first trace 31 after the third parallel connection continues to be connected to the power supply pin of the gate driver chip 8. The gate driver chip 8 is driven by the power signal provided by the first trace 31 after the third parallel connection.

[0049] From the above analysis, it can be seen that, Figure 2 The equivalent circuit diagram corresponding to the wiring method shown is as follows: Figure 5 As shown, assuming the trace resistance of the first PLG trace 30 from the power signal terminal to the gate driver chip 1, and the first PLG trace 30 between two adjacent gate driver chips are both R, then the trace resistance of the first trace 31 connected to the power pin of the gate driver chip 1 is R, and the trace resistance of the first trace 31 connected to the power pin of the gate driver chip 2 becomes 2R. Since the VGL trace 3 is connected in parallel with the first trace 31, the trace resistance after parallel connection becomes R. After the first trace 31 is connected in parallel, it reaches the position of the gate driver chip 3 after traveling a certain distance again, and the trace resistance at this time becomes 2R. That is, the trace resistance of the first trace 31 connected to the power pin of the gate driver chip 3 is 2R. If the VGL trace 3 is not connected in parallel with the first trace 31, then the trace resistance of the first trace 31 connected to the power pin of the gate driver chip 3 will become 3R. The subsequent analysis process is similar. Referring to the analysis process above, it can be seen that the parallel connection of the traces makes the trace resistance of each gate driver chip 211 connected to each group of chip units 21 more balanced.

[0050] In addition, such as Figure 2 As shown, a set of second PLG traces 40 is also provided in the first bonding area 121 on each side. The second PLG traces 40 are located on the side of the chipset 20 away from the power signal terminal, and the second PLG traces 40 are disconnected from the chipset 20.

[0051] The number of traces included in the second PLG trace 40 is the same as the number of traces included in the first PLG trace 30. For example, the first PLG trace 30 includes one first trace 31 and three second traces 32, and the second PLG trace 40 includes one fourth trace 41 and three fifth traces 42.

[0052] The second PLG wire 40 is not connected with each gate drive chip 211 in the chipset 20. By arranging the second PLG wire 40 on the side of the chipset 20 far from the power signal end, the uniformity of the wiring in the first binding area 121 is improved.

[0053] In another alternative embodiment of the present application, as shown in Figure 3 and Figure 4 two chipsets 20 and two groups of first PLG wires 30 are arranged in each first binding area 121; the non-display area further comprises a second binding area 122 located on each side of the display area 11, each second binding area 122 is located on the side adjacent to the side of the first binding area 121; and the power signal end connected by one group of first PLG wires 30 is located in one of the second binding areas 122, and the power signal end connected by the other group of first PLG wires 30 is located in the other second binding area 122.

[0054] At this time, the second binding area 122 is arranged on the DP side and the DPO side of the display area 11, and a PCB is arranged in each second binding area 122, one group of first PLG wires 30 is connected with the PCB in one of the second binding areas 122 through a gold finger, and the other group of first PLG wires 30 is connected with the PCB in the other second binding area 122 through a gold finger.

[0055] Next, taking a large-size display panel with a resolution of 3840*2160 as an example, the connection relationship between the gate drive chip 211 and the first PLG wire 30 is introduced. At this time, the power signal end connected by one group of first PLG wires 30 is located in the second binding area 122 on the DP side, and the power signal end connected by the other group of first PLG wires 30 is located in the second binding area 122 on the DPO side. And 8 gate drive chips 211 are arranged in each first binding area 121 on each side, and each gate drive chip 211 can drive 270 gate lines. Therefore, two chipsets 20 are arranged in each first binding area 121 on each side, each chipset 20 is divided into 4 chip units 21, each chip unit 21 includes one gate drive chip 211, and each group of first PLG wires 30 includes one first wire 31 and three second wires 32.

[0056] The three second traces 32 are called VGL trace 1, VGL trace 2 and VGL trace 3 in sequence, and the eight gate drive chips 211 are gate drive chip 1 (IC1), gate drive chip 2 (IC2), gate drive chip 3 (IC3), gate drive chip 4 (IC4), gate drive chip 5 (IC5), gate drive chip 6 (IC6), gate drive chip 7 (IC7) and gate drive chip 8 (IC8) in the direction from the DP side to the DPO side. Each gate drive chip 211 is a group of chip units 21, and the four groups of chip units 21 corresponding to the gate drive chip 1, the gate drive chip 2, the gate drive chip 3 and the gate drive chip 4 are a chip group 20 close to the DP side; and the four groups of chip units 21 corresponding to the gate drive chip 5, the gate drive chip 6, the gate drive chip 7 and the gate drive chip 8 are another chip group 20 close to the DPO side.

[0057] The input end of the first wire 31, the VGL wire 1, the VGL wire 2 and the VGL wire 3 corresponding to the chip set 20 close to the DP side are connected with the same power signal end on the DP side, and the first wire 31 is also connected with the power pin of the gate drive chip 1, the gate drive chip 1 is driven by the power signal provided by the first wire 31, and the VGL wire 1, the VGL wire 2 and the VGL wire 3 pass through the gate drive chip 1; after the first wire 31, the VGL wire 1, the VGL wire 2 and the VGL wire 3 pass through the gate drive chip 1, the VGL wire 3 is connected with the first wire 31 in parallel to form a first wire 31 after the first parallel, at this time, the first PLG wire 30 is only left with 3 wires, the first wire 31 after the first parallel, the VGL wire 1 and the VGL wire 2 reach the position of the gate drive chip 2 after passing through a distance, the first wire 31 after the first parallel is connected with the power pin of the gate drive chip 2, the gate drive chip 2 is driven by the power signal provided by the first wire 31 after the first parallel, and the VGL wire 1 and the VGL wire 2 pass through the gate drive chip 2; after the first wire 31 after the first parallel, the VGL wire 1 and the VGL wire 2 pass through the gate drive chip 2, the VGL wire 2 is connected with the first wire 31 after the first parallel again to form a second wire 31 after the second parallel, at this time, the first PLG wire 30 is only left with 2 wires, the second wire 31 after the second parallel and the VGL wire 1 reach the position of the gate drive chip 3 after passing through a distance, the second wire 31 after the second parallel is connected with the power pin of the gate drive chip 3, the gate drive chip 3 is driven by the power signal provided by the second wire 31 after the second parallel, and the VGL wire 1 passes through the gate drive chip 3; after the second wire 31 after the second parallel and the VGL wire 1 pass through the gate drive chip 3, the VGL wire 1 is connected with the second wire 31 after the second parallel again to form a third wire 31 after the third parallel, at this time, the first PLG wire 30 is only left with 1 wire, the third wire 31 after the third parallel reaches the position of the gate drive chip 4 after passing through a distance, and is connected with the power pin of the gate drive chip 4, the gate drive chip 4 is driven by the power signal provided by the third wire 31 after the third parallel.

[0058] Similarly, for another chip set 20 close to the DPO side, the input ends of the corresponding first wire 31, VGL wire 1, VGL wire 2 and VGL wire 3 are all connected with the same power signal end located at the DPO side, and the first wire 31 is also connected with the power pin of the gate drive chip 8, the gate drive chip 8 is driven by the power signal provided by the first wire 31, and the VGL wire 1, VGL wire 2 and VGL wire 3 all pass through the gate drive chip 8; after the first wire 31, VGL wire 1, VGL wire 2 and VGL wire 3 pass through the gate drive chip 8, the VGL wire 3 therein is connected in parallel with the first wire 31 to form a first wire 31 after first parallel, at this time the first PLG wire 30 is left with only 3 wires, the first wire 31 after first parallel, VGL wire 1 and VGL wire 2 reach the position of the gate drive chip 7 after passing through a distance, the first wire 31 after first parallel is connected with the power pin of the gate drive chip 7, the gate drive chip 7 is driven by the power signal provided by the first wire 31 after first parallel, and the VGL wire 1 and VGL wire 2 pass through the gate drive chip 7; after the first wire 31 after first parallel, VGL wire 1 and VGL wire 2 pass through the gate drive chip 7, the VGL wire 2 therein is connected in parallel with the first wire 31 after first parallel again to form a first wire 31 after second parallel, at this time the first PLG wire 30 is left with only 2 wires, the first wire 31 after second parallel and VGL wire 1 reach the position of the gate drive chip 6 after passing through a distance, the first wire 31 after second parallel is connected with the power pin of the gate drive chip 6, the gate drive chip 6 is driven by the power signal provided by the first wire 31 after second parallel, and the VGL wire 1 passes through the gate drive chip 6; after the first wire 31 after second parallel and VGL wire 1 pass through the gate drive chip 6, the VGL wire 1 is connected in parallel with the first wire 31 after second parallel again to form a first wire 31 after third parallel, at this time the first PLG wire 30 is left with only 1 wire, the first wire 31 after third parallel reaches the position of the gate drive chip 5 after passing through a distance, and is connected with the power pin of the gate drive chip 5, the gate drive chip 5 is driven by the power signal provided by the first wire 31 after third parallel.

[0059] From the above analysis, Figure 3 The equivalent circuit diagram corresponding to the wiring mode shown in Figure 6 The equivalent circuit diagram corresponding to the wiring mode shown in Figure 4 The equivalent circuit diagram corresponding to the wiring mode shown in Figure 7As shown, assuming that the wiring resistance of the first PLG wire 30 from the power signal end to the gate drive chip 1 and the wiring resistance of the first PLG wire 30 between the two adjacent gate drive chips 211 are both R, the wiring resistance of the first wire 31 connected with the power pin of the gate drive chip 1 is R, and since the VGL wire 3 is connected in parallel with the first wire 31, the wiring resistance after being connected in parallel is R / 2, and the first wire 31 after being connected in parallel again passes through a distance to reach the position of the gate drive chip 2, at which time the wiring resistance is 3R / 2, that is, the wiring resistance of the first wire 31 connected with the power pin of the gate drive chip 2 is 3R / 2; if the VGL wire 3 is not connected in parallel with the first wire 31, the wiring resistance of the first wire 31 connected with the power pin of the gate drive chip 2 will be 2R. The subsequent analysis process is similar, and it can be known from the above analysis process that, based on the parallel connection of the wires, the wiring resistances of the gate drive chips 211 connected to each group of chip units 21 are more balanced.

[0060] In actual products, as shown in Figure 3 , the power pin of the first edge chip is connected with the power pin of the second edge chip through the third wire 33; or as shown in Figure 4 , the power pin of the first edge chip is disconnected with the power pin of the second edge chip; the two chip groups 20 are respectively a first chip group and a second chip group, the first edge chip is the gate drive chip 211 closest to the second chip group in the first chip group, and the second edge chip is the gate drive chip 211 closest to the first chip group in the second chip group.

[0061] In Figure 3 and Figure 4 , the first edge chip refers to the gate drive chip 4, and the second edge chip refers to the gate drive chip 5. As shown in Figure 3 , the power pin of the gate drive chip 4 is connected with the power pin of the gate drive chip 5 through the third wire 33, so that the voltage balance between the two chip groups 20 can be realized; as shown in Figure 4 , the power pin of the gate drive chip 4 is disconnected with the power pin of the gate drive chip 5, that is, the two chip groups 20 are controlled separately through the respective first PLG wires 30, and do not affect each other.

[0062] In the embodiments of the present application, the total number of the first wires 31 and the second wires 32 included in each group of first PLG wires 30 is equal to the number of groups of chip units 21 included in each chip group 20; and the number of gate drive chips 211 included in each group of chip units 21 is equal.

[0063] As shown in Figures 2 to 4As shown, each group of first PLG wires 30 includes 1 first wire 31 and 3 second wires 32, that is, the total number of first wires 31 and second wires 32 included in each group of first PLG wires 30 is 4, and the group number of chip units 21 included in each chip group 20 is 4.

[0064] In addition, in Figure 2 , the number of gate drive chips 211 included in each group of chip units 21 is 2, in Figure 3 , the number of gate drive chips 211 included in each group of chip units 21 is 1. Figure 4

[0065] When the total number of first wires 31 and second wires 32 included in each group of first PLG wires 30 is equal to the group number of chip units 21 included in each chip group 20, the first PLG wires 30 connected to the last group of chip units 21 only include first wires 31, that is, while achieving the equalization of the wire resistance of each gate drive chip 211 by connecting the second wires 32 in parallel with the first wires 31, the total number of wires included in the first PLG wires 30 is minimized, that is, the material required by the first PLG wires 30 is reduced.

[0066] It should be noted that the group number of chip units 21 included in each chip group 20 is not limited to Figures 2 to 4 4 groups as shown, but can also be 2 groups, 3 groups, 5 groups, etc.; and the number of gate drive chips 211 included in each group of chip units 21 is not limited to Figure 3 1 as shown, and Figure 4 2 as shown, but can also be 3, etc. Figure 2

[0067] In addition, each group of chip units 21 includes at least two gate drive chips 211; within the same chip unit 21, the first wire 31 and the second wire 32 do not have a connection relationship. That is, when each group of chip units 21 includes at least two gate drive chips 211, the first wire 31 in the same chip unit 21 does not contact each second wire 32.

[0068] As shown in Figure 2 and Figure 8 ​​As shown, a first flip-chip thin film 50 is also provided in the first bonding area 121 on each side. Each gate driver chip 211 is bonded to the first bonding area 121 through the first flip-chip thin film 50. A first connection line 51 and at least one second connection line 52 are provided on the first flip-chip thin film 50. The first trace 31 is disconnected at the position of the gate driver chip 211, and the disconnected first trace 31 is connected through the first connection line 51. The second trace 32 is disconnected at the position of the gate driver chip 211, and the disconnected second trace 32 is connected through the second connection line 52.

[0069] In actual products, the first flip-chip film 50 refers to the COF (Chip On Film) corresponding to the gate driver chip 211. The gate driver chip 211 is disposed on the first flip-chip film 50 so as to bind the gate driver chip 211 in the first bonding area 121 through the first flip-chip film 50.

[0070] Each first flip-chip film 50 has a trace connected to the first PLG trace 30, namely a first connection line 51 and at least one second connection line 52. The first connection line 51 connects the disconnected first traces 31 together. When there is a second trace 32 between two adjacent gate driver chips 211 that is not connected in parallel with the first trace 31, the corresponding second connection line 52 connects the disconnected second traces 32 together; when the second trace 32 between two adjacent gate driver chips 211 is connected in parallel with the first trace 31, or when there is no second trace 32 between two adjacent gate driver chips 211, the corresponding second connection line 52 is a disconnected signal line.

[0071] For example, such as Figure 2 As shown, the first trace 31 between gate driver chip 6 and gate driver chip 7, and the first trace 31 between gate driver chip 7 and gate driver chip 8, are disconnected at the location of gate driver chip 7, and connected by a first connection line 51 on the first flip-chip film 50 corresponding to gate driver chip 7; correspondingly, the VGL trace 1 between gate driver chip 4 and gate driver chip 5, and the VGL trace 1 between gate driver chip 5 and gate driver chip 6, are disconnected at the location of gate driver chip 5, and connected by a second connection line 52 on the first flip-chip film 50 corresponding to gate driver chip 5; when only the first trace 31 exists between gate driver chip 7 and gate driver chip 8 and the second trace 32 does not exist, the second connection line 52 on gate driver chip 7 and gate driver chip 8 is not connected.

[0072] It is worth noting that the number of the second connecting lines 52 arranged on each first COF 50 is equal to the number of the second lines 32 included in each group of the first PLG lines 30.

[0073] It is to be noted that, by arranging the first connecting lines 51 and the second connecting lines 52 on the first COF 50, the first lines 31 and the second lines 32 arranged to be disconnected are connected, so that the occupied area of the first bonding area 121 can be reduced. If the first lines 31 and the second lines 32 included in the first PLG lines 30 arranged in the first bonding area 121 are directly connected without being connected through the first COF 50, since the film layer of the first PLG lines 30 is relatively thin, a larger area is required to reduce the line resistance, which will make the occupied area of the first bonding area 121 large. However, the film layer of the first connecting lines 51 and the second connecting lines 52 arranged on the first COF 50 is relatively thick, and the corresponding resistance is small, so the required area is reduced, and thus the occupied area of the first bonding area 121 is small.

[0074] In the embodiments of the present application, as shown in Figure 1 and Figure 9 , the display panel 10 is an in-cell touch display panel, the non-display area further includes a second bonding area 122 located on at least one side of the display panel 10 relative to the two sides of the display area 11, and a fan-out area 123 located on the side of each second bonding area 122 close to the display area 11; the display module further includes a touch display driving chip 60 located in each second bonding area 122; a plurality of data lines 111 and a plurality of touch signal lines 112 are arranged in the display area 11, a plurality of display leads 71 and a plurality of touch leads 72 are arranged in the fan-out area 123, and the touch display driving chip 60 has a plurality of display pins 61 and a plurality of touch pins 62; one end of each display lead 71 is connected with a data line 111, and the other end is connected with a display pin 61; one end of each touch lead 72 is connected with a touch signal line 112, and the other end is connected with a touch pin 62; wherein, in the row direction along the display panel 10, the distribution law of the display pins 61 and the touch pins 62 in the touch display driving chip 60 is the same as the distribution law of the data lines 111 and the touch signal lines 112 in the display area 11; the display leads 71 and the touch leads 72 are arranged in the same layer.

[0075] In actual products, the display panel 10 is an in-cell touch display panel, that is, the touch electrodes are arranged inside the display panel 10, at this time, a plurality of data lines 111 and a plurality of touch signal lines 112 are arranged in the display area 11.

[0076] The non-display area further includes a second binding area 122 and a fan-out area 123 between the second binding area 122 and the display area 11. At least one touch display driving chip 60, i.e. a TDDI (Touch and Display Driver Integration) chip, is arranged in the second binding area 122. The data lines 111 and the touch signal lines 112 are simultaneously driven by the touch display driving chip 60. Each touch display driving chip 60 has a plurality of display pins 61 and a plurality of touch pins 62. The fan-out area 123 is provided with a plurality of display lead lines 71 and a plurality of touch lead lines 72. Each display lead line 71 connects the data line 111 and the display pin 61. Each touch lead line 72 connects the touch signal line 112 and the touch pin 62.

[0077] In the row direction of the display panel 10, the distribution of the display pins 61 and the touch pins 62 in the touch display driving chip 60 is the same as the distribution of the data lines 111 and the touch signal lines 112 in the display area 11. That is, the arrangement sequence of the data lines 111 and the touch signal lines 112 in the display area 11 is the same as the arrangement sequence of the display pins 61 and the touch pins 62 in the touch display driving chip 60. Therefore, only one lead line layer including the display lead lines 71 and the touch lead lines 72 needs to be arranged in the fan-out area 123, so that the display lead lines 71 and the touch lead lines 72 are arranged in the same layer.

[0078] In the related art, all display pins in each touch display driving chip are concentrated in the middle, and touch pins are evenly distributed on both ends of the display pins. For example, the number of display pins in the touch display driving chip is 480, and the number of touch pins is 960. Along the distribution direction of the pins, they are 480 touch pins, 480 display pins, and 480 touch pins in turn. Alternatively, all touch pins in each touch display driving chip are concentrated in the middle, and display pins are evenly distributed on both ends of the touch pins. For example, the number of display pins in the touch display driving chip is 480, and the number of touch pins is 960. Along the distribution direction of the pins, they are 240 display pins, 960 touch pins, and 240 display pins in turn. Since the data lines 111 and the touch signal lines 112 arranged in the display area 11 are staggered, for example, the distribution ratio of the data lines 111 and the touch signal lines 112 is 1:2, that is, two touch signal lines 112 are distributed behind each data line 111, and two touch signal lines 112 are distributed between adjacent two data lines 111. At this time, in order to avoid the mutual influence of the data lines 111 and the touch signal lines 112, two layers of wire layers need to be arranged in the fan-out area 123, one layer of wire layer is used to arrange display leads, and the other layer is used to arrange touch leads. Therefore, the distribution mode of the related art needs to distribute two layers of wire layers in the fan-out area 123, which leads to a larger vertical occupied space of the fan-out area 123, and the touch leads and the display leads in the fan-out area 123 will generate overlapping capacitance.

[0079] In the embodiment of the present application, the distribution rule of the display pins 61 and the touch pins 62 in the touch display driving chip 60 is set to be the same as the distribution rule of the data lines 111 and the touch signal lines 112 in the display area 11, so that only one layer of lead layer is arranged in the fan-out area 123, that is, the display leads 71 and the touch leads 72 can be distributed, thereby reducing the vertical occupied space of the fan-out area 123. According to experimental measurement, compared with the first mode in the related art (the display pins are concentrated in the middle, and the touch pins are evenly distributed on both ends of the display pins), the space occupation area is saved by 10%, and compared with the second mode in the related art (the touch pins are concentrated in the middle, and the display pins are evenly distributed on both ends of the touch pins), the space occupation area is saved by 30%. When the display leads 71 and the touch leads 72 are arranged in the same layer, there is no direct overlapping capacitance between the display leads 71 and the touch leads 72. At this time, the coupling capacitance is only the lateral capacitance of the display leads 71 and the touch leads 72, and the coupling capacitance is small and uniform.

[0080] It should be noted that the non-display area can include two second binding areas 122, and each second binding area 122 is provided with a touch display driving chip 60, and one data line 111 is connected with the display pin 61 of the touch display driving chip 60 located in the two second binding areas 122, that is, the same data line 111 is driven by the touch display driving chip 60 located in the two second binding areas 122, so as to reduce the delay of the data line 111, improve the charging rate of the sub-pixel connected with the data line 111; and the touch electrodes of the in-cell touch display panel are divided into two parts along the row direction, one part of the touch electrodes connected with the touch signal line 112 is controlled by the touch display driving chip 60 located in the second binding area 122 on the DP side, and the other part of the touch electrodes connected with the touch signal line 112 is controlled by the touch display driving chip 60 located in the second binding area 122 on the DPO side, so as to reduce the load of the touch signal line 112 and improve the touch performance. Of course, the non-display area can also include one second binding area 122, that is, the second binding area 122 on the DP side or the second binding area 122 on the DPO side, at this time, the touch display driving chip 60 is arranged in the one second binding area 122, and the single-side driving of the data line 111 and the touch signal line 112 is realized.

[0081] In some optional embodiments, the number ratio of the touch signal line 112 connected with the touch display driving chip 60 to the data line 111 is X, X is a positive integer, and X touch pins 62 are arranged between any two adjacent display pins 61.

[0082] In some products, the data line 111 and the touch signal line 112 arranged in the display area 11 are distributed in a fixed integer ratio, for example, the data line 111 and the touch signal line 112 arranged in the display area 11 can be distributed in a 1:2 manner, at this time, the number ratio of the touch signal line 112 connected with the touch display driving chip 60 to the data line 111 is 2, and 2 touch pins 62 are arranged between any two adjacent display pins 61; or the data line 111 and the touch signal line 112 arranged in the display area 11 can be distributed in a 1:3 manner, at this time, the number ratio of the touch signal line 112 connected with the touch display driving chip 60 to the data line 111 is 3, and 3 touch pins 62 are arranged between any two adjacent display pins 61.

[0083] For example, as shown in FIG. 6, the data line 111 and the touch signal line 112 arranged in the display area 11 are distributed in a 1:2 manner, at this time, the number ratio of the touch signal line 112 connected with the touch display driving chip 60 to the data line 111 is 2, and 2 touch pins 62 are arranged between any two adjacent display pins 61. Figure 10As shown, the number of touch signal lines 112 connected to each touch display driving chip 60 is 960, and the number of data lines 111 connected to each touch display driving chip 60 is 480, that is, the number ratio of touch signal lines 112 to data lines 111 is 2, and accordingly, each touch display driving chip 60 has 480 display pins 61, such as the first display pin D1, the second display pin D2, and the 480th display pin D480, and each touch display driving chip 60 has 960 touch pins 62, such as the first touch pin T1, the second touch pin T2, the third touch pin T3, the fourth touch pin T4, and the 960th touch pin T960, and 2 touch pins 62 are arranged between any two adjacent display pins 61.

[0084] It should be noted that the pin distribution of the touch display driving chip 60 at this time is suitable for the mode of single-side driving of the data lines 111 and the touch signal lines 112, and if double-side driving is adopted, dummy pins corresponding to T959 and T960 need to be arranged in the touch display driving chip 60 on the DP side and the DPO side, so that the corresponding touch display driving chips 60 on the two sides are relatively mirror symmetrical in the row direction, that is, the touch display driving chip 60 on one side is rotated by 180° and is completely the same as the touch display driving chip 60 on the other side, to ensure that the second COF adopted by the touch display driving chips 60 on the two sides is the same.

[0085] In some other optional embodiments, the number of touch signal lines 112 connected to each touch display driving chip 60 is equal to the difference between X times the number of data lines 111 connected and Y; the pins of each touch display driving chip 60 are divided into Y / X pin groups; in the same pin group, the first pin and the last pin are both display pins 61, and X touch pins 62 are arranged between any two adjacent display pins 61; and the distribution of the pins in each pin group is the same; wherein X, Y, and Y / X are all positive integers greater than 1 or equal to 1; for the touch signal lines 112 and the data lines 111 connected to each touch display driving chip 60, the absolute value of the difference between the number of touch signal lines 112 and (X+1) times the number of data lines 111, and the absolute value of the difference between the number of touch signal lines 112 and (X-1) times the number of data lines 111, are both greater than Y.

[0086] In some products, the data lines 111 and the touch signal lines 112 arranged in the display area 11 are not distributed in an integral ratio, that is, the number ratio of the touch signal lines 112 connected to each touch display driving chip 60 to the data lines 111 is not a positive integer. In this case, in each touch display driving chip 60, the number of the X times of display pins 61 minus Y is equal to the number of touch pins 62, that is, the number of the touch signal lines 112 connected to each touch display driving chip 60 is equal to the number of the data lines 111 connected to each touch display driving chip 60 times X minus Y.

[0087] In this case, the pins of the touch display driving chip 60 need to be divided into Y / X pin groups, so that the distribution rules of the pins in each pin group are the same. In the same pin group, the first pin and the last pin are both display pins 61, and X touch pins 62 are arranged between the adjacent two display pins 61.

[0088] For example, for a 86-inch 4K in-cell touch display panel, the number of touch electrodes is 288*156, the number of touch signal lines 112 required is 44928, and the number of data lines 111 is 11520. The in-cell touch display panel is configured with 48 touch display driving chips 60, 24 touch display driving chips 60 are distributed on the DP side and the DPO side respectively, the data lines 111 are driven by double sides, and the touch signal lines 112 are divided into two parts, of which 22464 touch signal lines 112 are driven by the touch display driving chips 60 on the DP side, and the remaining 22464 touch signal lines 112 are driven by the touch display driving chips 60 on the DPO side. Therefore, each touch display driving chip 60 needs to drive 480 data lines 111 and 936 touch signal lines 112. In this case, the number ratio of the touch signal lines 112 connected to each touch display driving chip 60 to the data lines 111 is not a positive integer, and the number of the touch signal lines 112 connected to each touch display driving chip 60 is 936, which is equal to 2 times the number of the data lines 111 connected to each touch display driving chip 60 minus 24, that is, X is equal to 2 and Y is equal to 24.

[0089] Therefore, as shown in FIG. 6, the pins of the touch display driving chip 60 are divided into 24 pin groups, and the distribution rules of the pins in each pin group are the same. In the same pin group, the first pin and the last pin are both display pins 61, and 2 touch pins 62 are arranged between the adjacent two display pins 61. Figure 11As shown, the pins of each touch display driving chip 60 are divided into 12 pin groups, each pin group includes 40 display pins 61 and 78 touch pins 62, the pins included in the first pin group are in turn: the first display pin D1, the first touch pin T1, the second touch pin T2, the second display pin D2, the third touch pin T3, the fourth touch pin T4, and so on until the 39th display pin D39, the 77th touch pin T77, the 78th touch pin T78, and the 40th display pin D40. The second pin group starts from the 41st display pin D41, and no touch pin is arranged between the 40th display pin D40 and the 41st display pin D41. In each pin group, the first pin and the last pin are display pins 61, and two touch pins 62 are arranged between adjacent two display pins 61.

[0090] It should be noted that for the touch signal lines 112 and the data lines 111 connected to each touch display driving chip 60, the absolute value of the difference between the number of touch signal lines 112 and the number of data lines 111 multiplied by (X+1), and the absolute value of the difference between the number of touch signal lines 112 and the number of data lines 111 multiplied by (X-1) are both greater than Y, which can minimize the number of pin groups obtained by division, and accordingly, the pin distribution of the touch display driving chip 60 is simpler.

[0091] When the data lines 111 and the touch signal lines 112 in some display products are not distributed in an integer ratio, if the pins included in the touch display driving chip 60 are still distributed in a fixed ratio, at this time, dummy pins must be added in the touch display driving chip 60, such as two dummy pins between the 40th display pin D40 and the 41st display pin D41, thereby increasing the number of pins of the touch display driving chip 60, and the dummy pins will cause space waste and result in uneven distribution of the wires in the fan-out area 123. Therefore, the embodiment of the present application divides the pins included in the touch display driving chip 60, which are still distributed in a fixed ratio in the same pin group, and breaks the fixed ratio between adjacent two pin groups, thereby reducing the number of pins of the touch display driving chip 60 and the occupied space, and the wires in the corresponding fan-out area 123 can be evenly distributed.

[0092] In some products, the number of data lines 111 arranged in the display area 11 is N, the number of touch display driving chips 60 arranged in each second binding area 122 is M, and the number of display pins 61 included in each touch display driving chip 60 is N / M. N and M are both positive even numbers, and N is greater than M.

[0093] If the data lines 11 are driven by both sides, and the number of the data lines 111 arranged in the display area 11 is an even number N, and the number of the touch display driving chips 60 used is 2M, and the number of the touch display driving chips 60 arranged in each second binding area 122 is M, at this time, the data lines 111 are evenly distributed according to the number of the touch display driving chips 60 arranged on each side, that is, the number of the display pins 61 included in each touch display driving chip 60 is N / M, that is, each touch display driving chip 60 drives N / M data lines 111.

[0094] For example, as shown in FIG. 8, for a 86-inch 4K in-cell touch display panel, the number of the data lines is 11520, and the number of the touch display driving chips 60 arranged on the DP side and the DPO side is 24 respectively, then each touch display driving chip 60 has 480 display pins 61 to drive 480 data lines 111. Figure 11

[0095] In some other products, the number of the data lines 111 arranged in the display area 11 is N+1, and the number of the touch display driving chips 60 arranged in each second binding area 122 is M; the touch display driving chips 60 are divided into two types, which are the first type of driving chip and the second type of driving chip; the number of the first type of driving chip is M-1, and the number of the display pins 61 included in the first type of driving chip is N / M; the number of the second type of driving chip is 1, and the display pins 61 included in the second type of driving chip are divided into the first display pins and the second display pins, the number of the first display pins is N / M, and the number of the second display pins is 1; N and M are both positive even numbers, and N is greater than M; the second display pins in the second type of driving chip are located before or after all the remaining pins in the second type of driving chip.

[0096] If the data lines 11 are driven by both sides, and the number of the data lines 111 arranged in the display area 11 is an odd number N+1, and the number of the touch display driving chips 60 used is 2M, and the number of the touch display driving chips 60 arranged in each second binding area 122 is M, at this time, the touch display driving chips 60 are divided into two types, the number of the first type of driving chip is M-1, the number of the display pins 61 included in the first type of driving chip is N / M, and the number of the second type of driving chip is 1, the number of the display pins 61 included in the second type of driving chip is 1+N / M. Among them, the display pins 61 included in the second type of driving chip are divided into the first display pins and the second display pins, the number of the first display pins is N / M, and the number of the second display pins is 1, and the second display pins are located before or after all the remaining pins in the second type of driving chip.

[0097] ​For example, the display panel 10 includes 11521 data lines, and 24 touch display driving chips 60 are arranged in each second binding area 122, of which 23 touch display driving chips 60 are first type driving chips and include 480 display pins 61, and the remaining one touch display driving chip 60 is a second type driving chip and includes 481 display pins 61. As shown in Figure 12 the first display pin in the second type driving chip is display pin D1 to display pin D480, and the second display pin is D481, the second display pin D481 is arranged after all the remaining pins in the second type driving chip, i.e. after the first display pin D480, of course, it can also be arranged before the first display pin D1.

[0098] In addition, the non-display area includes a second binding area 122 located on opposite sides of the display area 11, and a second chip-on-film 82 is further arranged in each second binding area 122, and each touch display driving chip 60 is bound to the second binding area 122 through the second chip-on-film 82; in the second binding area 122 on the first side and the second binding area 122 on the second side, the second type driving chip further includes one first dummy pin, and the first type driving chip further includes two second dummy pins; in the second type driving chip, the first dummy pin and the second display pin are located on both sides of all the remaining pins; and the first dummy pin in the second type driving chip on one side and the second display pin in the second type driving chip on the other side are connected to the same data line 111.

[0099] When the number of data lines 111 driven by each touch display driving chip 60 is inconsistent, in order to ensure that the second chip-on-film 82 used by each touch display driving chip 60 is the same, a first dummy pin is added in the second type driving chip, and two second dummy pins are added in the first type driving chip, so that the total number of pins of each touch display driving chip 60 is equal, and the number of wirings on the second chip-on-film used by each touch display driving chip 60 is also equal, so that the touch display driving chip 60 driving different numbers of data lines 111 can use the same second chip-on-film 82, simplifying the design requirements of the second chip-on-film 82.

[0100] In addition, in the first type driving chip, the two second dummy pins can be located on both sides of all the remaining pins.

[0101] For example, as shown in Figure 12As shown, the second type of driving chip further includes a first dummy pin Dummy, the first dummy pin Dummy and the second display pin D481 are located on both sides of all the remaining pins, and the first dummy pin Dummy located on the DP side and the second display pin D481 located on the DPO side are connected with the same data line 111, while there is no data line 111 between the first dummy pin Dummy located on the DPO side and the second display pin D481 located on the DP side; and the first dummy pin Dummy located on the DP side does not output a data signal, but only outputs a corresponding data signal through the second display pin D481 to control the data line 111 connected therewith. At this time, the total number of pins in the second type of driving chip except the touch pin 62 is 482, and accordingly, for the other 23 first type of driving chips, two second dummy pins also need to be added, so that the total number of pins in the first type of driving chip except the touch pin 62 is also 482.

[0102] It should be noted that for the first type of driving chip, only 2 second dummy pins are added, and no wiring connected with the second dummy pin is arranged in the fan-out area 123 and the display area 111; while for the second type of driving chip, not only one first dummy pin is added, but also one wiring connected therewith is arranged in the fan-out area 123 and the display area 111.

[0103] In actual products, a PCB 81 is further arranged in each second binding area 122, and the PCB 81 also needs to be bound with the second chip-on-film 82, for providing a corresponding signal to the touch display driving chip 60 arranged on the second chip-on-film 82.

[0104] In the embodiment of the present application, by dividing the chip group into at least two chip units, and connecting the first wiring connected with the power pin of the last gate driving chip in the previous chip unit and any second wiring in parallel to the power pin of the first gate driving chip in the next chip unit, the wiring resistance between each gate driving chip in each chip unit is more balanced, therefore, the voltage difference of the power signal provided to each gate driving chip in each chip unit is reduced, and accordingly, the brightness difference of the pixels driven by the gate driving chips in each chip unit is also reduced, thereby reducing the display horizontal lines of the display panel.

[0105] The embodiment of the present application further provides a display device including the display module.

[0106] In actual application, the display device can be: a mobile phone, a tablet computer, a display, a notebook computer, a navigator, or any product or component with display and touch functions.

[0107] In addition, the specific structure of the display module in the display device can refer to the description of the display module above, and the effects are similar to those of the display module above. To avoid repetition, it will not be described here.

[0108] As used in this description, the terms "one embodiment", "an embodiment” or "one or more embodiments” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment” in various places in this description are not necessarily all referring to the same embodiment.

[0109] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0110] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising” does not exclude the presence of elements or steps other than those listed in a claim. The word "a” or "an” preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices, apparatuses or means can be listed, comprising means for carrying out a certain task. The use of the term "first”, "second” and "third” etc. does not limit the number of these means. These terms can be construed to be names.

[0111] Finally, it should be noted that the above-described embodiments are merely intended for describing and illustrating, but not limiting the technical solutions of the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to part of the technical features; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A display module, characterized by The display panel comprises a display area and a non-display area surrounding the display area, the non-display area comprising a first binding area on at least one side of the display area; At least one chip set and a group of first PLG wires corresponding to each chip set are arranged in the first binding area on each side; each chip set comprises at least two groups of chip units, and each group of chip units comprises at least one gate drive chip; each group of first PLG wires comprises a first wire and at least one second wire, and the input end of the first wire and each second wire is connected with the same power signal end; Wherein, the power pins of any two adjacent gate drive chips are connected through the first wire, and each second wire passes through each gate drive chip; and from the direction close to the power signal end to the direction away from the power signal end, the first wire connected with the power pin of the last gate drive chip in the last group of chip units and any second wire are connected in parallel to the power pin of the first gate drive chip in the next group of chip units. One chip set and a group of first PLG wires are arranged in the first binding area on each side; 2. The display module of claim 1, wherein, The non-display area further comprises a second binding area on any one side of the display area, the side of the second binding area is adjacent to the side of the first binding area, and the power signal end connected with the first PLG wire is located in the second binding area. Two chip sets and two groups of first PLG wires are arranged in the first binding area on each side; 3. The display module of claim 1, wherein, The non-display area further comprises a second binding area on each side of the display area, and the side of each second binding area is adjacent to the side of the first binding area; And the power signal end connected with one group of first PLG wires is located in one of the second binding areas, and the power signal end connected with the other group of first PLG wires is located in the other second binding area. The power pin of the first edge chip is connected with the power pin of the second edge chip through a third wire; or, the power pin of the first edge chip is disconnected from the power pin of the second edge chip; 4. The display module of claim 3, wherein, The two chip sets are a first chip set and a second chip set, the first edge chip is the gate drive chip in the first chip set closest to the second chip set, and the second edge chip is the gate drive chip in the second chip set closest to the first chip set. The total number of the first wires and the second wires included in each group of first PLG wires is equal to the number of groups of chip units included in each chip set; 5. The display module of claim 1, wherein, And the number of gate drive chips included in each group of chip units is equal. Each group of chip units comprises at least two gate drive chips; in the same chip unit, the first wire and the second wire have no connection relationship.

6. The display module of claim 1, wherein, ​ 7. The display module of claim 2, wherein, A second PLG wire group is arranged in the first binding area on each side, the second PLG wire group is arranged on the side of the chipset away from the power signal end, and the second PLG wire group is disconnected from the chipset.

8. The display module of claim 1, wherein, A first COF is arranged in the first binding area on each side, and each gate drive chip is bound to the first binding area through the first COF. The first wire is disconnected at the position of the gate drive chip, and the disconnected first wire is connected through the first connecting line. The second wire is disconnected at the position of the gate drive chip, and the disconnected second wire is connected through the second connecting line.

9. The display module of any one of claims 1-8, wherein, The display panel is an in-cell touch display panel, the non-display area further includes a second binding area on at least one of opposite sides of the display area, and a fan-out area on the side of each second binding area close to the display area; the display module further includes a touch display drive chip in each second binding area. The display area is provided with a plurality of data lines and a plurality of touch signal lines, the fan-out area is provided with a plurality of display leads and a plurality of touch leads, and the touch display drive chip has a plurality of display pins and a plurality of touch pins; one end of each display lead is connected with the data line, and the other end is connected with the display pin; one end of each touch lead is connected with the touch signal line, and the other end is connected with the touch pin. In the row direction of the display panel, the distribution rule of the display pins and the touch pins in the touch display drive chip is the same as the distribution rule of the data lines and the touch signal lines in the display area; the display leads and the touch leads are arranged in the same layer.

10. The display module of claim 9, wherein, The number ratio of the touch signal lines connected to each touch display drive chip to the data lines is X, X is a positive integer.

11. The display module of claim 9, wherein, The number of the touch signal lines connected to each touch display drive chip is equal to the difference between X times the number of the data lines connected and Y. The pins of each touch display drive chip are divided into Y / X pin groups; in the same pin group, the first pin and the last pin are both display pins, and X touch pins are arranged between adjacent display pins; and the distribution rule of the pins in each pin group is the same. X, Y and Y / X are all positive integers greater than 1 or equal to 1; for the touch signal lines and the data lines connected to each touch display drive chip, the absolute value of the difference between the number of the touch signal lines and (X+1) times the number of the data lines, and the absolute value of the difference between the number of the touch signal lines and (X-1) times the number of the data lines, are both greater than Y.

12. The display module of claim 9, wherein, The number of the data lines arranged in the display area is N, the number of the touch display driving chips arranged in each of the second binding areas is M, the number of the display pins included in each of the touch display driving chips is N / M, N and M are both positive even numbers, and N is greater than M.

13. The display module of claim 9, wherein, The number of the data lines arranged in the display area is N+1, the number of the touch display driving chips arranged in each of the second binding areas is M; The touch display driving chips are divided into two types, which are the first type of driving chip and the second type of driving chip; the number of the first type of driving chip is M-1, and the number of the display pins included in the first type of driving chip is N / M; the number of the second type of driving chip is 1, and the display pins included in the second type of driving chip are divided into a first display pin and a second display pin, the number of the first display pin is N / M, and the number of the second display pin is 1; N and M are both positive even numbers, and N is greater than M; The second display pin in the second type of driving chip is located before or after all the remaining pins in the second type of driving chip.

14. The display module of claim 13, wherein, The second binding area included in the non-display area is located on opposite sides of the display area, and each side of the second binding area is further provided with a second chip on film, and each of the touch display driving chips is bound to the second binding area through the second chip on film; In the second binding area on the first side and the second binding area on the second side, the second type of driving chip further includes one first dummy pin, and the first type of driving chip further includes two second dummy pins; In the second type of driving chip, the first dummy pin and the second display pin are located on both sides of all the remaining pins; and the first dummy pin in the second type of driving chip on one side and the second display pin in the second type of driving chip on the other side are both connected to the same data line.

15. A display device comprising: The display module includes any one of claims 1 to 14. The display module includes any one of claims 1 to 14.

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