System architecture determination based on machine learning

Abstract

This invention describes examples of techniques for system architecture determination based on machine learning. One aspect includes receiving a system architecture specification corresponding to a system design, and multiple topology variants of that specification. Another aspect includes determining a system architecture graph based on the system architecture specification. Yet another aspect includes classifying each topology variant as a feasible or infeasible architecture based on the system architecture graph using a neural network-based classifier. Finally, yet another aspect includes identifying a subset of feasible architectures as system design candidates based on performance prediction.

Description

Background Technology

[0001] This technology relates to machine learning. More specifically, it relates to machine learning-based system architecture determination.

[0002] Human engineers or designers can use their expertise and skills to design system architectures for complex engineering systems. They can generate a relatively large number of possible architectures based on the system architecture and examine these architectures to determine which are feasible. From this pool of feasible architectures, they can further explore and coarsely simulate selected architectures to predict system performance. Based on the predicted performance, the highest-performing model (which can be based on one or more specific performance requirements, such as higher acceleration for a car suspension) is selected for a trade-off study using high-fidelity simulations to determine the final optimal design. This trade-off study may require a relatively large amount of time and effort from the engineering team and is therefore best performed on a relatively small set of manually created models. Summary of the Invention

[0003] Embodiments of the present invention target the detection of duplicate code segments in source code. A non-limiting example of a computer-implemented method includes receiving a system architecture specification corresponding to a system design, and multiple topology variants of that system architecture specification. The method further includes determining a system architecture graph based on the system architecture specification. The method further includes classifying each topology variant among the topology variants as a feasible or infeasible architecture based on the system architecture graph using a neural network-based classifier. The method further includes identifying a subset of feasible architectures as system design candidates based on performance prediction.

[0004] Other embodiments of the present invention implement the features of the above-described method in computer systems and computer program products.

[0005] Additional technical features and benefits are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the detailed description and accompanying drawings. Attached Figure Description

[0006] Figure 1 A block diagram of an exemplary system for determining system architecture based on machine learning is shown;

[0007] Figure 2 A flowchart illustrating an exemplary method for determining system architecture based on machine learning is shown.

[0008] Figure 3A A block diagram of an exemplary system architecture specification for machine learning-based system architecture determination is shown.

[0009] Figure 3BA block diagram of an exemplary topology variant for machine learning-based system architecture determination is shown;

[0010] Figure 4 A block diagram illustrating an exemplary system architecture graph for machine learning-based system architecture determination is shown.

[0011] Figure 5 A block diagram is shown of an exemplary set of primitives for determining a system architecture based on machine learning;

[0012] Figure 6 A diagram illustrating an exemplary saliency map for machine learning-based system architecture determination is shown;

[0013] Figure 7 A block diagram illustrating exemplary extracted rules for determining a machine learning-based system architecture is shown; and

[0014] Figure 8 A block diagram of an exemplary computer system used in conjunction with a machine learning-based system architecture is shown. Detailed Implementation

[0015] An example of system architecture determination based on machine learning is provided, and exemplary embodiments will be discussed in detail below. Developing high-performance functional system models for complex engineering systems (including but not limited to embedded systems, satellite systems, or vehicle suspension or powertrain systems) can require a relatively significant investment of time and effort from design engineers. Tools for system architecture design of complex systems can use combinatorial methods to generate a set of possible designs, which need to be refined by expert engineers to determine feasible topologies for the system architecture. The process of refining possible designs to determine a reduced set of feasible system architectures may require expert engineers to manually review a relatively large number of possible designs. Because engineers may not be able to manually review the relatively large number (e.g., thousands) of possible designs that may be generated by system architecture design tools, there may be a limited exploration of the design space, and some feasible architectures may not be considered.

[0016] Machine learning can be used to discover rules characterizing feasible and infeasible system architecture designs, thereby reducing the number of potential designs that need to be reviewed by engineering teams. Possible designs can be categorized into feasible and infeasible system architectures based on graph embeddings. In various embodiments, graph embeddings can include the generation of adjacency matrices or graphlet-based embeddings performed on the system architecture graph. Feasible architectures can be identified for further analysis based on the extracted rules. These feasible architectures are parameterized, and machine learning techniques are used to perform simulations to evaluate key performance indicators (KPIs). KPIs can be determined relatively quickly and accurately using surrogate models. Based on system requirements and the determined KPIs, a relatively small number of identified feasible system architectures can be selected for broader human analysis and review.

[0017] Figure 1 A block diagram of a system 100 for determining a system architecture based on machine learning, according to one or more embodiments of the present invention, is shown. Figure 2 A process flowchart illustrating an illustrative method 200 for determining a system architecture based on machine learning, according to one or more embodiments of the present invention, is shown. It will be described below in conjunction with each other. Figure 1 and Figure 2 Embodiments of system 100 and method 200 can be implemented in conjunction with any suitable computer system, such as... Figure 8 The computer system 800. For example, system 100 may include software 811 executed by processor 801 and may operate on data stored in system memory 803 and / or mass storage 810.

[0018] In block 201 of method 200, system architecture acquisition module 101 in system 100 accepts a system architecture specification for a complex engineering problem as input, including possible topology variants and parameters or configuration options for elements of the system architecture specification. The system architecture specification can describe any suitable complex system, including but not limited to embedded systems, satellite systems, and vehicle suspension or powertrain systems. In various embodiments, the system architecture specification and topology variants can be determined by a generation engine and / or one or more experts (e.g., engineers). The system architecture specification can include any suitable information, such as a list of elements of the system architecture and any possible connections between those elements. In some embodiments, the system architecture specification can include an Extensible Markup Language (XML) document detailing possible connections between components of the system architecture. Configuration information can include any suitable types and values ​​for the elements included in the system architecture specification. Instances of system architecture specifications and topology variants for vehicle suspension systems that can be received by the system architecture acquisition module 101 in block 201 are relative to... Figures 3A-3BThe configuration options are shown, and exemplary associated options are shown relative to Table 1, which are discussed in further detail.

[0019] In block 202 of method 200, the preprocessing module 102 of system 100 receives a system architecture specification and associated topology variants from the system architecture acquisition module 101. The preprocessing module 102 is capable of converting the input format of the system architecture specification (e.g., XML representation) into a graph structure (e.g., a NetworkX graph), where each element of the system architecture specification is represented as a node, and edges between nodes represent connections. Edges can be directed and include data on input and output ports connecting nodes. The output of the preprocessing module 102 is a system architecture graph corresponding to the system architecture specification, which is provided to the graph embedding module 103. Instances of system architecture graphs that can be generated by the preprocessing module 102 are relative to... Figure 4 This will be explained in further detail below. In various embodiments, the system architecture specifications received by the preprocessing module 102 and the system architecture diagrams output by the preprocessing module 102 can be in any suitable format.

[0020] In block 203 of method 200, the graph embedding module 103 receives a system architecture graph from the preprocessing module 102. The graph embedding module 103 generates graph embeddings of specific predefined dimensions based on the system architecture graph. The graph embeddings can be mapped to substructures within the system architecture graph. In some embodiments, the adjacency matrix can be generated by the graph embedding module 103 based on the system architecture graph. In some embodiments, the graph embedding module 103 can perform primitive-based embeddings based on the system architecture graph. Both embeddings have the same size, independent of the size of the input graph, which facilitates performance prediction by the performance evaluation module 106 using a machine learning model.

[0021] One or more embodiments of the graph embedding module 103 can generate, in block 203, an adjacency matrix representing how each node in the system architecture graph is connected to every other node in the input graph. The adjacency matrix can be a sparse matrix representing the connectivity of edges in the system architecture graph. For example, each entry in the adjacency matrix can correspond to two nodes in the system architecture graph and can describe the connection (i.e., edge) between the two nodes corresponding to that entry. For example, if there is an edge between two nodes in the system architecture graph, the corresponding entry in the adjacency matrix for those two nodes can be one; if there is no connection between the two nodes, the entry can be zero. For a system architecture graph including directed edges from node 1 to node 2, the entries in the adjacency matrix can indicate the directed edges in the system architecture graph; for example, the first entry in the adjacency matrix corresponding to nodes 1 and 2 can be one, and the second entry in the adjacency matrix corresponding to nodes 2 and 1 can be zero. The adjacency matrix can be constructed based on the largest set of nodes found in the input system architecture graph.

[0022] One or more embodiments of the graph embedding module 103 can perform primitive-based embedding in block 203 by generating primitives from an input system architecture graph and counting the number of times each particular primitive is generated. A primitive is a relatively small, connected, non-isomorphically induced subgraph of a larger network described by the input system architecture graph. In various embodiments, the input system architecture graph used to determine the primitive-based embedding can be an uncolored or colored network, and an undirected or directed network. Isomorphic primitives can be filtered from the generated primitives; isomorphism can be determined based on the identification of node and edge attributes and based on port type. Primitives included in the input system architecture graph can be counted using any suitable algorithm, including but not limited to the Orbital Counting Algorithm (ORCA) and G-Tries. In some embodiments, a histogram of primitive frequencies can be generated by the graph embedding module 103. In some embodiments, the histogram can be provided as a feature vector to the classification module 104, or the primitive frequencies can be compared with each other using the histogram, for example, based on norm difference. In some embodiments, primitives can be vectorized by extracting a basis that includes a set of subgraphs. Each primitive can be represented according to the basis set. It can remove any coordinate with zero variance from the primitive set. Figure 5 An example of a primitive set that can be generated by primitive-based embedding using an embodiment of the graphics embedding module 103 in box 203 is shown, which will be discussed in further detail below.

[0023] In block 204 of method 200, classification module 104 receives graph embeddings from graph embedding module 103 and classifies topology variants (i.e., possible system architectures) into feasible and infeasible architectures based on the graph embeddings. The classification module can include a neural network-based classifier. Any architecture labeled as infeasible by classification module 104 can be exempted from further inspection. In some embodiments, classification module 104 can use a Siamese network and a contrast loss to classify topology variants. The Siamese network output can include vectors that can be used to distinguish pairs of topology variants belonging to the same or different labels. In some embodiments, the neural network-based classifier in classification module 104 can include multiple layers, including a final layer trained by freezing the values ​​of all other layers in the neural network-based classifier. The output of classification module 104 is to label each topology variant of the system architecture as a feasible or infeasible architecture.

[0024] In block 205 of method 200, rule extraction module 105 receives possible system architectures, their assigned labels (e.g., feasible or infeasible architectures), and a trained classifier from classification module 104. Rule extraction module 105 extracts rules based on the classification to indicate why a possible architecture is feasible or infeasible. Negative rules determined by rule extraction module 105 can specify whether the absence of a feature indicates a possible system architecture is feasible or infeasible. For example, a negative rule can correspond to a feature not present in a feasible architecture. Positive rules determined by rule extraction module 105 can specify whether the presence of a feature indicates a possible system architecture is feasible or infeasible. For example, a negative rule can correspond to a feature present in a feasible architecture. Instances of negative features for bad connections can include direct connections between roads and car motors. Detecting the presence of bad connections in a possible architecture indicates that the possible architecture is infeasible; detecting the absence of such connections in a possible architecture indicates that the possible architecture is feasible.

[0025] In some embodiments, saliency maps can be generated by the rule extraction module 105 based on the classification architecture. Negative saliency maps can detect the absence of key features for each label (e.g., no bad connections in feasible architectures, or no good connections in infeasible architectures). Positive saliency maps can detect the presence of key features for each label (e.g., bad connections in infeasible architectures, or good connections in feasible architectures). In some embodiments, positive saliency maps (indicating the presence of one or more features) and negative saliency maps (indicating the absence of one or more features) can be generated for both the infeasible and feasible architecture sets. Combining negative saliency maps constructed based on feasible architectures and positive saliency maps constructed based on infeasible architectures yields a set of rules characterizing infeasible architectures. Combining negative saliency maps constructed based on infeasible architectures with positive saliency maps constructed based on feasible architectures yields a set of rules characterizing feasible architectures. In some embodiments, each saliency map can be converted into a binary representation using thresholding. The most prominent portion of the binary representation can be detected by the rule extraction module 105 for use as a rule. Gradient-weighted class activation mapping (GradCAM++) can be used to determine the parts of the saliency map responsible for classifying the architecture to a given label (i.e., feasible or infeasible) by the classifier. GradCAM++ can be used to extract classification rules from the saliency map via the rule extraction module 105. GradCAM maps are capable of highlighting any part of the saliency map responsible for the label.

[0026] In various embodiments, the rule extraction module 105 can represent rules in various formats based on whether the graph embedding module 103 generates an adjacency matrix or performs primitive-based embedding. The extracted rules can be fed back into a neural network-based classifier in the classification module 104 to refine the filtering of possible architectures into feasible and infeasible architectures. In embodiments where the graph embedding module 103 performs primitive-based embedding, instances of rules that can be generated by the rule extraction module 105 for infeasible architectures are relative to... Figure 7 This will be discussed in further detail below. The instance rules for the infeasible architecture of the embodiment where the graph embedding module 103 generates the adjacency matrix can include:

[0027] {'Environment' is connected to 'Semi-active_Damper_Hydraulics'} and

[0028] {'Environment' is connected to 'Balance_Control'}

[0029] In block 206 of method 200, performance evaluation module 106 receives a categorized set of feasible architectures, graphical embeddings, and configuration options. The performance evaluation module constructs a proxy model that performs simulations of the feasible architectures based on the configuration options received along with the system architecture specifications and determines key performance indicators (KPIs) to measure the predicted performance of each feasible architecture. KPIs may include any suitable metrics that describe the system architecture, including but not limited to acceleration, fuel consumption, cost, availability, and weight. Performance evaluation module 106 is capable of using any suitable number of data points to predict any suitable number of KPIs for the feasible architectures.

[0030] In various embodiments, the performance evaluation module 106 can use one or more regression methods. Examples of regression methods that can be implemented in embodiments of the performance evaluation module 106 include, but are not limited to, random forest regression, linear regression, gradient boosting regression, extra-tree regression, residual neural network-based regression, highly randomized tree regression, and Gaussian process regression. The performance evaluation module 106 can be trained using the results of an initial run from a reduced-order simulation until a desired error rate (e.g., less than 5%) is achieved. In some embodiments, the error metric can be 100*abs(y pred -y true ) / abs(y true ), where y prcd The value y is predicted by the surrogate model. true It is the true value (e.g., the ground truth) found in the test dataset of known results on the same input set.

[0031] In box 207 of method 200, it is determined whether the error rate of the KPI prediction from performance evaluation module 106 is less than a threshold. Based on the error exceeding the threshold in box 207, performance evaluation module 106 can identify any incorrectly classified architectures, and the process can return to box 204, where the neural network-based classifier in classification module 104 can be refined based on the identified incorrectly classified architectures, and the possible architectures can be reclassified as feasible or infeasible based on the refined classification module 104. The process can then proceed through boxes 205 and 206, where rules are extracted based on classification in box 205, and KPIs and associated error rates are determined for the reclassified architectures in box 206. The process then proceeds from box 206 to box 207. Based on the error less than the threshold in box 207, the process proceeds to box 208. In box 208, the current set of feasible architectures can be ranked based on the KPIs determined by the performance evaluation module 106 in box 206, and the ranked feasible architectures 107 are output by the performance evaluation module 106 of system 100. A subset of the ranked feasible architectures 107 can be selected as candidates for further analysis and manual review by design engineers to select the final architecture for the design of complex systems. Complex systems can be constructed based on the selected final architecture.

[0032] It should be understood that Figure 1 The block diagram is not intended to indicate that system 100 includes Figure 1 All components shown. Conversely, system 100 can include... Figure 1 Any suitable fewer or additional components not shown herein (e.g., additional computer systems, processors, memory components, embedded controllers, modules, computer networks, network interfaces, data inputs, etc.). Furthermore, the embodiments described herein with respect to system 100 can be implemented with any suitable logic, wherein, in various embodiments, the logic mentioned herein can include any suitable hardware (e.g., processors, embedded controllers, or application-specific integrated circuits, etc.), software (e.g., applications, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0033] Figure 2 The process flowchart is not intended to indicate that the operations of method 200 should be performed in any particular order, or that all operations of method 200 should be included in every case. Furthermore, method 200 is capable of including any suitable number of additional operations.

[0034] Figure 3AAn exemplary system architecture specification 300A for machine learning-based system architecture determination is described according to one or more embodiments of the present invention. System architecture specification 300A corresponds to a vehicle suspension model 301 and includes multiple elements 302-315. As shown in system architecture specification 300A, suspension model 301 includes an internal combustion engine 302, a battery 303, an electric motor 304, a generator 305, a gearbox 306, a clutch 307, driven axles 308 (which includes a front axle 310 having a front axle individual 311 and a front axle differential 312, and a rear axle 313 including a rear axle individual 314 and a rear axle differential 315), and a vehicle 309. Elements 302-315 include designated connection points that can be connected to other elements of the same type in various topological variations of system architecture specification 300A. For example, the internal combustion engine (ICE) 301 has a first connection point of type 1 and a second connection point of type 2; the first connection point can be connected to any other connection point of type 1 (e.g., on the electric motor 304, generator 305, gearbox 306, or clutch 307). The system architecture specification 300A can be generated by the engineering team and can be... Figure 2 The method 200 is provided in box 201 Figure 1 System architecture acquisition module 101 of system 100.

[0035] It is also possible to receive a set of configuration options corresponding to the system architecture specification in block 201 of method 200; an example of such configuration options corresponding to system architecture specification 300A is shown in Table 1. The configuration options can provide possible values ​​for various elements of the system architecture specification and can be used by performance evaluation module 106 to determine the KPIs of a feasible architecture.

[0036] Table 1: Exemplary configuration options for system architecture specifications

[0037]

[0038]

[0039] Figure 3A This is shown for illustrative purposes only. In various embodiments, such as Figure 3A The system architecture specification shown can include any suitable number and type of elements, each element having any suitable number and type of connection points, and can correspond to any suitable type of complex system.

[0040] Figure 3B A topology variant 300B-C for machine learning-based system architecture determination is described according to one or more embodiments of the present invention. Topology variant 300B-C is generated, for example, by a generation engine based on system architecture specification 300A, and... Figure 2The topology variants 300B-C are received by the system architecture acquisition module 101 in box 201. Each of the topology variants 300B-C includes a subset of elements 302-305 from system architecture specification 300A connected in a manner conforming to the constraints of system architecture specification 300A (e.g., connection points of the same type connect the elements). A relatively large number (e.g., hundreds or thousands) of topology variants such as topology variants 300B-C can be generated based on system architecture specifications such as system architecture specification 300A; the total set of topology variants can include any variants permitted within the constraints defined by system architecture specification 300A. Figure 2 In box 204, topological variants such as topological variants 300B-C are provided by Figure 1 The classification module 104 categorizes architectures into feasible and infeasible architectures.

[0041] Figure 3B This is shown for illustrative purposes only. Any suitable number of topology variants, such as topology variant 300B-C, can be generated based on system architecture specification 300A. Furthermore, topology variants such as topology variant 300B-C can include any suitable number of elements of any suitable type, and these elements can be connected in any suitable manner.

[0042] Figure 4 An exemplary system architecture diagram 400 for system architecture determination based on machine learning is shown according to one or more embodiments of the present invention. System architecture diagram 400 includes a plurality of interconnected nodes 401-411. Figure 4 As shown, the system architecture diagram 400 includes wheels 401, a physical system 402, springs 403, a chassis 404, a road 405, an environment 406, a semi-active converter 407, a canopy control 408, a control system 409, a hydraulic semi-active damper 410, and a semi-active damper hydraulic system 411. Nodes 401-411 are connected by edges. Edges can be directed and include edges connecting data on input and output ports on nodes 401-411 (e.g., edge 412 from an output port on the control system 409 to an input port on the physical system 402). System architecture diagrams such as system architecture diagram 400 can be constructed from... Figure 1 The preprocessing module 102 of system 100 is based on, for example, Figure 3A The system architecture specification 300A is used to generate the system architecture diagram. The system architecture diagram 400 is input into the diagram embedding module 103 to determine its relationship with the system architecture diagram 400. Figure 2 The graphical embedding corresponding to the system architecture specification on which method 200 is based in box 203.

[0043] Figure 4This is shown for illustrative purposes only. A system architecture diagram such as system architecture diagram 400 can include any suitable type and any suitable number of nodes, and these nodes can be connected in any suitable manner by any suitable number and configuration of edges.

[0044] Figure 5 An exemplary primitive set 500 for system architecture determination based on machine learning is shown according to one or more embodiments of the present invention. Figure 2 In block 203 of method 200, the graphics embedding module 103 can be based on, for example, Figure 4 The system architecture diagram 400 is used to generate the primitive set 500. Each primitive 500 includes a subset of interconnect nodes 501-511 from the basic system architecture diagram.

[0045] Figure 5 This is shown for illustrative purposes only. A set of primitives (e.g., primitive 500) may each include any suitable number of nodes of any suitable type, and the nodes can be connected in any suitable manner. Furthermore, any suitable number of primitives, such as primitive 500, can be generated based on the system architecture graph.

[0046] Figure 6 An exemplary saliency map 600 for system architecture determination based on machine learning according to one or more embodiments of the present invention is shown. A saliency map such as saliency map 600 can be determined by... Figure 1 The rule extraction module 105 in Figure 2 The adjacency matrix in box 205 is generated based on the adjacency matrix, which can be received from the graph embedding module 103. Figure 6 The saliency map 600 is a negative saliency map, indicating that the absence of a feature corresponding to region 601 in the saliency map is the reason for the lack of a topology variant that is classified as feasible or infeasible by the classification module 104. For example, region 601 of the saliency map 600 could correspond to the absence of a connection between two specified nodes in a topology variant (e.g., a road connected to a hydraulic passive damper), which would cause the classification module 104 to classify a topology variant that does not include that connection as feasible.

[0047] Figure 6 This is shown for illustrative purposes only. For example, in various embodiments, a saliency map such as saliency map 600 can include any suitable data and features, and can include negative saliency maps, positive saliency maps, or gradient-weighted class activation maps.

[0048] Figure 7 An exemplary extraction rule 700 for system architecture determination based on machine learning according to one or more embodiments of the present invention is described. Rule 700 can be derived by... Figure 1 The rule extraction module 105 in Figure 2The determination in box 205 is based on primitive-based embedding performed by the graph embedding module 103. Rule 700 includes interconnected sets of nodes 701-704 and defines specific connections between nodes that may be necessary to classify a particular topology variant as an infeasible architecture. Connections in the rule can be oriented. For example, in rule 700, both wheel 701 and chassis 704 are acted upon by physical systems 702 and springs 703.

[0049] Figure 7 This is shown for illustrative purposes only. For example, a rule such as rule 700 can include any suitable number and type of nodes connected in any suitable manner, and can be an affirmative or negative rule in various embodiments.

[0050] Now go to Figure 8 A computer system 800 is generally illustrated according to an embodiment. The computer system 800 can be an electronic computer framework, including and / or employing any number and combination of computing devices and networks utilizing various communication technologies, as described herein. The computer system 800 can be easily expanded, extended, and modularized, with the ability to change to different services or reconfigure certain features independently of other features. The computer system 800 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some instances, the computer system 800 can be a cloud computing node. The computer system 800 can be described in the general context of computer system executable instructions such as program modules executed by the computer system. Typically, program modules can include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. The computer system 800 can be implemented in a distributed cloud computing environment in which tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can reside in local and remote computer system storage media, including memory storage devices.

[0051] like Figure 8As shown, the computer system 800 has one or more central processing units (CPUs) 801a, 801b, 801c, etc. (collectively or collectively referred to as processor 801). Processor 801 can be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 801, also called processing circuitry, is coupled to system memory 803 and various other components via system bus 802. System memory 803 can include read-only memory (ROM) 804 and random access memory (RAM) 805. ROM 804 is coupled to system bus 802 and can include a basic input / output system (BIOS) that controls certain basic functions of computer system 800. RAM is a read-write memory coupled to system bus 802 for use by processor 801. System memory 803 provides temporary storage space for the operation of instructions during operation. System memory 803 can include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0052] Computer system 800 includes an input / output (I / O) adapter 806 and a communication adapter 807 coupled to a system bus 802. I / O adapter 806 may be a Small Computer System Interface (SCSI) adapter that communicates with a hard disk 808 and / or any other similar component. I / O adapter 806 and hard disk 808 are collectively referred to herein as mass storage 810.

[0053] Software 811 for execution on computer system 800 can be stored in mass storage 810. Mass storage 810 is an example of a tangible storage medium readable by processor 801, wherein software 811 is stored as instructions for execution by processor 801 to operate computer system 800, as described below with reference to the accompanying drawings. Examples of computer program products and the execution of such instructions are discussed in more detail here. Communication adapter 807 interconnects system bus 802 with network 812, which can be an external network, enabling computer system 800 to communicate with other such systems. In one embodiment, a portion of system memory 803 and mass storage 810 jointly store an operating system, which can be a coordinating... Figure 8 The functions of the various components shown can be used with any suitable operating system.

[0054] Additional input / output devices are shown connected to system bus 802 via display adapter 815 and interface adapter 816. In one embodiment, adapters 806, 807, 815, and 816 can be connected to one or more I / O buses connected to system bus 802 via an intermediate bus bridge (not shown). Display 819 (e.g., screen or display monitor) is connected to system bus 802 via display adapter 815, which can include a graphics controller and a video controller for improving performance in graphics-intensive applications. Keyboard 821, mouse 822, speaker 823, etc., can be interconnected to system bus 802 via interface adapter 816, which can include, for example, a super I / O chip integrating multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Therefore, as Figure 8 The computer system 800 configured includes: processing capabilities in the form of a processor 801, storage capabilities including system memory 803 and mass storage 810, input devices such as a keyboard 821 and a mouse 822, and output capabilities including a speaker 823 and a display 819.

[0055] In some embodiments, the communication adapter 807 can use any suitable interface or protocol to send data, such as an Internet minicomputer system interface (IMSI). The network 812 can be a cellular network, radio network, wide area network (WAN), local area network (LAN), or the Internet. An external computing device can connect to the computer system 800 via the network 812. In some instances, the external computing device can be an external web server or a cloud computing node.

[0056] It should be understood that Figure 8 The block diagram is not intended to indicate the computer system 800 including Figure 8 All the components shown. Instead, the computer system 800 is capable of including... Figure 8 Any suitable fewer or additional components not shown (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, the embodiments described herein with respect to computer system 800 can be implemented with any suitable logic, wherein, in various embodiments, the logic mentioned herein can include any suitable hardware (e.g., processor, embedded controller, or application-specific integrated circuit, etc.), software (e.g., applications, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0057] While specific embodiments of this disclosure have been described, those skilled in the art will recognize that many other modifications and alternative embodiments exist within the scope of this disclosure. For example, any functionality and / or processing capability described with respect to a particular system, system component, device, or device component can be performed by any other system, device, or component. Furthermore, while various illustrative implementations and architectures have been described according to embodiments of this disclosure, those skilled in the art will understand that many other modifications to the illustrative implementations and architectures described herein are also within the scope of this disclosure. Additionally, it should be understood that any operation, element, component, data, etc., described herein as being based on another operation, element, component, data, etc., can be additionally based on one or more other operations, elements, components, data, etc. Therefore, the phrase "based on" or variations thereof should be interpreted as "at least partially based on".

[0058] This disclosure can be a system, method, apparatus, and / or computer program product. A computer program product can include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of this disclosure.

[0059] A computer-readable storage medium can be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanically encoded devices (such as punched cards or raised structures in slots on which instructions are recorded), and any suitable combination of the foregoing. The computer-readable storage medium used herein should not be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0060] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, local area network, wide area network, and / or wireless network) to an external computer or external storage device. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, internetworking computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0061] Computer-readable program instructions used to perform the operations of this disclosure can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or connected to an external computer (e.g., via the Internet provided by an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can be personalized to execute computer-readable program instructions by utilizing status information from the computer-readable program instructions in order to perform aspects of this disclosure.

[0062] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0063] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more boxes of a flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, and / or other equipment to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of writing including instructions that implement aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0064] Computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device, thereby producing a computer-implemented process, such that the instructions that execute on the computer, other programmable apparatus or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0065] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, apparatuses, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram can represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than shown in the figures. For example, depending on the function involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0066] The description of various embodiments of this technology is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to existing technologies in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method, the method comprising: The processor receives a system architecture specification corresponding to the system design, as well as multiple topology variations of the system architecture specification; The system architecture diagram is determined based on the aforementioned system architecture specifications; The graphic embedding is determined based on the system architecture diagram; Each of the topological variants is classified as a feasible or infeasible architecture based on the graph embedding using a neural network-based classifier. The classification rules for each of the topological variants are extracted into feasible or infeasible architectures, and the extracted rules can be fed back into a neural network-based classifier to refine the classification of possible architectures into feasible and infeasible architectures. Construct a proxy model that performs simulation of a feasible architecture based on configuration options received along with the system architecture specification, and determines the key performance indicators (KPIs) of the feasible architecture based on the configuration options corresponding to the system architecture specification. Determine if the error rate of the predicted KPI is less than a threshold. If the determined error rate is greater than the threshold, identify any incorrectly classified architectures and repeat the steps of classification, extraction, determining the predicted KPI, and determining the error rate. Specifically, refine the neural network-based classifier based on any identified incorrectly classified architectures. When the determined error rate is less than a threshold, a subset of the feasible architectures is identified as system design candidates based on the predicted KPIs.

2. The method according to claim 1, wherein, Identifying the subset of feasible architectures as system design candidates based on the performance prediction includes: The feasible architectures are ranked based on the key performance indicators.

3. The method according to claim 1 or 2, wherein, Determining the graph embedding includes constructing an adjacency matrix based on the system architecture graph.

4. The method according to claim 1 or 2, wherein, Determining the graph embedding includes performing primitive-based embedding based on the system architecture graph.

5. The method according to claim 1, wherein, Extracting the classification rules includes: Construct a saliency map based on a subset of the classified topological variants; and Features in the saliency map are identified based on gradient-weighted class activation mapping (GradCAM++).

6. The method according to claim 5, wherein, The feature corresponds to one of a negation rule and an affirmation rule, wherein the feature does not exist in the subset of the classified topological variants corresponding to the saliency graph in the negation rule, and the feature exists in the subset of the classified topological variants corresponding to the saliency graph in the affirmation rule.

7. A system comprising: A memory containing computer-readable instructions; as well as One or more processors for executing the computer-readable instructions, the computer-readable instructions controlling the one or more processors to perform operations, the operations including: Receive system architecture specifications corresponding to the system design, and multiple topology variations of the system architecture specifications; The system architecture diagram is determined based on the aforementioned system architecture specifications; The graphic embedding is determined based on the system architecture diagram; Each of the topological variants is classified as a feasible or infeasible architecture based on the graph embedding using a neural network-based classifier. The classification rules for each of the topological variants are extracted into feasible or infeasible architectures, and the extracted rules can be fed back into a neural network-based classifier to refine the classification of possible architectures into feasible and infeasible architectures. Construct a proxy model that performs simulation of a feasible architecture based on configuration options received along with the system architecture specification, and determines the key performance indicators (KPIs) of the feasible architecture based on the configuration options corresponding to the system architecture specification. Determine if the error rate of the predicted KPI is less than a threshold. If the determined error rate is greater than the threshold, identify any incorrectly classified architectures and repeat the steps of classification, extraction, determining the predicted KPI, and determining the error rate. Specifically, refine the neural network-based classifier based on any identified incorrectly classified architectures. When the determined error rate is less than a threshold, a subset of the feasible architectures is identified as system design candidates based on the predicted KPIs.

8. The system according to claim 7, wherein, Identifying the subset of feasible architectures as system design candidates based on the performance prediction includes: The feasible architectures are ranked based on the key performance indicators.

9. The system according to claim 7, wherein, Determining the graph embedding includes constructing an adjacency matrix based on the system architecture graph.

10. The system according to claim 7, wherein, Determining the graph embedding includes performing primitive-based embedding based on the system architecture graph.

11. The system according to claim 7, wherein, Extracting the classification rules includes: Construct a saliency map based on a subset of the classified topological variants; and Features in the saliency map are identified based on gradient-weighted class activation mapping (GradCAM++).

12. The system according to claim 11, wherein, The feature corresponds to one of a negation rule and an affirmation rule, wherein the feature does not exist in the subset of the classified topological variants corresponding to the saliency graph in the negation rule, and the feature exists in the subset of the classified topological variants corresponding to the saliency graph in the affirmation rule.

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