Data processing method, computing device, and computer system

Abstract

Embodiments of the present application provide a data processing method, a computing device and a computer system. In the embodiments, a first cache node runs in a computer system, and the computer system is deployed with a computing device. The first cache node generates access request information based on an access instruction sent by a computing node. The access request information includes computing information. The access request information corresponds to a cache address of a local cache. The access request information and the cache address are sent to the computing device, so that the computing device accesses the local cache based on the cache address to respond to the access request information and perform computing processing on target data requested according to the computing information. The technical solution provided by the embodiments of the present application reduces the computing overhead of the computing node and improves the processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, computing device and computer system. Background Technology

[0002] Storage-compute separation technology refers to decoupling computation and storage, with different systems handling data storage and computation. Since data storage typically uses persistent storage located remotely, retrieving all data from this remote storage system for every computation would significantly reduce processing efficiency. To address this issue, storage-compute separation architecture emerged. This architecture uses a caching system as a bridge between the two systems, acting as a cache layer to solve the problem of all data needing to be fetched from the storage system. For example, frequently accessed or intermediate data can be stored in the cache system. If the cache system contains data that a compute node requests, the compute node can directly retrieve the data from the cache system and perform computation.

[0003] However, even with this storage separation architecture, the computational overhead of the compute nodes is still significant. Summary of the Invention

[0004] This application provides a data processing method, a computing device, and a computer system to solve the technical problem of high technical overhead of computing nodes in the prior art.

[0005] In a first aspect, embodiments of this application provide a data processing method applied to a first cache node, the first cache node running in a computer system, the computer system having a computing device deployed thereon; the method includes:

[0006] Based on the access command sent by the computing node, an access request information is generated; the access request information includes computing information.

[0007] Determine the cache address of the local cache corresponding to the access request information;

[0008] The access request information and the cache address are sent to the computing device so that the computing device can access the local cache based on the cache address to respond to the access request information and perform calculation processing on the target data requested for access according to the calculation information.

[0009] Secondly, this application provides a data processing method applied to a computing device, wherein the computing device is configured in a computer system, and the computer system runs a first cache node, the method comprising:

[0010] Obtain the access request information and cache address sent by the first cache node; the access request information includes computation information; the access request information is generated based on the access instruction sent by the computation node;

[0011] Access the local cache of the computer system based on the cache address;

[0012] Responding to the access request information, and performing calculations on the target data to be accessed according to the calculation information.

[0013] Thirdly, this application provides a computing device including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are invoked and executed by the processing component to implement the data processing method as described in the second aspect above.

[0014] Fourthly, this application provides a computer system including a processing component and a storage component; the processing component is used to connect to a computing device; the storage component stores one or more computer instructions; the one or more computer instructions are used to be invoked and executed by the processing component to run a first cache node and perform the data processing method as described in the first aspect above.

[0015] In this embodiment, a computing device is deployed in a computer system running a cache node. The computing node sends an access instruction to the cache node, and the cache node generates access request information based on the access instruction. The access request information includes computation information. Then, the cache address corresponding to the access request information is determined, and the access request information and the cache address are sent to the computing component device. The computing component device can then access the local cache based on the cache address. It responds to the access request information and performs computation processing on the requested target data according to the computation information. The technical solution of this embodiment provides storage-in-the-path computing capability, enabling online computation of requested data, thereby eliminating the need for computation processing by the computing node, reducing the computational overhead of the computing node, avoiding data transmission delays, and improving processing efficiency.

[0016] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This diagram illustrates a system architecture in which the technical solution of this application is applied.

[0019] Figure 2 A flowchart of one embodiment of a data processing method provided in this application is shown;

[0020] Figure 3 This illustration shows a schematic diagram of the SQE data structure in a practical application according to an embodiment of this application;

[0021] Figure 4a This illustration shows an interactive diagram of data reading in a practical application, based on an embodiment of this application.

[0022] Figure 4b This illustration shows an interactive diagram of data reading in a practical application, based on an embodiment of this application.

[0023] Figure 4c This illustration shows an interactive diagram of data writing in a practical application, according to an embodiment of this application.

[0024] Figure 5 This illustration shows an interactive diagram of a cache node accessing a computing device in a practical application, according to an embodiment of this application.

[0025] Figure 6 This illustration shows a queue mapping diagram of an embodiment of this application in a practical application;

[0026] Figure 7 A flowchart of yet another embodiment of a data processing method provided in this application is shown;

[0027] Figure 8 This invention provides a schematic diagram of the structure of one embodiment of a data processing apparatus.

[0028] Figure 9 This illustration shows a structural schematic diagram of yet another embodiment of a data processing apparatus provided in this application;

[0029] Figure 10 This application provides a schematic diagram illustrating the structure of one embodiment of a computing device.

[0030] Figure 11 A schematic diagram of the structure of one embodiment of a computer system provided in this application is shown. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0032] In some of the processes described in the specification, claims, and accompanying drawings of this application, multiple operations appearing in a specific order are included. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or may be executed in parallel. The operation numbers, such as 101, 102, etc., are merely used to distinguish different operations and do not themselves represent any execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first," "second," etc., in this document are used to distinguish different messages, devices, modules, etc., and do not represent a chronological order, nor do they limit "first" and "second" to different types.

[0033] To facilitate understanding of the technical solution of this application, the technical terms that may be involved in this application will be explained below:

[0034] External devices refer to devices in a computer system other than the host computer, including input devices (such as keyboards and mice), output devices (such as monitors and printers), and external storage devices (such as hard disks, floppy disks, and optical disks). External devices can be categorized into character devices, block devices, and network communication devices based on their operating methods. I / O (Input / Output) operations describe the computer system's access to external devices, and may include data I / O (reading and writing data) and network I / O (network requests and responses). The computing device involved in the embodiments of this application is a type of external device used to accelerate computational processing.

[0035] Kernel Space and User Space: The core of an operating system is the kernel, which has access to a protected memory space and full access to underlying hardware devices. To ensure kernel security, modern operating systems generally prevent user processes from directly manipulating the kernel. The specific implementation typically involves the operating system dividing the virtual address space into two parts: kernel space and user space. Applications running in user space are called user-mode applications, and programs running in kernel space are called kernel-mode applications. Applications running in user space can access kernel space through system calls, where they can perform operations such as data reading and writing, and memory allocation. I / O operations involve accessing kernel space from user space via system calls; that is, the application only initiates the I / O operation call, and the actual I / O operation is performed by the kernel program.

[0036] Virtualized devices: External devices are virtualized using I / O virtualization technology.

[0037] AIO (Asynchronous I / O): Asynchronous I / O means that after an application submits an access request, it does not need to wait for the I / O operation to complete, but can continue to process other things. Once the I / O operation is complete, the application will be notified in some way.

[0038] io_uring: An asynchronous I / O technology that provides a buffered queue that can be shared between user space and kernel space to avoid memory copying. io_uring registers memory in kernel space, which can be mapped to user space using mmap (a memory map). Communication between user space and kernel space is achieved through the buffered queue within memory. This buffered queue can be a circular queue, allowing both user space and kernel space to read and put data. The buffered queue can include a Submission Queue (SQ) and a Completion Queue (CQ). Elements in the SQ are SQEs (Submission Queue Entry), and elements in the CQ are CQEs (Completion Queue Entry). SQEs and CQEs can store submitted request information or indexes of those requests, with the request information stored in an additional array.

[0039] Virtio is an I / O paravirtualization technology that abstracts a set of general-purpose external devices within a paravirtualized hypervisor. It's a front-end / back-end architecture including device drivers, virtualized devices, and virtualization queues (Vrings) for communication between the device drivers and virtualized devices. Virtualized devices are obtained by simulating external devices. In a virtual machine environment, the device driver resides within the virtual machine and is the corresponding driver for the virtualized device. The virtualized devices are obtained by the hypervisor based on the virtualization of external devices. The external devices seen in the virtual machine are those virtualized by the hypervisor. The virtualization queue can be a circular queue, from which both device drivers and virtualized devices can read and write data. The device driver saves access request information to the virtual queue and then notifies the virtualized device, which can then retrieve and process the access request information from the virtual queue. The virtualization queue may include, for example, an available ring and a used ring. The available ring and the used ring may store operation addresses or indexes of operation addresses. The operation addresses are stored in an additional data table, and each operation address may point to a memory space.

[0040] Virtual machine: A virtual machine is a complete computer system with full hardware system functionality simulated by software on a physical host, running in a completely isolated environment. The physical host is the host relative to the virtual machine, and the virtual machine is the guest relative to the physical host.

[0041] Cloud computing: Cloud computing is one of the fastest-growing trends in computer technology, involving the provision of managed services over a network. A cloud computing environment provides computing and storage resources as a service to end users. End users can request processing from the provided services. The processing capacity of a service is typically limited by the configured resources. Cloud computing is a service delivery model designed to enable on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing power, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and deployed with minimal management effort or interaction with the service provider.

[0042] VFS (Virtual File System): It uses standard Unix system calls to read and write different file systems located on different physical media, thus providing a unified operating interface and application programming interface for various file systems.

[0043] Block layer: The module interface in kernel space used to access storage devices.

[0044] A file system is a system that organizes and allocates space on file storage devices, and is responsible for storing, protecting, and retrieving files.

[0045] PCIe (Peripheral Component Interconnect Express): A high-speed serial computer expansion bus standard.

[0046] MEM (memory): storage medium.

[0047] PMEM (Persistent Memory): Persistent storage medium.

[0048] NVMe (Non-Volatile Memory express): A non-volatile memory host controller interface specification for accessing non-volatile storage media attached via the PCIe bus.

[0049] SSD (Solid State Disk): Solid State Drive. NVMe hard drive refers to a solid state drive based on NVMe.

[0050] POSIX (Portable Operating System Interface): Portable operating system interface.

[0051] HDFS: Hadoop Distributed File System, refers to a distributed file system designed to run on commodity hardware. The cache nodes involved in this application's embodiments can refer to the data nodes in HDFS responsible for data storage.

[0052] API: Application Programming Interface.

[0053] The technical solutions of this application can be applied to storage-compute separation scenarios using a storage-separation architecture, particularly in cloud computing scenarios with storage-compute separation. With the development of cloud computing and cloud storage, scalable elasticity has been provided for both computing resources and persistent storage. However, the bandwidth of cloud storage backends, which typically serve as persistent storage, is limited. If the data required for computation needs to be retrieved from the cloud storage backend every time, processing efficiency will be significantly reduced. Furthermore, if intermediate computation results need to be written to the cloud storage backend every time, it not only increases unnecessary overhead but also significantly reduces processing efficiency. Therefore, to solve this problem, a storage-separation architecture has emerged. This architecture uses a cache layer to address the issue of all data needing to be retrieved from the backend, for example, storing hot data and intermediate data in the cache layer.

[0054] The cache layer can be implemented by a single cache node or a distributed file system consisting of multiple cache nodes. Similarly, the computing layer for data computation can be implemented by a single computing node or a distributed computing system consisting of multiple computing nodes. This application does not impose any restrictions on the distributed computing system.

[0055] The inventors discovered that even with a distributed file system providing a storage separation solution, the computational overhead of computing nodes remains relatively high. Therefore, they considered whether online computation could be performed on data during access, reducing the computational overhead of computing nodes and avoiding transmission delays, thus significantly improving computational efficiency. To achieve this technical solution, the inventors, after a series of studies, proposed the technical solution of this application. A computing device is deployed in the computer system where the cache node resides. The computing node can send access commands using predefined interfaces supported by the cache node. Based on the access command, the cache node generates access request information, which includes computational information. Then, the cache address corresponding to the access request information is determined, and the access request information and cache address are sent to the computing device. The computing device can then access the local cache based on the cache address to respond to the access request information and perform computational processing on the requested target data according to the computational information. The computing devices and cache nodes are deployed in the computer system. The computing devices can directly access the local cache of the cache nodes and perform calculations on the requested target data directly without the need for the computing nodes to execute the calculations. This enables computation to be performed simultaneously with the access, which is called storage-in-the-path computation. Therefore, the computing devices provide storage-in-the-path computation capabilities, enabling online computation of the requested data without the need for computation processing by the computing nodes. This reduces the computational overhead of the computing nodes, avoids problems such as data transmission delays, and improves processing efficiency.

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] Figure 1 This diagram illustrates a system architecture in which the technical solution of this application can be applied. Compute node 101 can send access commands to cache node 102. Cache node 102 can use one or more storage media 103, such as MEM, PMEM, and / or NVMe hard drives, as local caches to cache hot data or intermediate data in storage system 100. Storage system 100 can use a unified and reliable persistent storage solution, such as cloud storage or other types of network storage systems. Cache node 102 can access storage system 100 through the API (Application Programming Interface) corresponding to storage system 100.

[0058] In this system, cache node 102 serves as an intermediate cache layer for storing at least a portion of the data in storage system 100. The cache layer can be implemented using a single cache node 102. However, in practical applications, it can also be implemented as a distributed file system, consisting of multiple cache nodes 102. Figure 1 As shown in the image.

[0059] In the case of a distributed file system, data computation can be performed by a distributed computing system. The distributed computing system can distribute data computation tasks to each computing node 101. Each computing node 101 can send access commands to the corresponding cache node based on the data computation tasks distributed by the control node. To implement the technical solution of this application, a predefined interface can be pre-configured. Computing node 101 can access cache node 102 by calling the predefined interface and trigger the execution of the technical solution of this application. Of course, this predefined interface can be compatible with existing interfaces to implement the original access process. For example, if the distributed file system is HDFS, this predefined interface can be the API provided by HDFS for upper-layer systems to access HDFS.

[0060] In practical applications, compute node 101 and cache node 102 can run on the same computer system, or they can run on different computer systems. Different cache nodes 102 or different compute nodes 101 can run on the same computer system or different computer systems; this application does not limit this. The computer system where cache node 102 resides can be connected to compute device 104 via I / O interface. Computation device 104, as an external device, can provide data computation functions to achieve computation acceleration. It should be noted that... Figure 1 The system architecture diagram is a logical schematic and does not represent the actual hardware structure.

[0061] The cache node 102 can run in a virtual machine built on a computer system. Of course, the compute node 101 can also run in a virtual machine built on a computer system. This application does not limit this.

[0062] The components included in the host portion of the computer system of this application may be distributed on one or more physical machines. This application does not limit this, and its specific implementation structure will be described in the following embodiments.

[0063] The implementation details of the technical solutions in the embodiments of this application are described in detail below.

[0064] Figure 2This application provides a flowchart of one embodiment of a data processing method. The technical solution of this embodiment is executed by a first cache node, which runs in a computer system. The computer system deploys computing devices; these computing devices are external devices of the computer system and can be connected to the host portion of the computer system via I / O interfaces, etc. The method may include the following steps:

[0065] 201: Generate access request information based on the access command sent by the compute node.

[0066] The access request information may include computational information, as well as access operation data. The computational information may be included in the access instruction and provided by the computing node. This computational information may include, for example, operators indicating the data computation method, and may consist of operators and parameters.

[0067] The access instructions can include data write instructions or data read instructions. For a data write instruction, it can contain the target data to be written. This target data can be included in the access operation data. Alternatively, the cache node can store the target data in target memory, which can be obtained by the first cache node in the computer system. The access operation data can include the operation address corresponding to the target data in the target memory, pointing to the memory space of the target data in the target memory. For a data read instruction, the access operation data can include a data identifier and, in addition, an operation address in the target memory, used to store the target data so that the cache node can retrieve it. Similarly, the operation address points to the memory space in the target memory. Depending on the storage medium type, such as for MEM or PMEN, the operation address can be a memory address; for NVMe hard drives, the operation address can include a data block identifier, as well as the starting address of the target data within the data block and the data length, etc.

[0068] Optionally, a predefined interface can be provided for the compute nodes, which then call the predefined interface to send access commands. The first cache node can generate access request information based on the access commands sent by the compute nodes using the predefined interface. The first cache node can generate the access request information and execute the technical solution of this embodiment to perform in-path computation only if it detects that the compute nodes have sent access commands using the predefined interface. If the compute nodes have not sent access commands using the predefined interface, only the access operation can be performed without in-path computation. The predefined interface can be an API that allows the compute nodes to access the first cache node.

[0069] 202: Determine the cache address of the local cache corresponding to the access request information.

[0070] Local caching can be implemented using storage media such as MEM, PMEM, and / or NVMe hard drives.

[0071] 203: Send the access request information and cache address to the computing device.

[0072] The computing device can access the local cache based on the cache address to respond to the access request information and perform calculations on the target data requested for access according to the calculation information.

[0073] In this embodiment, the computing node can send access commands through a predefined interface, thereby pushing computing information down to the computing device through the cache node. The computing device then executes the access operation and performs computation processing on the requested target data. The computing device and the cache node are deployed in the computer system. The computing device can directly access the local cache of the cache node and perform computation processing on the requested target data directly, without the need for the computing node to execute the operation. This achieves computation during access, i.e., storage-in-the-path computation. Therefore, this embodiment provides storage-in-the-path computation capability through a predefined interface and computing device, enabling online computation of requested data without the need for computation processing by the computing node. This reduces the computational overhead of the computing node, avoids data transmission delays, and improves processing efficiency.

[0074] In some embodiments, the access request information may include the operation address corresponding to the target memory of the first cache node; the computing device is further configured to write the calculation result corresponding to the target data into the target memory based on the operation address; the method may further include: obtaining the calculation result from the target memory.

[0075] The calculation result may include a success message or a failure message. In addition, for data read instructions, it may also include the target data to be accessed or the address of the target data in the target memory.

[0076] The first cache node can retrieve the computation results from the target memory and can also feed the computation results back to the compute node.

[0077] The first cache node runs in user space. Since user space cannot directly access computing devices, it needs to access kernel space through system calls. Access to computing devices is then achieved in kernel space. To improve access efficiency and further processing efficiency, the inventors discovered that io_uring technology enables communication between user space and kernel space, avoiding memory copying. Virtio technology, with its semi-virtualization approach, accesses external devices through device drivers, also avoiding memory copying. The inventors wondered if combining these two technologies could improve access efficiency. However, they found that virtio technology supports block devices, network devices, and other device types. Drivers for these devices expose interfaces for these device types to the operating system. If an application accesses a virtualized device using io_uring technology, the access request must first be converted into a request corresponding to the external device's device type, and then the request corresponding to the device type must be converted into an element in the virtio ring. This still requires request mapping and memory copying, increasing access latency and reducing access efficiency. Further investigation by the inventors revealed that both io_uring and virtio technologies utilize shared queues. Based on this discovery, a device driver corresponding to a computing device can be created in the computer system. This device driver runs in kernel space, and kernel space and user space share a buffer queue in the target memory. The virtualized device obtained through computing device virtualization shares a virtualization queue with the device driver. Therefore, in some embodiments, the user space and kernel space share a buffer queue in the target memory, and the computing device corresponds to a device driver running in kernel space. The virtualized device is obtained through computing device virtualization; the virtualized device and device driver share a virtualization queue. Sending access request information and the cached address to the computing device can include:

[0078] The access request information and cache address are submitted to the buffer queue. The device driver retrieves the access request information and cache address from the buffer queue and maps them to the virtualization queue. The virtualization device retrieves the access request information and cache address from the virtualization queue and sends them to the computing device.

[0079] In one implementation, kernel space and user space can refer to the kernel space and user space of a virtual machine created by the computer system. Of course, kernel space and user space can also refer to the kernel space and user space provided by the physical host of the computer system, etc.

[0080] In one implementation, with the virtual machine providing kernel space and user space, a computing device can virtualize and generate multiple virtualized devices according to actual needs, and correspond to different device drivers, in order to support communication with cache nodes in multiple virtual machines, etc.

[0081] Kernel space and user space can be accessed using io_uring technology. Device drivers, virtualized devices, and virtualized queues can be created using virtio technology.

[0082] Furthermore, the technical solutions of this application embodiment can be applied to cloud computing scenarios. The computer system is a hardware device provided by the cloud computing system, and the created virtual machine can, for example, serve as a cloud server. One or more applications for performing different processing operations can run within the virtual machine, or it can be a cloud application. The above embodiment, through the mapping between the buffer queue and the virtualization queue, only requires a single request mapping, avoiding multi-level request mapping and memory copying, thus enabling the first cache node to access the computing device and improving access efficiency.

[0083] In some embodiments, the virtualization device can submit the computation results of the computing device to a virtualization queue, and the device driver can obtain the computation results from the virtualization queue and map the computation results to a buffer queue;

[0084] The calculation result can be obtained from the target memory by obtaining the calculation result from the buffer queue.

[0085] In some embodiments, to further improve access efficiency, the device driver may keep the operation address in the access request information unchanged and map the access request information to the virtualization queue.

[0086] In other words, the operation address corresponding to the access request information remains unchanged for both the buffer queue and the virtualization queue. This operation address points to a memory space in the target memory, so that external devices can directly access the target memory without performing memory copying, thus enabling the processing of the request information.

[0087] In some embodiments, the buffer queue and the virtualization queue may each include two queues. The buffer queue includes a first queue and a second queue; the virtualization queue includes a third queue and a fourth queue; the calculation result may be specifically submitted to the fourth queue; the first cache node may submit the access request information to the first queue, and the device driver obtains the access request information from the first queue.

[0088] The device driver can map access request information to a virtualization queue or to a third queue.

[0089] The device driver can retrieve response results from the virtualization queue, or retrieve computation results from the fourth queue.

[0090] The device driver can map the computation results to a buffer queue or to a second queue.

[0091] The first and third queues store the data for the operations performed, while the second and fourth queues store the results returned after the operations are completed. Specifically, the first queue is used for writing to the first cache node and reading from the device driver; the second queue is used for writing to the device driver and reading from the first cache node; the third queue is used for writing to the device driver and reading from the virtualized device; and the fourth queue is used for writing to the virtualized device and reading from the device driver.

[0092] In practical applications, buffer queues can be implemented based on io_uring technology, with the first queue being SQ and the second queue being CQ; virtualization queues can be implemented based on virtio technology, with the third queue being Available Ring and the fourth queue being Used Ring.

[0093] SQ, CQ, Available Ring, and Used Ring can all be circular queues, with dequeues from the tail and enqueues from the head. For example, the first cache node can generate an SQE based on the access request information and add it to the tail of the SQ queue. The device driver retrieves the SQE from the head of the SQ queue to obtain the access request information. Similarly, the device driver can generate a CQE based on the response result and add it to the tail of the CQ queue. The target application retrieves the CQE from the head of the CQ queue to obtain the calculation result, etc.

[0094] The SQE can include access operation data and computation information. Therefore, the buffer queue can also include an array to store access operation data and computation information, or pointers to such data. The SQE can store index information pointing to this array. Furthermore, based on the io_uring standard, the SQE data structure can include multiple fields, such as an opcode field to store the opcode, a flags field to store the flag set, an fd field to store the file descriptor, an addr field to store access operation data and computation information or index information pointing to the array, and a user_data field to store user data. Of course, this application does not limit the specific data structure of the SQE.

[0095] This array can be an iov (i / o Virtualization) array, but this application does not limit it to this. When the array stores pointers, each entry in the array points to the memory space that stores access operation data and computation information. For ease of understanding, see [link to relevant documentation]. Figure 3 In the SQE diagram, the addr field of SQE can point to the iov array. Each entry in the iov array stores a pointer, which can point to a memory space that stores different information. For example, the memory space pointed to by IOV[0] can store the following information: Sub_op: represents the calculation information, such as the operator; Parameter_iov_num: represents the number of iov entries corresponding to the parameters required by the operator; Buffer_iov_num: represents the number of iov entries corresponding to the memory space corresponding to the operator; Cache_iov_num: represents the number of iov entries corresponding to the local cache corresponding to the operator; IOV[1]~[2], the memory space pointed to by the two iov entries stores the parameters required by the operator, etc.; the memory space pointed to by IOV[3] contains relevant information (data buffer), such as the operation address; the memory space pointed to by IOV[4] is used to store the relevant description information of the local cache, such as the cache type (MEM, PMEM, NVMe hard disk), cache address, etc.

[0096] Of course, depending on the practical application, the corresponding entries in the iov array can be empty if no information is needed. It should be noted that this is merely an example illustrating the implementation of the iov array and should not be taken as a limitation of this application.

[0097] The array information corresponding to the iov array can be mapped from the buffer queue to the virtualization queue. Optionally, only the index information of the addr field in SQE can be mapped to the virtualization queue, so that the index information mapped in the virtualization queue can be used to index the iov array to obtain the access operation data. Of course, the access operation data corresponding to the iov array can also be mapped to the virtualization queue, so that the access operation data can be obtained directly from the virtualization queue. This application does not limit this.

[0098] CQE is used to store the execution result, such as the return value corresponding to success or failure. Based on the io_uring technical standard, CQE can be composed of user_data field, flags field and res field storing calculation results, etc., and this application does not limit it.

[0099] The Available Ring stores the addresses of operations to be processed or their indexes. These addresses can be stored in a descriptor table, each pointing to a memory space. Therefore, each entry in the Available Ring points to a memory space. Based on the virtio standard, the data structure of each descriptor in the Descriptor Table can include an `addr` field to store the operation address, a `len` field to store the length of the corresponding memory space, a `flags` field to store control information, and a `next` field to store the next descriptor identifier. The data structure of each entry in the Available Ring can include, for example, control information (`flags`), the next descriptor identifier, and the current descriptor identifier; however, this application does not limit this.

[0100] The Used Ring is used to store the addresses of completed operations or index information of those addresses. Based on the virtio standard, the data structure of each entry in the Used Ring, compared to the Available Ring, can also include a len field to store memory length, etc., although this application does not impose any limitations on this.

[0101] Based on io_uring technology, the first cache node can specifically use the io_uring interface to submit access request information to the buffer queue. The io_uring interface is a system call interface implemented by io_uring technology, thereby enabling reading and writing to the buffer queue.

[0102] In some embodiments, the device driver may convert the access request information into a format according to the first format requirement corresponding to the virtualization queue and submit it to the virtualization queue; and convert the calculation result into a format according to the second format requirement corresponding to the buffer queue and submit it to the buffer queue.

[0103] The first format requirement specifies the data structure of each entry in the virtualization queue, thereby enabling format conversion of access request information. The second format requirement specifies the data structure of each entry in the buffer queue, thereby enabling format conversion of calculation results.

[0104] The format mapping relationship can be pre-configured, that is, the mapping relationship between the fields contained in each entry in the buffer queue and the fields contained in each entry in the virtualization queue, so that the mapping can be realized. The mapping relationship can be set according to actual needs, and this application does not impose specific limitations on it.

[0105] As described above, access commands issued by computing nodes can be divided into data read commands and data write commands. In some embodiments, determining the cache address of the local cache corresponding to the access request may include:

[0106] If the access instruction is a data read instruction, determine whether the target data to be accessed is located in the local cache; if the target data to be accessed is located in the local cache, determine the cache address of the target data in the local cache.

[0107] In some embodiments, determining whether the target data to be accessed is located in the local cache may include: querying metadata information to determine whether the target data to be accessed is located in the local cache.

[0108] This could involve querying locally stored metadata, or, in a distributed file system scenario, querying metadata from the control node.

[0109] The metadata information can store information such as the cache address of different data in the local cache.

[0110] In some embodiments, the access request information may include the operation address of the target memory corresponding to the first cache node, and the computing device is used to write the result data obtained by computing on the target data into the target memory; then the method may further include: obtaining the result data from the target memory, and feeding the result data back to the computing node.

[0111] To facilitate understanding of this data reading process, such as Figure 4a In the interactive diagram shown, the computing node sends an access instruction 11 to the first cache node. The access instruction may include the operators used for data computation. The first cache node 402 can query metadata information 12 based on the data identifier of the target data to be accessed, determine whether the target data is stored in the local cache, and obtain the cache address 13 of the target data in the local cache. The target data may hit multiple data blocks, and the cache addresses corresponding to these multiple data blocks can be sent to the first cache node 402 in list form, specifically as a scatter-gather list (SGL, a data organization format).

[0112] The first cache node can send the operator, cache address, and operation address of the target memory 403 corresponding to the first cache node 402 to the computing device 14.

[0113] The computing device reads the target data 15 from the local cache, performs calculations on the target data according to the operators to obtain the result data, and then sends the result data to the target memory 16.

[0114] The computing device can notify the first cache node of the computing result 17; after the first cache node obtains the computing result, it can notify the computing node of the computing result 18, and can also retrieve the result data from the target memory and feed it back to the computing node.

[0115] In some embodiments, the target data may not be stored in the local cache, so the method may further include:

[0116] If the target data requested is not in the local cache, determine the storage space allocated for the target data in the local cache; read the target data from the storage system or the second cache node; write the target data to the storage space; and use the cache address corresponding to the storage space as the cache address of the target data in the local cache.

[0117] If the target data is not present in the local cache, a corresponding storage space can be allocated for it in the local cache first. The target data can then be read from the storage system and stored in that storage space. In a distributed file system implementation, the target data can also be read from a second cache node that stores the target data. The cache address corresponding to this storage space is also the cache address of the target data in the local cache.

[0118] In some embodiments, as described above, determining whether the target data to be accessed is located in the local cache may include: querying metadata information to determine whether the target data to be accessed is located in the local cache;

[0119] After writing the target data into the storage space, the method may further include: updating metadata information based on the cache address and the target data.

[0120] For ease of understanding, such as Figure 4b In the interactive diagram of the data reading process shown, the computing node sends an access instruction 21 to the first cache node. The access instruction may include the operators used for data computation. The first cache node queries metadata information 22 and determines that the target data is not stored in its local cache. If so, it can allocate corresponding storage space 23 for the target data. The first cache node sends a read request 24 to the storage system or the second cache node to read the target data 25, and then stores the target data in its local cache 26. The cache address corresponding to this storage space is the cache address of the target data in the local cache.

[0121] The first cache node can send the operator, cache address, and the operation address of the target memory corresponding to the first cache node to the computing device 27.

[0122] The computing device reads the target data 28 from the local cache, performs calculations on the target data according to the operators to obtain the result data, and then sends the result data to the target memory 29.

[0123] The computing device can notify the first cache node of the computing result 30; after the first cache node obtains the computing result, it can notify the computing node of the computing result, and it can also retrieve the result data from the target memory and feed it back to the computing node.

[0124] In some embodiments, determining the cache address of the local cache corresponding to the access request may include:

[0125] When the access instruction is a data write instruction, determine the storage space allocated for the target data in the local cache; use the cache address of the storage space as the cache address corresponding to the access request.

[0126] In some embodiments, the method may further include: saving the target data requested to be written by the computing node to the target memory corresponding to the first cache node; the access request information includes the operation address of the target data in the target memory; the computing device is used to obtain the target data from the target memory based on the operation address, and write the result data obtained by computing the target data based on the cache address into the storage space.

[0127] In some embodiments, the method may further include: updating metadata information based on the target data and the cache address; the metadata information is used to query whether the target data is stored in the local cache.

[0128] In some embodiments, the method may further include: locking the target data to be written when the access request is a data write request; and unlocking the target data when the target data is successfully written.

[0129] Locking the target data to be written can involve locking the file to which the target data is to be written. Locking can prevent data inconsistencies and ensure that other nodes do not perform write operations on the file until the operation is complete.

[0130] Among these measures, locking the target data to be written can be done, for example, by setting a lock flag in the metadata information. When the access request is a data write request, the process can first check whether the target data has a lock flag set in the metadata information. If so, the process can end; otherwise, the target data to be written can be locked.

[0131] In some embodiments, the method may further include synchronizing the result data stored in the local cache to the storage system.

[0132] For ease of understanding, such as Figure 4cIn the interactive diagram of the data writing process shown, the computing node sends an access instruction 31 to the first cache node. The access instruction may include the operator used for data computation. The first cache node can query metadata information 32, lock the target data to be written, and allocate the corresponding storage space 33.

[0133] The first cache node can send operators, the cache address of the storage space, and the operation address of the target memory corresponding to the first cache node to the computing device 34.

[0134] The computing device retrieves the target data from the target memory and performs calculations on the target data according to the operators to obtain the result data 35; the computing device writes the result data into the storage space of the local cache 36.

[0135] The computing device can notify the first cache node of the computing result 37. After receiving the computing result, the first cache node can update the metadata information 38 and can feed the computing result back to the computing node 39.

[0136] In addition, if a synchronization operation is required, the first cache node can synchronize the result data written to the local cache to the storage system 40.

[0137] Furthermore, as another embodiment, when the access command is a data write command, the target data requested by the compute node can be saved to the storage system. That is, the target data can be directly written to the backend storage system, supporting full data write-through.

[0138] In one or more of the above embodiments, the computing device can directly access the local cache. For the local cache to be MEM or PMEM, the computing device can access the local cache through the PCIe channel. For NVMe hard drives, the computing device can access the local cache through the P2P (peer to peer) channel. Therefore, the computing device can directly manage data without going through the file system.

[0139] In this embodiment, the first cache node can directly parse metadata information to access the computing device, enabling the first cache node to utilize the computing power of the computing device to perform online data calculation, achieving the purpose of on-the-path calculation and improving processing efficiency.

[0140] Furthermore, in this embodiment, the computing device can access various storage media such as MEM, PMEM, and NVMe hard drives that serve as local caches in the first cache node, and the target data to be processed can be distributed across multiple storage media, thereby improving scalability.

[0141] In this embodiment of the application, by defining a predefined interface for computing nodes, support is provided for computing nodes to perform on-the-path computing using computing devices.

[0142] In this embodiment of the application, when the computing device is virtualized into a virtualized device, the operation information such as operators, cache addresses and operation addresses can be directly sent to the computing device by the device driver without touching the operation information. The computing device can determine the specific type of execution, etc. Therefore, when the capabilities of the computing device are extended, the uniformity for the predefined interface can be maintained.

[0143] In a practical application, the first cache node can run in the user space of a virtual machine, while the computing device has a corresponding device driver running in the kernel space of the virtual machine. The user space and kernel space share a buffer queue in the target memory, and the computing device is virtualized to obtain a virtualized device. The virtualized device and the device driver share a virtualized queue. For example, taking the implementation of this application's technical solution based on io_uring and virtio technologies, see [link to relevant documentation]. Figure 5 In the interaction diagram shown, the compute node can send access commands to the virtual machine (VM) through a predefined interface. The first cache node running in the VM's user space, based on the access command, queries metadata information, generates access request information, and determines the corresponding local cache address. Then, it can call the `io_uring` interface to submit the access request information and cache address to the buffer queue `io_uring` in the target memory pre-registered in the VM's kernel space. The buffer queue can include SQ and CQ. The access request information and cache address are specifically submitted to the SQ. The device driver running in kernel space, as a kernel program, can access this buffer queue and obtain the access request information and cache address. The device driver can then perform format conversion, keeping the corresponding operation address in the target memory unchanged, to map the access request information and cache address from the SQ to the virtualization queue `vring`. A mapping diagram can be shown as follows. Figure 6 As shown in the diagram, the virtualization device, also known as the virtio device, can obtain access request information and cache addresses from the virtualization queue. The computing device then accesses the local cache based on the cache addresses to respond to the access request information and performs computation processing on the requested target data according to the computation information.

[0144] The virtio device can also submit the response result to the virtualization queue. The device driver can then obtain the response result from the virtualization queue and map it to the buffer queue, specifically to the CQ. The target application can then obtain the response result from the buffer queue, i.e., the CQ.

[0145] Among them, computing devices can access NVMe hard drives as local caches through P2P channels, and access MEN or PMEM as local caches through PCIe channels.

[0146] Among them, io_uring serves as the interface between user space and kernel space on the VM. The number of SQ / CQ pairs can be determined by software, and any SQ / CQ can be selected for writing, etc. The device driver in the kernel space maps the SQE / CQE of io_uring to vring, and the number of vring can be determined in combination with the number of CPU cores, etc.

[0147] Virtualization devices can exist in the form of standard PCIe or MMIO (Memory-mapped I / O) devices, and are responsible for the corresponding processing.

[0148] The target memory used in io_uring can be registered in the kernel space in advance. The device driver is responsible for the format conversion between io_uring and vring, but will not modify the operation address. Thus, the virtualization device can directly access the target memory for processing, avoiding multiple memory copies of data.

[0149] Figure 7 This is a flowchart illustrating another embodiment of a data processing method provided by this application. This embodiment can be executed by a computing device. The solution is described from the perspective of computing device execution. It should be noted that the relevant operations performed by the computing device have been described in detail in one or more of the above embodiments, and will not be repeated here. The computing device is configured in a computer system, and the computer system runs a first cache node. The method may include the following steps:

[0150] 701: Get the access request information and cache address sent by the first cache node.

[0151] The access request information includes computation information; the access request information is generated based on the access instructions sent by the computing node.

[0152] The access request information and cache address can be obtained from the virtualization device and the corresponding device driver obtained through computing device virtualization.

[0153] 702: Access the computer system's local cache based on the cache address.

[0154] 703: Responds to the access request information and performs calculations on the target data requested for access according to the calculation information.

[0155] In some embodiments, the access request information may include an operation address; responding to the access request information and performing calculations on the target data to be accessed according to the calculation information may include:

[0156] When the access instruction is a data read instruction, the corresponding target data is retrieved from the local cache based on the cache address;

[0157] The target data is processed according to the calculation information to obtain the result data;

[0158] The result data is stored in the target memory corresponding to the operation address; the first cache node is used to retrieve the result data from the target memory.

[0159] In some embodiments, the access request information may include an operation address; responding to the access request information and performing calculations on the target data to be accessed according to the calculation information may include:

[0160] When the access instruction is a data write instruction, the target data to be written is obtained from the operation address;

[0161] The target data is processed according to the calculation information to obtain the result data;

[0162] Write the result data to the local cache according to the cache address.

[0163] Figure 8 This application provides a schematic diagram of the structure of a data processing apparatus according to one embodiment. The apparatus can be implemented as a first cache node, which runs in a computer system, and the computer system deploys computing devices. The apparatus may include:

[0164] The information generation module 801 is used to generate access request information based on the access instructions sent by the computing node; the access request information includes computing information.

[0165] Address determination module 802 is used to determine the cache address of the local cache corresponding to the access request information;

[0166] The information sending module 803 is used to send access request information and cache address to the computing device, so that the computing device can access the local cache based on the cache address to respond to the access request information and perform calculation processing on the target data requested for access according to the calculation information.

[0167] In some embodiments, the access request information includes the operation address corresponding to the target memory of the first cache node; the computing device is further configured to write the calculation result corresponding to the target data into the target memory based on the operation address; the device may further include: a result acquisition module, configured to acquire the calculation result from the target memory.

[0168] In some embodiments, the first cache node runs in user space, and user space and kernel space share a buffer queue in the target memory. The computing device has a corresponding device driver running in kernel space. The computing device is virtualized to obtain a virtualized device. The virtualized device and the device driver share a virtualized queue.

[0169] Specifically, the information sending module submits the access request information and the cache address to a buffer queue. The device driver retrieves the access request information and the cache address from the buffer queue and maps them to a virtualization queue. The virtualization device retrieves the access request information and the cache address from the virtualization queue and sends them to the computing device. In some embodiments, the address determination module specifically determines whether the target data to be accessed is located in the local cache when the access instruction is a data read instruction; if the target data to be accessed is located in the local cache, it determines the cache address of the target data in the local cache.

[0170] In some embodiments, the address determination module is further configured to determine the storage space allocated for the target data in the local cache when the target data to be accessed is not in the local cache; read the target data from the storage system or the second cache node; write the target data into the storage space; and use the cache address corresponding to the storage space as the cache address of the target data in the local cache.

[0171] In some embodiments, the access request information includes the operation address of the target memory corresponding to the first cache node, and the computing device is used to write the result data obtained by computing and processing the target data into the target memory;

[0172] The device may also include a data acquisition module for obtaining result data from the target memory.

[0173] In some embodiments, the address determination module determines whether the target data to be accessed is located in the local cache by: querying metadata information to determine whether the target data to be accessed is located in the local cache;

[0174] The device may also include a metadata update module for updating metadata information based on the cache address and the target data.

[0175] In some embodiments, the address determination module may specifically determine the storage space allocated for the target data in the local cache when the access instruction is a data write instruction; the cache address of the storage space is used as the cache address corresponding to the access request. This may involve querying metadata information to determine the allocated storage space in the local cache.

[0176] In some embodiments, the information generation module is further configured to save the target data requested to be written by the computing node to the target memory corresponding to the first cache node; the access request information includes the operation address of the target data in the target memory; the computing device is configured to obtain the target data from the target memory based on the operation address, and write the result data obtained by computing the target data based on the cache address into the storage space.

[0177] In some embodiments, the apparatus may further include a metadata update module for updating metadata information based on the cache address and the target data. The metadata information is used to query whether the target data is stored in the local cache.

[0178] In some embodiments, the address determination module is also used to lock the target data to be written when the access instruction is a data write instruction; and to unlock the target data when the target data is successfully written.

[0179] In some embodiments, the apparatus may further include a synchronization operation for synchronizing result data stored in a local cache to a storage system.

[0180] In some embodiments, the device may further include a data pass-through module, used to save the target data requested to be written by the computing node to the storage system when the access instruction is a data write instruction.

[0181] Figure 8 The data processing device can perform Figure 2 The implementation principle and technical effects of the data processing method described in the illustrated embodiments will not be repeated here. The specific methods by which each module and unit of the data processing device in the above embodiments performs its operations have been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0182] Figure 9 This is a schematic diagram of another embodiment of a data processing apparatus provided in this application. The apparatus can be implemented as a computing device or a virtualized device obtained by virtualizing a computing device. The computing device is configured in a computer system, and the computer system runs a first cache node. The apparatus includes:

[0183] The information acquisition module 901 is used to acquire the access request information and cache address sent by the first cache node; the access request information includes computing information; the access request information is generated based on the access instructions sent by the computing node;

[0184] The response module 902 is used to access the local cache of the computer system based on the cache address; respond to the access request information; and perform calculation processing on the target data requested for access according to the calculation information.

[0185] In some embodiments, the response module may specifically retrieve the corresponding target data from the local cache based on the cache address when the access instruction is a data read instruction; perform calculation processing on the target data according to the calculation information to obtain the result data; store the result data in the target memory corresponding to the operation address; and the first cache node is used to retrieve the result data from the target memory.

[0186] In some embodiments, the response module may specifically obtain the target data to be written from the operation address when the access instruction is a data write instruction; perform calculation processing on the target data according to the calculation information to obtain the result data; and write the result data into the local cache according to the cache address.

[0187] Figure 9 The data processing device can perform Figure 7 The implementation principle and technical effects of the data processing method described in the illustrated embodiments will not be repeated here. The specific methods by which each module and unit of the data processing device in the above embodiments performs its operations have been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0188] This application also provides a computing device, such as... Figure 10 As shown, the computing device may include a storage component 1001 and a processing component 1002; the storage component contains one or more computer instructions, wherein one or more computer instructions are invoked and executed by the processing component to achieve, for example... Figure 7 The data processing method described above.

[0189] The computing device can be implemented using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Of course, it can also be implemented using a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a controller, a microcontroller, a microprocessor, or other forms of integrated circuits (ICs). This application does not limit the implementation of such devices.

[0190] This application also provides a computer system, such as... Figure 11 As shown, the computer system may include a storage component 1101 and a processing component 1102; wherein, the storage component 1101 may include one or more storage media as local cache, such as MEN, PMEM, NVMe hard disk, etc.

[0191] The processing component 1102 can be connected to the computing device 1103 via an I / O interface. For a detailed implementation of the computing device 1103, please refer to... Figure 10 As shown.

[0192] Storage component 1101 may store one or more computer instructions, wherein one or more computer instructions are invoked and executed by processing component 1102 to run the first cache node, such as... Figure 2 The data processing method described above.

[0193] In addition, the processing component 1102 can also be used to run a virtual machine and a virtual machine monitor, specifically to run a first cache node in the user space of the virtual machine, to run a device driver in the kernel space of the virtual machine, and to run a virtualized device of the computing device in the virtual machine monitor.

[0194] Of course, a computer system may also include other components, such as communication components. These communication components are configured to facilitate wired or wireless communication between the computing device and other devices.

[0195] The processing component involved in the above embodiments may include one or more processors to execute computer instructions to complete all or part of the steps in the above method. Alternatively, the processing component may be implemented as one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the above method.

[0196] The storage components involved in the above embodiments are configured to store various types of data to support operations on the terminal. The storage components can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0197] It should be noted that the aforementioned computer system can be a physical device or an elastic computing host provided by a cloud computing platform. It can be implemented as a distributed cluster composed of multiple servers or terminal devices, or as a single server or a single terminal device.

[0198] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a computer, can perform the above-described functions. Figure 2 or Figure 7 The data processing method of the illustrated embodiment. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device.

[0199] This application also provides a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program, when executed by a computer, can perform the above-described functions. Figure 2 or Figure 7 The illustrated embodiment describes a data processing method. In such an embodiment, the computer program may be downloaded and installed from a network, and / or installed from a removable medium. When the computer program is executed by a processor, it performs various functions defined in the system of this application.

[0200] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0201] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0202] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A data processing method, characterized by, The method is applied to a first cache node, the first cache node runs in a computer system, and a computing device is deployed in the computer system; the method comprises: generating access request information based on an access instruction sent by a computing node; the access request information comprises computing information; determining a cache address of a local cache corresponding to the access request information; sending the access request information and the cache address to the computing device, so that the computing device accesses the local cache based on the cache address to respond to the access request information and perform computing processing on target data requested to be accessed according to the computing information; the first cache node runs in a user space, the user space and a kernel space share a buffer queue in a target memory, and the computing device corresponds to a device driver running in the kernel space; the computing device is virtually obtained as a virtual device; the virtual device and the device driver share a virtual queue; the sending of the access request information and the cache address to the computing device comprises: submitting the access request information and the cache address to the buffer queue, obtaining the access request information and the cache address from the buffer queue by the device driver, and mapping the access request information and the cache address to the virtual queue; the virtual device is used to obtain the access request information and the cache address from the virtual queue and send them to the computing device.

2. The method of claim 1, wherein, the access request information comprises an operation address corresponding to a target memory of the first cache node; the computing device is further configured to write a computing result corresponding to the target data into the target memory based on the operation address; the method further comprises: obtaining the computing result from the target memory.

3. The method of claim 1, wherein, the determination of the cache address of the local cache corresponding to the access request comprises: in a case where the access instruction is a data read instruction, determining whether target data requested to be accessed is located in the local cache; when the target data requested to be accessed is located in the local cache, determining a cache address of the target data in the local cache.

4. The method of claim 3, wherein, further comprising: when the target data requested to be accessed is not located in the local cache, determining a storage space allocated for the target data in the local cache; reading the target data from a storage system or a second cache node; writing the target data into the storage space; taking a cache address corresponding to the storage space as the cache address of the target data in the local cache.

5. The method of claim 4, wherein, the determination of whether the target data requested to be accessed is located in the local cache comprises: querying metadata information to determine whether the target data requested to be accessed is located in the local cache; after the writing of the target data into the storage space, the method further comprises: updating the metadata information based on the cache address and the target data.

6. The method of claim 1, wherein, the determination of the cache address of the local cache corresponding to the access request comprises: in a case where the access instruction is a data write instruction, determining a storage space allocated for the target data in the local cache; taking a cache address of the storage space as the cache address corresponding to the access request.

7. The method of claim 6, wherein, Also comprising: Saving the target data requested to be written by the computing node to the target memory corresponding to the first cache node; The access request information includes the operation address of the target data in the target memory; The computing device is configured to obtain the target data from the target memory based on the operation address, and write the result data obtained by computing and processing the target data based on the cache address to the storage space.

8. The method of claim 1, wherein, The access request information is generated based on the access instruction sent by the computing node, comprising: Judging whether the access instruction sent by the computing node is through a predefined interface; If yes, generating the access request information based on the access instruction.

9. A data processing method, characterized by, Applied to a computing device configured in a computer system running a first cache node, the method comprises: Obtaining the access request information and cache address sent by the first cache node; the access request information includes computing information; the access request information is generated based on the access instruction sent by the computing node; Accessing the local cache of the computer system based on the cache address; Responding to the access request information and computing and processing the target data requested to access according to the computing information; The first cache node runs in a user space, and the user space and a kernel space share a buffer queue in a target memory; the computing device corresponds to a device driver running in the kernel space; the computing device is virtually obtained as a virtual device; the virtual device and the device driver share a virtual queue; The access request information and the cache address sent by the first cache node are obtained, comprising: The first cache node submits the access request information and the cache address to the buffer queue, and the device driver obtains the access request information and the cache address from the buffer queue and maps the access request information and the cache address to the virtual queue; the virtual device is configured to obtain the access request information and the cache address from the virtual queue and send them to the computing device.

10. The method of claim 9, wherein, The access request information includes the operation address of the target memory; responding to the access request information and computing and processing the target data requested to access according to the computing information comprises: In the case that the access instruction is a data read instruction, obtaining the corresponding target data from the local cache based on the cache address; Computing and processing the target data according to the computing information to obtain result data; Storing the result data to the target memory corresponding to the operation address; the first cache node is configured to obtain the result data from the target memory.

11. The method of claim 9, wherein, The access request information includes the operation address of the target memory; responding to the access request information and computing and processing the target data requested to access according to the computing information comprises: In the case that the access instruction is a data write instruction, obtaining the target data requested to be written from the operation address; Computing and processing the target data according to the computing information to obtain result data; writing the result data into the local cache according to the cache address.

12. A computing device, comprising: The data processing method comprises the following steps: a processing component is connected to a computing device; a storage component stores one or more computer instructions; the one or more computer instructions are called and executed by the processing component to run a first cache node; and the data processing method is executed.

13. A computer system, characterized by The data processing method comprises the following steps: a processing component is connected to a computing device; a storage component stores one or more computer instructions; the one or more computer instructions are called and executed by the processing component to run a first cache node; and the data processing method is executed.

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