Data transmission compensation method for differential output polarity reversal of tlk2711 chip

Abstract

The application relates to a compensation method for differential output polarity inversion of a TLK2711 chip, and relates to the technical field of differential data transmission, and solves the problem that data transmission cannot be normally carried out due to the reverse connection of the differential output polarity of the TLK2711 chip during hardware design, and the method compensates for the hardware design failure through a software scheme, and avoids the physical operation of re-designing a PCB circuit board or performing chip warping and flying wire operation. The method is realized by adding an encoder, an inverter and a decoder at the transmission link sending end of the differential output polarity inversion; in the application, since the data bit width of the TLK2711 chip is 16bit, the encoder is composed of two 8b10b decoders, each 8b10b decoder is composed of one 6b5b decoder and one 4b3b decoder, and all the decoders share one running inconsistency judge.

Description

Technical Field

[0001] This invention relates to a data transmission compensation method for reverse polarity of the differential output of a TLK2711 chip, and particularly to a data transmission compensation method for reverse polarity of the differential output of a TLK2711 chip based on 8b10b encoding rules. This method is a technical approach that uses software to compensate for hardware design errors, and can effectively solve the problem of data transmission failure caused by reversing the polarity of the differential output of the TLK2711 chip during hardware design. Background Technology

[0002] The TLK2711 chip is a commonly used data transmission chip. Based on the 8b10b encoding rule, the chip performs serial-to-parallel and parallel-to-serial conversion. As a transmitting chip, it can convert parallel data (TTL level) into serial differential data (LVDS level). As a receiving chip, it can convert serial differential data into parallel data. The serial differential data transmission rate is 1.6 to 2.5 Gbps, realizing ultra-high-speed bidirectional point-to-point data transmission.

[0003] The serial differential data of the TLK2711 chip is at LVDS (Low-Voltage Differential Signaling) level. LVDS is a differential signaling technology with low power consumption, low bit error rate, low crosstalk, and low radiation. The differential signal is divided into two signals, positive and negative. When connecting them, the positive terminal must be connected to the positive terminal and the negative terminal to the negative terminal. If there is an error in the hardware design, such as connecting the positive terminal to the negative terminal or vice versa, it will cause abnormal data transmission. The data decoded by the TLK2711 receiver chip will be inconsistent with the data input to the transmitter chip, resulting in the inability to realize the data transmission function. Furthermore, since the 8b10b encoding rule is an asymmetric encoding method that maintains DC voltage balance, it cannot be simply restored by inverting the output data. Summary of the Invention

[0004] This invention provides a data transmission compensation method for the TLK2711 chip differential output polarity reversed, which effectively solves the problem of data transmission failure caused by reversing the differential output polarity of the TLK2711 chip during hardware design. The software solution compensates for hardware design errors, avoiding the need to redesign and process the PCB circuit board or perform physical operations such as chip lifting or flying wires.

[0005] A data transmission compensation method for the TLK2711 chip with reversed differential output polarity is proposed. This method is achieved by adding an encoder, inverter, and decoder to the transmitting end of the transmission link with reversed differential output polarity.

[0006] The encoder and decoder simulate the encoding and decoding process of the TLK2711 chip, and the inverter simulates the reverse polarity of the differential output. After the internal simulated reverse polarity of the differential output at the inverter and the actual reverse polarity of the differential output at the external hardware link, the data decoded at the receiving end of the transmission link with the reverse polarity of the differential output is consistent with the data decoded at the receiving end of the transmission link with the correct differential output polarity, thus realizing data transmission compensation.

[0007] The encoder is used to simulate the encoding of the TLK2711 chip. The specific encoding is based on the 8b10b encoding rule, and the specific steps are as follows:

[0008] Step 1: Determine the current program's inconsistent state RD. The initial value of RD is -1. If RD = +1, proceed to Step 3; if RD = -1, proceed to Step 2.

[0009] Step 2: Encode the lower 5 bits of the high 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=+1 according to the TKMSB high bit K code identifier signal status and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the high 6 bits of the high 10 bits of the output 20-bit data signal. Execute Step 4.

[0010] Step 3: Encode the lower 5 bits of the high 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the high 6 bits of the high 10 bits of the output 20-bit data signal. Then proceed to step 4.

[0011] Step 4: Determine whether the RD value has changed based on the 8b10b encoding rules and the inconsistent application situation. If it has changed, proceed to Step 5; otherwise, proceed to Step 6.

[0012] Step 5: Change the inconsistency polarity during execution, then proceed to Step 6;

[0013] Step 6: Determine the current inconsistent state RD. If RD = +1, proceed to Step 7; if RD = -1, proceed to Step 8.

[0014] Step 7: Encode the high 3 bits of the high 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=+1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the low 4 bits of the high 10 bits of the output 20-bit data signal. Then proceed to step 9.

[0015] Step 8: Encode the high 3 bits of the high 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the low 4 bits of the high 10 bits of the output 20-bit data signal. Then proceed to step 9.

[0016] Step 9: Determine whether the RD value has changed based on the 8b10b encoding rules and the inconsistent application situation. If it has changed, proceed to step 10; if it has not changed, proceed to step 11.

[0017] Step 10: Change the inconsistent polarity during operation, then proceed to Step 11;

[0018] Step 11: Determine the current running inconsistency RD. If RD = +1, proceed to Step 12; if RD = -1, proceed to Step 13.

[0019] Step 12: Encode the lower 5 bits of the lower 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the higher 6 bits of the lower 10 bits of the output 20-bit data signal. Then proceed to step 14.

[0020] Step 13: Encode the lower 5 bits of the lower 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the higher 6 bits of the lower 10 bits of the output 20-bit data signal. Then proceed to step 14.

[0021] Step Fourteen: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to Step Fifteen; if it has not changed, proceed to Step Sixteen.

[0022] Step 15: Change the inconsistency polarity during execution, then proceed to Step 16;

[0023] Step 16: Determine the current running inconsistency RD. If RD = +1, proceed to Step 17; if RD = -1, proceed to Step 18.

[0024] Step 17: Encode the high 3 bits of the lower 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the lower 4 bits of the lower 10 bits of the output 20-bit data signal. Execute Step 19.

[0025] Step 18: Encode the high 3 bits of the lower 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the lower 4 bits of the lower 10 bits of the output 20-bit data signal. Step 19;

[0026] Step 19: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to step 20; if it has not changed, return to step 1.

[0027] Step 20: The inconsistency polarity changes during execution; return to step 1.

[0028] The beneficial effects of the present invention: The present invention proposes a data transmission compensation method for the differential output polarity reversal of the TLK2711 chip based on the 8b10b encoding rule for encoding and decoding. Since the data bit width of the TLK2711 chip is 16 bits, the encoder is composed of two 8b10b decoders, and each 8b10b decoder is composed of one 6b5b decoder and one 4b3b decoder. All decoders share a single inconsistency judge.

[0029] The method of this invention effectively solves the problem of data transmission failure caused by reversing the polarity of the differential output of the TLK2711 chip during hardware design. It compensates for hardware design errors through software solutions, avoiding the need to redesign and process the PCB circuit board or perform physical operations such as chip lifting or flying wires. Attached Figure Description

[0030] Figure 1 This diagram illustrates the correct connection method for a data transmission system based on the TLK2711 chip.

[0031] Figure 2 This is a schematic diagram of the differential output polarity reversal of a data transmission system based on the TLK2711 chip;

[0032] Figure 3 A schematic diagram of a data transmission compensation method for reverse polarity of the differential output of the TLK2711 chip;

[0033] Figure 4 This is a schematic diagram of the internal structure of the encoder;

[0034] Figure 5 This is a schematic diagram of the internal structure of the decoder;

[0035] Figure 6 Here is a flowchart of the encoder's workflow;

[0036] Figure 7 This is a flowchart of the decoder's workflow. Detailed Implementation

[0037] Combination Figures 1 to 7 This embodiment describes a data transmission compensation method for the differential output polarity reversed of the TLK2711 chip. The specific implementation method will be described in detail below with reference to the accompanying drawings.

[0038] The TLK2711 chip's serial differential data is in LVDS (Low-Voltage Differential Signaling) mode. LVDS is a low-power, low-error-rate, low-crosstalk, and low-radiation differential signaling technology. The differential signal consists of two terminals: a positive terminal and a negative terminal. When connecting, the positive terminal must be connected to the positive terminal, and the negative terminal to the negative terminal. The normal connection method is as follows: Figure 1 As shown; if there is an error in the hardware design, such as connecting the positive terminal to the negative terminal or vice versa, the incorrect connection method is as follows: Figure 2 As shown, this will lead to data transmission abnormalities. The data decoded by the TLK2711 receiving chip is inconsistent with the data input to the transmitting chip, resulting in the inability to achieve data transmission functionality. Furthermore, since the 8b10b encoding rule is an asymmetric encoding method that maintains DC voltage balance, it cannot be simply restored by inverting the output data. The specific implementation process of this embodiment is as follows:

[0039] An encoder, inverter, and decoder are added to the transmitting end of a differential output polarity reversed transmission link. The data transmission compensation method is as follows: Figure 3 As shown, the encoder and decoder simulate the encoding and decoding process of the TLK2711 chip, and the inverter simulates the reverse polarity of the differential output. Thus, after the internal simulated differential output polarity is reversed at the inverter and the actual differential output polarity is reversed in the external hardware link, the data decoded at the receiving end of the transmission link with the reversed differential output polarity is consistent with the data decoded at the receiving end of the transmission link with the correctly connected differential output polarity. This achieves data transmission compensation using a software method.

[0040] The newly added encoder at the transmitting end of the transmission link is used to simulate the encoding process of the TLK2711 chip. The encoding process is based on the 8b10b encoding rule. The internal structure of the encoder is as follows: Figure 4 As shown: Since the TLK2711 chip has a data bit width of 16 bits, the encoder is composed of two 8b10b encoders. Each 8b10b encoder is composed of one 5b6b encoder and one 3b4b encoder. All encoders share a single inconsistency checker.

[0041] The encoder input signals include: a clock signal (TXCLK), a high-order K-code identifier signal (TKMSB), a low-order K-code identifier signal (TKLSB), and 16-bit data signals (TXD15~TXD0). The clock signal is the encoder's operating clock. The high-order K-code identifier signal (TKMSB) determines whether the high 8 bits of the 16-bit data signal are encoded as K-code or D-code during 8b10b encoding. When the high-order K-code identifier signal is high (logic 1), the high 8 bits of the data signal are encoded as K-code. When the low bit (logo 0) signal is used, the high 8 bits of the data signal are encoded as D code. The low bit K code identifier signal (TKLSB) determines whether the low 8 bits of the 16-bit data signal are encoded as K code (KCode) or D code (DCode) during 8b10b encoding. When the low bit K code identifier signal is high (logo 1), the low 8 bits of the data signal are encoded as K code; when the low bit K code identifier signal is low (logo 0), the low 8 bits of the data signal are encoded as D code. The 16-bit data signal is divided into high 8 bits and low 8 bits, which are encoded separately. After encoding, the 16-bit data is encoded into 20-bit data. The encoder output signal is the encoded 20-bit data signal (SDATA19~SDATA0).

[0042] Encoder workflow as follows Figure 6 As shown, the specific workflow is as follows:

[0043] a) The program starts running, then jumps to b;

[0044] b) Determine the current running disparity (RD). The initial value of RD is -1. If RD is +1, jump to c. If RD = -1, jump to d.

[0045] c) Encode the lower 5 bits of the high 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=+1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the high 6 bits of the high 10 bits of the output 20-bit data signal. Jump to e.

[0046] d) Encode the lower 5 bits of the high 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=-1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the high 6 bits of the high 10 bits of the output 20-bit data signal. Jump to e;

[0047] e) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to f; otherwise, jump to g.

[0048] f) If the polarity of the runtime inconsistency changes, jump to g;

[0049] g) Determine the current running disparity (RD). If RD is +1, jump to h; if RD = -1, jump to i.

[0050] h) Encode the high 3 bits of the high 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=+1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the low 4 bits of the high 10 bits of the output 20-bit data signal. Jump to j;

[0051] i) Encode the high 3 bits of the high 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the low 4 bits of the high 10 bits of the output 20-bit data signal. Jump to j;

[0052] j) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to k; otherwise, jump to l.

[0053] k) If the polarity of the runtime inconsistency changes, jump to l;

[0054] l) Determine the current running disparity (RD). If RD is +1, jump to m; if RD = -1, jump to n.

[0055] m) Encode the lower 5 bits of the lower 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the higher 6 bits of the lower 10 bits of the output 20-bit data signal. Jump to o.

[0056] n) Encode the lower 5 bits of the lower 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the higher 6 bits of the lower 10 bits of the output 20-bit data signal. Jump to o.

[0057] o) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to p; otherwise, jump to q.

[0058] p) If the polarity of the runtime inconsistency changes, jump to q;

[0059] q) Determine if there is a running disparity (RD). If RD is +1, jump to r; if RD is -1, jump to s.

[0060] r) Encode the high 3 bits of the lower 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the lower 4 bits of the lower 10 bits of the output 20-bit data signal. Jump to t;

[0061] s) Encode the high 3 bits of the lower 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the lower 4 bits of the lower 10 bits of the output 20-bit data signal. Jump to t;

[0062] t) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to u; otherwise, jump to a.

[0063] u) If the polarity changes due to inconsistency, jump to a.

[0064] In this embodiment, the inverter added to the transmitting end of the transmission link is used to simulate the reverse polarity of the differential output, inverting the input signal bit by bit, that is, changing each bit of the input signal from 0 to 1 or from 1 to 0. The inverter signal input signal is a 20-bit data signal (SDATA19~SDATA0), and the output is the inverted 20-bit data signal (SDATA19~SDATA0).

[0065] In this embodiment, the newly added decoder at the transmitting end of the transmission link is used to simulate the decoding process of the TLK2711 chip. The decoding process is based on the 8b10b encoding rule, and the internal structure of the decoder is as follows: Figure 5 As shown: Since the TLK2711 chip has a data bit width of 16 bits, the encoder is composed of two 10b8b decoders. Each 10b8b decoder is composed of one 6b5b decoder and one 4b3b decoder. All decoders share a single inconsistency checker.

[0066] The decoder input signals include: a clock signal (TXCLK), a high-order K-code identifier signal (TKMSB), a low-order K-code identifier signal (TKLSB), and 20-bit data signals (SDATA19~SDATA0). The clock signal is the decoder's operating clock. The high-order K-code identifier signal (TKMSB) determines whether the high 10 bits of the 20-bit data signal are interpreted as K-code or D-code during 8b10b decoding. When the high-order K-code identifier signal is high (logic 1), the high 10 bits of the data signal are interpreted as K-code. When the low bit (logo 0) signal is active, the high 10 bits of the data signal are decoded as D code. The low bit K code identifier signal (TKLSB) determines whether the low 10 bits of the 20-bit data signal are decoded as K code (KCode) or D code (DCode) during 8b10b decoding. When the low bit K code identifier signal is active (logo 1), the low 10 bits of the data signal are decoded as K code; when the low bit K code identifier signal is active (logo 0), the low 10 bits of the data signal are decoded as D code. The 20-bit data signal is divided into two parts, the high 10 bits and the low 10 bits, which are decoded separately. After decoding, the 20-bit data is decoded into 16-bit data. The decoder output signal is the decoded 16-bit data (TXD15~TXD0).

[0067] Decoder workflow as follows Figure 7 As shown, the specific workflow is as follows:

[0068] a) The program starts running, then jumps to b;

[0069] b) Determine the current running disparity (RD). The initial value of RD is -1. If RD is +1, jump to c. If RD = -1, jump to d.

[0070] c) Decode the high 6 bits of the high 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=+1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit decoded sub-data block is the low 5 bits of the high 8 bits of the output 16-bit data signal. Jump to e.

[0071] d) Decode the high 6 bits of the high 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=-1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the low 5 bits of the high 8 bits of the output 16-bit data signal. Jump to e;

[0072] e) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to f; otherwise, jump to g.

[0073] f) If the polarity of the runtime inconsistency changes, jump to g;

[0074] g) Determine the current running disparity (RD). If RD is +1, jump to h; if RD = -1, jump to i.

[0075] h) Decode the lower 4 bits of the high 10 bits of the input 20-bit data signal into a 3-bit decoded sub-data block corresponding to RD=+1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 3-bit decoded sub-data block is the high 3 bits of the high 8 bits of the output 16-bit data signal. Jump to j;

[0076] i) Decode the lower 4 bits of the high 10 bits of the input 20-bit data signal into a 3-bit decoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 3-bit decoded sub-data block is the high 3 bits of the high 8 bits of the output 16-bit data signal. Jump to j;

[0077] j) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to k; otherwise, jump to l.

[0078] k) If the polarity of the runtime inconsistency changes, jump to l;

[0079] l) Determine the current running disparity (RD). If RD is +1, jump to m; if RD = -1, jump to n.

[0080] m) The high 6 bits of the lower 10 bits of the input 20-bit data signal are decoded into a 5-bit decoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the lower 5 bits of the lower 8 bits of the output 16-bit data signal. Jump to o;

[0081] n) Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the lower 5 bits of the lower 8 bits of the output 16-bit data signal. Jump to o.

[0082] o) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to p; otherwise, jump to q.

[0083] p) If the polarity of the runtime inconsistency changes, jump to q;

[0084] q) Determine if there is a running disparity (RD). If RD is +1, jump to r; if RD is -1, jump to s.

[0085] r) Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the high 3 bits of the lower 8 bits of the output 16-bit data signal. Jump to t;

[0086] s) Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the high 3 bits of the lower 8 bits of the output 16-bit data signal. Jump to t;

[0087] t) Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, jump to u; otherwise, jump to a.

[0088] u) If the polarity changes due to inconsistency, jump to a.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A data transmission compensation method for differential output polarity reversal of the TLK2711 chip, characterized by: This method is implemented by adding an encoder, inverter, and decoder to the transmitting end of a transmission link with reversed differential output polarity; The encoder and decoder simulate the encoding and decoding process of the TLK2711 chip, and the inverter simulates the reverse polarity of the differential output. After the internal simulated reverse polarity of the differential output at the inverter and the actual reverse polarity of the differential output at the external hardware link, the data decoded at the receiving end of the transmission link with the reverse polarity of the differential output is consistent with the data decoded at the receiving end of the transmission link with the correct differential output polarity, thus realizing data transmission compensation. The encoder is used to simulate the encoding of the TLK2711 chip. The specific encoding is based on the 8b10b encoding rule, and the specific steps are as follows: Step 1: Determine the current program's inconsistent state RD. The initial value of RD is -1. If RD = +1, proceed to Step 2; if RD = -1, proceed to Step 3. Step 2: Encode the lower 5 bits of the high 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=+1 according to the TKMSB high bit K code identifier signal status and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the high 6 bits of the high 10 bits of the output 20-bit data signal. Then proceed to Step 4. Step 3: Encode the lower 5 bits of the high 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the high 6 bits of the high 10 bits of the output 20-bit data signal. Then proceed to Step 4. Step 4: Determine whether the RD value has changed based on the 8b10b encoding rules and the inconsistent application situation. If it has changed, proceed to Step 5; otherwise, proceed to Step 6. Step 5: Change the inconsistency polarity during execution, then proceed to Step 6; Step 6: Determine the current inconsistent state RD. If RD = +1, proceed to Step 7; if RD = -1, proceed to Step 8. Step 7: Encode the high 3 bits of the high 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=+1 according to the TKMSB state and the 8b10b encoding rule. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the low 4 bits of the high 10 bits of the output 20-bit data signal. Then proceed to step 9. Step 8: Encode the high 3 bits of the high 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the low 4 bits of the high 10 bits of the output 20-bit data signal. Then proceed to step 9. Step 9: Determine whether the RD value has changed based on the 8b10b encoding rules and the inconsistent application situation. If it has changed, proceed to step 10; if it has not changed, proceed to step 11. Step 10: Change the inconsistent polarity during operation, then proceed to Step 11; Step 11: Determine the current running inconsistency RD. If RD = +1, then proceed to Step 12. If RD = -1, then proceed to step thirteen; Step 12: Encode the lower 5 bits of the lower 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=+1 according to the 8b10b encoding rule based on the lower K code identifier signal TKLSB status. When the TKLSB signal is high, it is compiled into K code; when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the higher 6 bits of the lower 10 bits of the output 20-bit data signal. Execute Step 14. Step 13: Encode the lower 5 bits of the lower 8 bits of the input 16-bit data signal into a 6-bit encoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the higher 6 bits of the lower 10 bits of the output 20-bit data signal. Then proceed to step 14. Step Fourteen: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to Step Fifteen; if it has not changed, proceed to Step Sixteen. Step 15: Change the inconsistency polarity during execution, then proceed to Step 16; Step 16: Determine the current running inconsistency RD. If RD = +1, proceed to Step 17; if RD = -1, proceed to Step 18. Step 17: Encode the high 3 bits of the lower 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the lower 4 bits of the lower 10 bits of the output 20-bit data signal. Execute Step 19. Step 18: Encode the high 3 bits of the lower 8 bits of the input 16-bit data signal into a 4-bit encoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit encoded sub-data block is the lower 4 bits of the lower 10 bits of the output 20-bit data signal. Step 19: Step 19: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to step 20; if it has not changed, return to step 1. Step 20: The inconsistency polarity changes during execution; return to step 1.

2. The data transmission compensation method for reverse polarity differential output of the TLK2711 chip according to claim 1, characterized in that: The encoder input signals include a clock signal, a high-order K-code identifier signal, a low-order K-code identifier signal, and a 16-bit data signal; The clock signal is the encoder's operating clock; the high-order K-code identifier signal determines whether the high 8 bits of the 16-bit data signal are encoded as K code or D code during 8b10b encoding. When the high-order K-code identifier signal is high, the high 8 bits of the data signal are encoded as K code; when the high-order K-code identifier signal is low, the high 8 bits of the data signal are encoded as D code. The low-order K-code identifier signal determines whether the lower 8 bits of the 16-bit data signal are encoded as K-code or D-code during 8b10b encoding. When the low-order K-code identifier signal is high, the lower 8 bits of the data signal are encoded as K-code; when the low-order K-code identifier signal is low, the lower 8 bits of the data signal are encoded as D-code. The 16-bit data signal is divided into two parts, the high 8 bits and the low 8 bits, which are encoded separately. After encoding, the 16-bit data is compiled into 20-bit data, and the encoder output signal is the compiled 20-bit data signal.

3. The data transmission compensation method for reverse polarity of the differential output of the TLK2711 chip according to claim 1, characterized in that: The inverter is used to simulate the reverse polarity of the differential output, and to invert the input signal bit by bit in sequence, that is, to change each bit of the input signal from 0 to 1 or from 1 to 0. The inverter input signal is a 20-bit data signal, and the output is a 20-bit data signal after inversion.

4. The data transmission compensation method for reverse polarity differential output of the TLK2711 chip according to claim 1, characterized in that: The decoder input signals include a clock signal, a high-order K-code identifier signal, a low-order K-code identifier signal, and a 20-bit data signal; The clock signal is the decoder's operating clock; the high-order K-code identifier signal determines whether the high 10 bits of the 20-bit data signal are parsed as K-code or D-code during 8b10b decoding. When the high-order K-code identifier signal is high, the high 10 bits of the data signal are parsed as K-code; when the high-order K-code identifier signal is low, the high 10 bits of the data signal are parsed as D-code. The low-order K-code identifier signal determines whether the lower 10 bits of the 20-bit data signal are parsed as K-code or D-code during 8b10b decoding. When the low-order K-code identifier signal is high, the lower 10 bits of the data signal are parsed as K-code; when the low-order K-code identifier signal is low, the lower 10 bits of the data signal are parsed as D-code. The 20-bit data signal is divided into two parts, the high 10 bits and the low 10 bits, which are decoded separately. After decoding, the 20-bit data is parsed into 16-bit data, and the decoder output signal is the parsed 16-bit data signal.

5. The data transmission compensation method for reverse polarity differential output of the TLK2711 chip according to claim 1, characterized in that: The decoder is used to simulate TLK2711 chip decoding. The decoding process is based on the 8b10b encoding rule, and the specific steps are as follows: Step a: Determine the current running inconsistency RD. The initial value of RD is -1. If RD = +1, proceed to step b. If RD = -1, proceed to step c. Step b: Decode the high 6 bits of the high 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=+1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 6-bit decoded sub-data block is the low 5 bits of the high 8 bits of the output 16-bit data signal. Then proceed to step c. Step c: Decode the high 6 bits of the high 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the low 5 bits of the high 8 bits of the output 16-bit data signal. Then execute step d. Step d: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to step e; if it has not changed, proceed to step f. Step e: Change the inconsistency polarity during execution, then proceed to step f; Step f: Determine the current running inconsistency RD. If RD = +1, proceed to step g; if RD = -1, proceed to step h. Step g: Decode the lower 4 bits of the high 10 bits of the input 20-bit data signal into a 3-bit decoded sub-data block corresponding to RD=+1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 3-bit decoded sub-data block is the high 3 bits of the high 8 bits of the output 16-bit data signal. Execute step i. Step h: Decode the lower 4 bits of the high 10 bits of the input 20-bit data signal into a 3-bit decoded sub-data block corresponding to RD=-1 according to the 8b10b encoding rule based on the TKMSB state. When the TKMSB signal is high, it is compiled into K code; when it is low, it is compiled into D code. The 3-bit decoded sub-data block is the high 3 bits of the high 8 bits of the output 16-bit data signal. Execute step i. Step i: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to step j; otherwise, proceed to step k. Step j: Change the inconsistency polarity during execution, then proceed to step k; Step k: Determine the current running inconsistency RD. If RD = +1, execute step l; if RD = -1, execute step m. Step 1: Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the lower 5 bits of the lower 8 bits of the output 16-bit data signal. Execute step n. Step m: Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the lower 5 bits of the lower 8 bits of the output 16-bit data signal. Execute step n. Step n: Determine whether RD has changed based on the 8b10b encoding rules and the application of inconsistent operation. If it has changed, proceed to step o; if it has not changed, proceed to step p. Step o: Change the inconsistency polarity during execution, then proceed to step p; Step p: Determine the current running inconsistency RD. If RD = +1, proceed to step q; if RD = -1, proceed to step r. Step q: Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=+1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the high 3 bits of the lower 8 bits of the output 16-bit data signal. Execute step s. Step r: Decode the high 6 bits of the lower 10 bits of the input 20-bit data signal into a 5-bit decoded sub-data block corresponding to RD=-1 according to the TKLSB state and the 8b10b encoding rule. When the TKLSB signal is high, it is compiled into K code, and when it is low, it is compiled into D code. The 5-bit decoded sub-data block is the high 3 bits of the lower 8 bits of the output 16-bit data signal. Execute step s. Step s: Determine whether RD has changed based on the 8b10b encoding rules and the inconsistent application situation. If it has changed, execute step t; if it has not changed, return to execute step a. Step t: If the polarity of the inconsistency changes, return to step a.

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