Detector training method based on temperature difference compensation

Abstract

The application relates to a temperature difference compensation-based detector training method and relates to the technical field of CMOS detector training application, and solves the problems that, in the prior art, a long time is needed from the start of power-on of a detector to the temperature of a camera detector reaching thermal equilibrium and remaining unchanged, the camera efficiency is seriously affected, and the detected jump edge position in the bit correction process does not conform to the actual state, so that the sampling position is not the optimal position, and the like. Firstly, the temperature difference value at the working steady state and the initial working time and the detected jump edge corresponding delay tap value difference are measured, and then the corresponding tap value difference is compensated into the correction formula in the measurement process. In addition, for the application based on a double data rate input register IDDR, the sampling clock edge switching and the judgment of the number of detected jump edges are optimized.

Description

Technical Field

[0001] This invention relates to the field of CMOS detector training application technology, and specifically to a detector training method based on temperature difference compensation. Background Technology

[0002] For high-power detectors with rapid temperature rise, the temperature during serial image data conditioning may differ significantly from the temperature during imaging. Furthermore, the temperature may change considerably during conditioning, resulting in a large deviation between the conditioned bit correction information and the working temperature. Additionally, due to the rapid temperature change rate during adjustment, correction deviations may occur, ultimately leading to poor temperature adaptability after training, and the detector can only operate within a relatively small temperature variation range.

[0003] The conventional power-on process involves first powering on the focal plane with the imaging controller, then following the relevant timing sequence for powering on the detector, and finally initiating the imaging operation. From the moment the detector is powered on until it reaches thermal equilibrium and remains stable, a considerable amount of time is required, such as 30 minutes. Waiting for the detector to reach thermal equilibrium before each training session—for example, requiring a 5-minute imaging session—would necessitate a 30-minute wait, severely impacting imaging efficiency.

[0004] The existing state transition diagram for bit correction is as follows: Figure 1 As shown, for high-power detectors with rapid temperature rise, the temperature during serial image data conditioning may differ significantly from the temperature during imaging. Furthermore, the temperature may fluctuate considerably during conditioning, resulting in a large deviation between the conditioned bit correction information and the operational temperature. Additionally, the rapid temperature change rate during conditioning leads to correction deviations, ultimately resulting in poor temperature adaptability after training, limiting its operation to a relatively small temperature range. The training process is as follows: At the start of training a new channel, the process enters the "finding the first transition edge" stage. After detecting the first transition edge, it enters the "finding the first stable sampling eye start position" stage. Once the data stabilizes after the first transition edge, it enters the "finding the second transition edge" stage. If the number of stable taps does not meet the specified limit for the second transition edge, it enters the "finding the first stable sampling eye start position" stage; otherwise, it enters the "second transition edge found" stage.

[0005] During the "finding the first transition edge" phase, the current IODELAY delay count, subchant_EYE_CHECK_cnt, is assigned the value of the detected first transition edge position, loc_eye_start. During the "finding the second transition edge" phase, the count of cnt_stable is incremented by 1. During the "second transition edge found" phase, if an unstable data state is detected simultaneously...

[0006] loc_eye_end=loc_eye_start+cnt_stable;

[0007] loc_eye_mid=loc_eye_start+cnt_stable / 2;

[0008] loc_eye_end is the position of the second detected transition edge, and cnt_stable is the number of stable taps detected.

[0009] Based on the frequency f of the serial image data serial_data IODELAY's reference clock frequency f reference and the maximum number of taps n in IODELAY tap_max Estimate the maximum number of taps n corresponding to the potentially detectable stable region. data_tap_max ;

[0010]

[0011] Using this method, even if only one transition edge position is detected, and that transition edge position is far enough away from the start and end positions of the detection, it will be processed as if two transition edge positions were detected, which does not conform to the actual state, and the final sampling position is not the optimal sampling position. Summary of the Invention

[0012] This invention addresses the problems of existing detectors requiring a long time from power-on to thermal equilibrium, which severely impacts imaging efficiency and results in suboptimal sampling positions due to discrepancies between detected transition edges and actual conditions during position correction. It provides a detector training method based on temperature difference compensation.

[0013] A detector training method based on temperature difference compensation, which is implemented based on an improved position correction state transition, is as follows:

[0014] At the start of training for a new channel, the process enters the stage of finding the first transition edge. After the first transition edge is detected, the process enters the stage of finding the first stable sampling eye start position. In the stage of finding the first stable sampling eye start position, the process enters the stage of finding the second transition edge.

[0015] If the number of stable taps does not meet the specified number when the second transition edge is detected, the process enters the stage of finding the starting position of the first stable sampling eye; if the second transition edge is detected and the number of stable taps meets the specified number, the process enters the stage of finding the second transition edge; otherwise, that is, if the second transition edge is not detected, the process continues to search for the second transition edge in this stage.

[0016] During the first edge search phase, each channel assigns the current IODELAY delay count, subchannle_EYE_CHECK_cnt, to loc_eye_start. i ;

[0017] During the second edge-finding phase, cnt_stable i The number of times is incremented by 1; when the second transition edge is found and an unstable data state is detected, the final sampling position of channel i is loc_eye_mid. i for:

[0018] loc_eye_mid i =loc_eye_start i +cnt_stable i / 2-pos i _shift;

[0019] loc_eye_start i The position of the first transition edge of channel i, cnt_stable i For the stable tap count of the i-channel, pos i _shift is the temperature offset value for channel i;

[0020] If the delay count of IODELAY, subchant_EYE_CHECK_cnt, has reached its maximum value during the second edge-finding phase, then the final sampling position of the corresponding i-channel is:

[0021]

[0022] When the delay count of IODELAY, subchant_EYE_CHECK_cnt, reaches its maximum value during the first edge-finding phase, the final sampling position of each channel is:

[0023]

[0024] The beneficial effects of this invention are:

[0025] 1. The method of the present invention compares the training results after power-on steady state with the training results at the initial power-on state, thereby calculating the deviation value of the detected jump edge position caused by the temperature difference, and thus determining the deviation of the detection result caused by the temperature rise of the detector during the detection process.

[0026] 2. The method of this invention, when the detector temperature reaches thermal equilibrium, does not perform detector power-off or focal plane power-off operations, but directly trains the detector, avoiding the influence of temperature changes, thereby obtaining the true state during the imaging process.

[0027] 3. The method of the present invention corrects the results of power-on training based on the deviation between steady-state and power-on training results, thereby reducing the preparation time from power-on to the capture of an effective image and improving photography efficiency. Attached Figure Description

[0028] Figure 1 State transition diagram for bit correction;

[0029] Figure 2 This is a structural diagram of the training system in the detector training method based on temperature difference compensation described in this invention.

[0030] Figure 3 This is a flowchart illustrating the processing of serial image data from a single-channel, high-power, fast-temperature-rise detector within the imaging controller.

[0031] Figure 4 An improved bit correction state transition diagram. Detailed Implementation

[0032] Combination Figures 2 to 4 This embodiment describes a detector training method based on temperature difference compensation, which involves, as follows: Figure 2 The training system for the high-power, fast-temperature-rise detector shown is implemented. The training system includes a low-frequency crystal oscillator, a clock splitter, and an imaging controller. The clock generated by the low-frequency crystal oscillator is divided by the clock splitter to produce a frequency f. inter The CMOS serial clock and frequency are f iodelay The reference clock is sent to the imaging controller. The imaging controller then sends a clock with a frequency of f... inter The CMOS serial clock is fed into the multi-channel CMOS detector, and the multi-channel data output by the multi-channel CMOS detector is sent to the imaging controller for serial-to-parallel conversion.

[0033] Figure 3 This is a flowchart illustrating the processing of serial image data from a single-channel, high-power, fast-temperature-rise detector within the imaging controller. The serial data is processed at a frequency of f. inter Under the low-frequency clock control of / n, the data is first converted from differential to single-ended sequential via IBUFDS, then switched by the dual data rate input register IDDR under the control of IDDR_sel, and finally passed through a reference frequency of f. iodelay The IODELAY is subjected to a fine phase delay, and then a frequency of f is used. inter The clock is based on a shift register to perform serial-to-parallel conversion, and finally outputs n bits of parallel data.

[0034] In this embodiment, the improved bit correction state transition diagram is as follows: Figure 4As shown, at the start of training for a new channel, the process enters the "finding the first transition edge" phase. During the "finding the first transition edge" phase, once the first transition edge is detected, the process moves to the "finding the first stable sampling eye start position" phase. During the "finding the first stable sampling eye start position" phase, once the data stabilizes after experiencing the first transition edge, the process moves to the "finding the second transition edge" phase. While in the "finding the second transition edge" phase, if the number of stable taps does not meet the specified requirement for the second transition edge, the process moves to the "finding the first stable sampling eye start position" phase. If the second transition edge is detected and the number of stable taps meets the specified requirement (e.g., 24 taps), the process moves to the "second transition edge found" phase; otherwise (if the second transition edge is not detected), the process remains in the "finding the second transition edge" phase.

[0035] During the "find the first transition edge" phase, each channel assigns the current IODELAY delay count subchannle_EYE_CHECK_cnt to loc_eye_start. i During the "finding the second transition edge" phase, cnt_stable i The number of times is incremented by 1; if an unstable data state is detected simultaneously during the "second transition edge found" stage, the final sampling position of each channel is:

[0036] loc_eye_mid i =loc_eye_start i +cnt_stable i / 2-pos i _shift;

[0037] If the delay count of IODELAY, subchant_EYE_CHECK_cnt, has reached its maximum value during the "finding the second transition edge" phase, then the final sampling position for each channel is:

[0038]

[0039] If the delay count of IODELAY, subchant_EYE_CHECK_cnt, has reached its maximum value during the "finding the first transition edge" phase, then the final sampling position for each channel is:

[0040]

[0041] In this embodiment, the training results are first based on traditional training methods such as "A New Training Method for Multi-Channel Low-Frequency CMOS Serial Image Data" and "A Bit-Correction Improved Training Method for Serial CMOS Image Data". Training is performed at the target temperature T0 before power-on and the target temperature T1 during imaging, respectively, with the connected heat dissipation equipment in the same state as during application. The relevant timing sequence for detector power-on is performed at T0, and then training is performed to detect the transition edge position pos of each channel. i _00 or pos i _01; Once the detector has been powered on and reached thermal equilibrium (T1), a training command is sent to detect the transition edge position pos of each channel. i _10 or pos i _11; where i represents the number of channels.

[0042] During bit correction, the required delay time t for the high-low level switching of IDDR_sel is... IDDR_sel_delay The delay time t from the emission of a pulse less than IODELAY to the start of edge detection iodelay_to_check .

[0043] t IDDR_sel_delay <t iodelay_to_check

[0044] Correction algorithm:

[0045] a) If each channel detects at least one transition edge position pos at T0 and T1. i _00 and pos i _10, then the offset value of each temperature.

[0046]

[0047] tap max It is twice the maximum number of delayed taps of Iodelay.

[0048] In this embodiment, the power-on sequence is as follows: the focal plane with the imaging controller is powered on first, followed by the relevant timing sequence for powering on the detector, and finally, the imaging operation is performed. The detector training operation begins immediately after power-on, not after the detector reaches thermal equilibrium. The detector temperature before power-on and before operation is the pre-power-on thermal control target temperature T0, and the steady-state temperature after imaging, when the detector reaches thermal equilibrium, is the thermal control target temperature T1 during imaging.

[0049] In this embodiment, the low-frequency crystal oscillator is a product of Wuhan Haichuang Company; the clock splitter is CDCM7005 of TI Company; the imaging controller is Virtex 5 series FPGA; and the CMOS image sensor is TDICMOS image sensor of Changguang Chenxin Company.

Claims

1. A detector training method based on temperature difference compensation, characterized by: This training method is based on an improved bit-corrected state transition: the specific process is as follows: At the start of training for a new channel, the process enters the stage of finding the first transition edge. After the first transition edge is detected, the process enters the stage of finding the first stable sampling eye start position. In the stage of finding the first stable sampling eye start position, the process enters the stage of finding the second transition edge. If the number of stable taps does not meet the specified number when the second transition edge is detected, the process enters the stage of finding the starting position of the first stable sampling eye; if the second transition edge is detected and the number of stable taps meets the specified number, the process enters the stage of finding the second transition edge; otherwise, that is, if the second transition edge is not detected, the process continues to search for the second transition edge in this stage. During the first edge search phase, each channel assigns the current IODELAY delay count, subchannle_EYE_CHECK_cnt, to loc_eye_start. i ; During the second edge-finding phase, cnt_stable i The number of times is incremented by 1; when the second transition edge is found and an unstable data state is detected, the final sampling position of channel i is loc_eye_mid. i for: loc_eye_mid i =loc_eye_start i +cnt_stable i / 2-pos i _shift; loc_eye_start i The position of the first transition edge of channel i, cnt_stable i For the stable tap count of the i-channel, pos i _shift is the temperature offset value for channel i; If the delay count of IODELAY, subchant_EYE_CHECK_cnt, has reached its maximum value during the second edge-finding phase, then the final sampling position of the corresponding i-channel is: When the delay count of IODELAY, subchant_EYE_CHECK_cnt, reaches its maximum value during the first edge-finding phase, the final sampling position of each channel is: n data_tap_max The maximum number of taps corresponding to the stable region.

2. The detector training method based on temperature difference compensation according to claim 1, characterized in that: The training method is implemented through a training system for a high-power, fast-temperature-rise detector, which includes a low-frequency crystal oscillator, a clock splitter, and an imaging controller. The clock generated by the low-frequency crystal oscillator is divided by a clock splitter to produce a frequency of f. inter The CMOS serial clock and frequency are f iodelay The reference clock is sent to the imaging controller; the imaging controller will send a frequency of f inter The CMOS serial clock is fed into the multi-channel CMOS detector, and the multi-channel data output by the multi-channel CMOS detector is sent to the imaging controller for serial-to-parallel conversion.

3. The detector training method based on temperature difference compensation according to claim 2, characterized in that: The process of serial-to-parallel conversion performed by the imaging controller is as follows: The serial data output by the multi-channel CMOS detector is at a frequency of f inter Under the low-frequency clock control of / n, the signal is first differentially converted to a single-ended signal by the differential signal buffer IBUFDS. Then, under the control of the dual data rate input register select signal IDDR_sel, the sampling clock edge is switched by the dual data rate input register IDDR. Finally, the signal passes through a reference frequency of f. iodelay The IODELAY is subjected to a fine phase delay, and then a frequency of f is used. inter The clock is based on a shift register to perform serial-to-parallel conversion, ultimately outputting n bits of parallel data.

4. The detector training method based on temperature difference compensation according to claim 2, characterized in that: The power-on sequence of the training system is as follows: the focal plane with the imaging controller is powered on first, then the relevant timing sequence for powering on the multi-channel CMOS detector is performed, and finally the imaging operation is performed; the training operation of the multi-channel CMOS detector begins after the detector is powered on, the temperature of the focal plane before power-on is the thermal control target temperature T0 before power-on, and the steady-state temperature of the detector after reaching thermal equilibrium after imaging is the thermal control target temperature T1 during imaging.

5. The detector training method based on temperature difference compensation according to claim 2, characterized in that: During bit correction, the required delay time t for the high-low level switching of IDDR_sel is... IDDR_sel_delay The delay time t from the emission of a pulse less than IODELAY to the start of edge detection iodelay_to_check .

6. The detector training method based on temperature difference compensation according to claim 2, characterized in that: The training method is performed at the target temperature T0 before power-on and the target temperature T1 during imaging, with the connected heat dissipation equipment in the same state as during application. The relevant timing sequence for detector power-on is performed at T0, followed by training, and the transition edge position pos of each channel is detected. i _00 or pos i _01; When the detector reaches thermal equilibrium and is maintained at T1, a training command is sent to detect the transition edge position pos of each channel. i _10 or pos i _11; where i represents the number of channels.

7. The detector training method based on temperature difference compensation according to claim 6, characterized in that: If each channel detects at least one transition edge position pos under T0 and T1. i _00 and pos i If _10, then the offset value pos for each temperature. i _shift is: In the formula, tap max It is twice the maximum number of delayed taps for IODELAY.

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