Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of first detection pins and a plurality of second detection pins, and the plurality of first detection pins and the plurality of second detection pins are arranged in two rows. Therefore, in the case that the size of the substrate in the display panel along the pixel row direction is limited, the number of the set detection pins can be increased, the detection ratio of the sub-pixels in the display panel is further increased, the missing detection probability is reduced, and the yield of the display panel is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The display panel has a display area and a peripheral area surrounding the display area. The display panel includes a plurality of columns of sub-pixels in the display area and a plurality of data lines connected one-to-one with the plurality of columns of sub-pixels, each data line being used for transmitting a signal to a corresponding column of sub-pixels. In addition, the display panel further includes a plurality of detection pins in the peripheral area and a detection trace in the display area and the peripheral area, one end of the detection trace being connected with one detection pin and the other end being connected with one data line.

[0003] In the related art, in order to electrically detect the sub-pixels of the display panel, a detection device can be connected with the plurality of detection pins, so that the detection device provides a signal to the data line through the detection trace to realize the detection process.

[0004] However, due to the limited horizontal size of the peripheral area of the display panel, it is difficult to design corresponding detection pins and detection traces for all data lines in the display area, and there is a risk of missing detection. SUMMARY

[0005] The present application provides a display panel and a display device, which can solve the problem of missing detection of sub-pixels in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, which includes:

[0007] a substrate having a display area and a peripheral area surrounding the display area;

[0008] a plurality of data lines at least in the display area, the plurality of data lines extending along a pixel column direction and arranged along a pixel row direction;

[0009] a plurality of first detection pins in a first region of the peripheral area, the plurality of first detection pins being arranged along the pixel row direction and having a gap between each adjacent two first detection pins, the first region and the display region being arranged along the pixel column direction;

[0010] a plurality of first detection traces at least in the first region, the plurality of first detection traces and the plurality of first detection pins corresponding one-to-one, a first end of each first detection trace being connected with a corresponding one of the first detection pins, and a second end being connected with one of the data lines;

[0011] a plurality of second detection pins located in the first region and on a side of the plurality of first detection pins away from the display area, the plurality of second detection pins being arranged along the pixel row direction;

[0012] and a plurality of second detection traces located in at least the first region, the plurality of second detection traces corresponding to the plurality of second detection pins one by one, a first end of each of the second detection traces being connected to a corresponding one of the second detection pins, and a second end of each of the second detection traces being connected to a data line through the gap.

[0013] Optionally, the plurality of second detection pins and the plurality of first detection pins are arranged alternately.

[0014] Optionally, each of the second detection traces connected to a second detection pin is located in a gap between two adjacent first detection pins, and each of the gaps between two adjacent first detection pins has one of the second detection traces.

[0015] Optionally, a projection of each of the second detection pins on the substrate substrate is arranged along the pixel column direction with a projection of the corresponding gap on the substrate substrate.

[0016] Optionally, a connection line segment of the second detection trace connected to the second detection pin and a line segment of the second detection trace located in the gap both extend along the pixel column direction.

[0017] Optionally, the display panel further comprises:

[0018] a plurality of first dummy detection pins located in the first region, the plurality of first dummy detection pins being located on at least one side of the plurality of first detection pins, and the plurality of first dummy detection pins and the plurality of first detection pins being arranged along the pixel row direction, each of the first dummy detection pins not being connected to the first detection trace;

[0019] a plurality of second dummy detection pins located in the first region, the plurality of second dummy detection pins being located on at least one side of the plurality of second detection pins, and the plurality of second dummy detection pins and the plurality of second detection pins being arranged along the pixel row direction, each of the second dummy detection pins not being connected to the second detection trace.

[0020] Optionally, the display panel further comprises:

[0021] a plurality of dummy detection traces located in at least the first region, the dummy detection traces not being connected to the first dummy detection pins, the second dummy detection pins, or the data lines.

[0022] Optionally, the peripheral area includes a second area located between the display area and the first area; the display panel further includes: power traces located on the first metal layer of the display panel; the power traces include:

[0023] The first part is located on the side of the second region away from the display area;

[0024] The second part, located in the second region, includes multiple connecting lines, with a gap between each pair of adjacent connecting lines;

[0025] And a third part, which is located on the side of the second region closer to the display area;

[0026] Wherein, the first end of the first part is used to connect to the power supply circuit, the second end of the first part is connected to the first end of the plurality of connecting lines, the second end of the plurality of connecting lines is connected to the first end of the third part, the second end of the third part is connected to the structure in the display area of ​​the display panel, and the width of the first part and the third part is greater than the width threshold.

[0027] Optionally, the portions of the first detection trace and the second detection trace located in the second region are located in the first metal layer, and the portions of the first detection trace and the second detection trace located outside the second region are located in the second metal layer of the display panel;

[0028] Wherein, the width of each of the plurality of first detection traces and the plurality of second detection traces is smaller than the width of the gap between the connecting lines, the portion of the target detection trace in the second region of the first detection trace and the second detection trace is located in the gap between the connecting lines, and the orthographic projection of the portion of the target detection trace other than that located in the second region on the substrate overlaps at least partially with the orthographic projection of the power supply trace on the substrate.

[0029] Optionally, the display panel further includes: an insulating layer located between the first metal layer and the second metal layer; each of the plurality of first detection traces and the plurality of second detection traces includes:

[0030] A first line segment, the first line segment being located on the side of the second region away from the display area, the first line segment being located in the second metal layer;

[0031] A first connecting portion is located on the side of the second region away from the display area and on the side of the first line segment close to the second region. The first connecting portion is located in a first through hole in the insulating layer and is connected to the first line segment.

[0032] The second line segment has a first end located on the side of the second region away from the display area, and the first end of the second line segment is connected to the first connecting portion. The second end of the second line segment passes through the second region and is located on the side of the second region closer to the display area. The second line segment is located in the first metal layer.

[0033] The second connecting part is located on the side of the second region closer to the display area. The second connecting part is located in the second via in the insulating layer and is connected to the second end of the second line segment.

[0034] The third line segment is located on the side of the second region closer to the display area, and on the side of the second connecting portion away from the second region. The third line segment is connected to the second connecting portion and is located in the second metal layer.

[0035] Optionally, the first portion of the power supply trace has a first opening, and the first connection portion of the target detection trace is located inside the first opening and has a gap with the first opening;

[0036] The third part of the power supply trace has a second opening, and the second connection part of the target detection trace is located inside the second opening and has a gap with the second opening.

[0037] Optionally, the first metal layer is a source / drain layer, and the second metal layer is a gate layer.

[0038] Optionally, the peripheral area includes a third area located in the first area away from the display area; the display panel further includes:

[0039] Multiple signal pins located in the third region, the multiple signal pins being arranged along the pixel row direction;

[0040] The plurality of signal pins are used to transmit signals when the display panel is displaying normally, and the plurality of target pins among the plurality of signal pins are also used to transmit signals when the display panel is tested for lighting.

[0041] Optionally, the extension direction of the central axis of each of the signal pins intersects the direction of the pixel column.

[0042] Optionally, the angle between the extension direction of the central axis of each signal pin and the direction of the pixel column ranges from 8 degrees to 15 degrees.

[0043] Optionally, the plurality of target pins includes a first type of target pin and a second type of target pin;

[0044] The first type of target pin is used to transmit DC signals, and the second type of target pin is used to transmit AC signals. The width of the first type of target pin along the pixel row direction is greater than the width of the second target pin along the pixel row direction.

[0045] On the other hand, a display device is provided, the display device comprising: a power supply component and a display panel as described above;

[0046] The power supply component is used to supply power to the display panel.

[0047] The beneficial effects of the technical solution provided in this application include at least the following:

[0048] This application provides a display panel and a display device. The display panel includes a plurality of first detection pins and a plurality of second detection pins, which are arranged in two rows. Therefore, given the limited size of the substrate along the pixel row direction in the display panel, the number of detection pins can be increased, thereby increasing the detection ratio of sub-pixels in the display panel, reducing the probability of missed detections, and ensuring the yield of the display panel. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0051] Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0052] Figure 3 This is a partial structural diagram of another display panel provided in an embodiment of this application;

[0053] Figure 4 This is a partial structural diagram of a display panel in related technologies;

[0054] Figure 5 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0055] Figure 6 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0056] Figure 7 This is a partial cross-sectional view of a display panel provided in an embodiment of this application;

[0057] Figure 8 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0058] Figure 9 This is a schematic diagram of the LED test pin and signal pin in the relevant technology;

[0059] Figure 10 This is a schematic diagram of the surrounding area in the related technology;

[0060] Figure 11 This is a schematic diagram of a signal pin provided in an embodiment of this application;

[0061] Figure 12 This is a schematic diagram of the lamp testing pin and signal pin provided in an embodiment of this application;

[0062] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0064] In related technologies, to improve the detection ratio of sub-pixels, a data selector (multiplexer, MUX) is usually designed in the detection area. This approach can typically increase the detection ratio from 1 / 4 to 1 / 2. However, the added MUX is prone to introducing risks such as electrostatic discharge (ESD), reducing the tolerance for reliability tests.

[0065] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. (Reference) Figure 1 The display panel 10 may include: a substrate 101, multiple data lines 102, multiple first detection pins 103, multiple first detection traces 104, multiple second detection pins 105, and multiple second detection traces 106.

[0066] The substrate 101 includes a display area 101a and a peripheral area 101b surrounding the display area 101a. Multiple data lines 102 are located at least in the display area 101a, and each data line 102 is connected to a column of sub-pixels in the display panel 10 located in the display area 101a, providing data signals to that column of sub-pixels. Multiple first detection pins 103 are located in a first region b1 within the peripheral area 101b, and multiple second detection pins 105 are located in the first region b1 and on the side of the multiple first detection pins 103 away from the display area 101a. Multiple first detection traces 104 and multiple second detection traces 106 are located at least in the first region b1.

[0067] Multiple data lines 102 extend along the pixel column direction Y and are arranged along the pixel row direction X. Multiple first detection pins 103 are arranged along the pixel row direction X, with a gap between each pair of adjacent first detection pins 103. Multiple second detection pins 105 are arranged along the pixel row direction X.

[0068] Furthermore, multiple first detection traces 104 correspond one-to-one with multiple first detection pins 103. The first end of each first detection trace 104 is connected to a corresponding first detection pin 103, and the second end is connected to a data line 102. Multiple second detection traces 106 correspond one-to-one with multiple second detection pins 105. The first end of each second detection trace 106 is connected to a corresponding second detection pin 105, and the second end passes through the gap between two first detection pins 103 and is connected to a data line 102.

[0069] For example Figure 1 As shown, one end of each data line 102 connected to the first detection line 104 or the second detection line 106 is located in the peripheral area 101b, while the second end of the first detection line 104 or the second end of the second detection line 106 is not located in the display area 101a. The connection point between each first detection line 104 or each second detection line 106 and a data line 102 is located in the peripheral area 101b. Alternatively, the second end of the first detection line 104 or the second end of the second detection line 106 is also located in the display area 101a, while one end of each data line 102 connected to the first detection line 104 or the second detection line 106 is not located in the peripheral area 101b. The connection point between each first detection line 104 or each second detection line 106 and a data line 102 is located in the display area 101a.

[0070] Therefore, when performing electrical detection of sub-pixels in the display area 101a of the display panel 10, the detection circuit provides a detection signal to the first detection pin 103 through the first detection trace 104 to the data line 102, and provides a detection signal to the second detection pin 105 through the second detection trace 106 to the data line 102, thereby completing the electrical detection of sub-pixels connected to multiple data lines 102.

[0071] In this embodiment, since two rows of detection pins (i.e., multiple first detection pins 103 and multiple second detection pins 105) are arranged in the first region b1 of the peripheral area 101b of the display panel 10, and each detection pin is connected to a data line 102 through a detection trace, even though the size of the substrate 101 in the pixel row direction X is limited, a larger number of data lines 102 can receive detection signals through the detection pins. This increases the electrical detection ratio of the sub-pixels of the display area 101a in the display panel 10 (the detection ratio is increased from 1 / 4 to 1 / 2), improves the detection rate of defective products, reduces the probability of missed detection, and ensures the yield of the display panel 10. Furthermore, it achieves the same effect as a MUX, but avoids the risks associated with a MUX.

[0072] In summary, this application provides a display panel including a plurality of first detection pins and a plurality of second detection pins, arranged in two rows. Therefore, given the limited dimensions of the substrate along the pixel row direction in the display panel, the number of detection pins can be increased, thereby increasing the detection ratio of sub-pixels in the display panel, reducing the probability of missed detections, and ensuring the yield of the display panel.

[0073] Optionally, a gap is also provided between each pair of adjacent detection pins in the plurality of second detection pins 105 to avoid signal interference between adjacent detection pins. The display panel 10 may also include a plurality of third detection pins and a plurality of third detection traces (not shown in the figure) corresponding one-to-one with the plurality of third detection pins. The plurality of third detection pins are located in the first region b1 and on the side of the plurality of second detection pins 105 away from the display area 101a. The plurality of third detection pins are arranged along the pixel row direction X. The plurality of third detection traces are located in the first region b1 and the display area 101a. The first end of each third detection trace is connected to a corresponding third detection pin, and the second end passes through the gap between two of the second detection pins 105 and the gap between two of the first detection pins 103 in sequence and is connected to a data line 102.

[0074] In other words, the display panel 10 may include three rows of detection pins, which, compared to a two-row arrangement, can increase the number of detection pins, further increase the detection ratio of sub-pixels in the display panel 10, and further reduce the probability of missed detection.

[0075] It should be noted that the display panel 10 may include more rows of detection pins, such as four rows or five rows of detection pins. This application embodiment does not limit this, as long as there is sufficient space in the first region b1 of the substrate 101 to accommodate the detection pins.

[0076] In the embodiments of this application, among the multiple gaps formed by multiple first detection pins 103 (e.g., n detection pins form n-1 gaps), some gaps may be provided with multiple second detection traces 106, while some gaps may not be provided with second detection traces 106. It is sufficient to ensure that there are certain gaps between the second detection traces 106 and between the second detection traces 106 and the first detection pins 103 to ensure reliable signal transmission.

[0077] refer to Figure 2 and Figure 3 The multiple second detection pins 105 and the multiple first detection pins 103 are arranged in an alternating pattern. Alternatively, the multiple second detection pins 105 and the multiple first detection pins 103 can be arranged in an array. This application does not limit this.

[0078] Optionally, when multiple second detection pins 105 and multiple first detection pins 103 are arranged in an alternating manner, a second detection trace 106 connected to each second detection pin 105 is located in the gap between two adjacent first detection pins 103, and there is one second detection trace 106 in each gap between two adjacent first detection pins 103. That is, the gap between each two adjacent first detection pins 103 allows one second detection trace 106 connected to a corresponding second detection pin 105 to pass through.

[0079] In this configuration, the orthographic projection of each second detection pin 105 onto the substrate 101 is aligned with the orthographic projection of the corresponding gap onto the substrate 101 along the pixel column direction Y. Alternatively, the orthographic projection of each second detection pin 105 onto a reference plane at least partially overlaps with the orthographic projection of the corresponding gap onto the reference plane. This reference plane is perpendicular to the bearing surface of the substrate 101 and parallel to the pixel row direction X. For example, the central axis of each second detection pin 105 may overlap with the central axis of the corresponding gap.

[0080] refer to Figure 3In the second detection trace 106, the connection segment F1 at the junction with the second detection pin 105, and the portion of the second detection trace 106 located in the gap, both extend along the pixel column direction Y. That is, the portion of the second detection trace 106 from its connection to the second detection pin 105 until it passes through the gap between the first detection pin 103 and the second detection trace 106, is a straight line. This method avoids interference between signals transmitted by different detection traces, ensuring the reliability of the signal transmitted by each detection trace.

[0081] Combination Figure 2 and Figure 3 The display panel 10 further includes: a plurality of first dummy detection pins 107 located in the first region b1 and a plurality of second dummy detection pins 108 located in the first region b1. The plurality of first dummy detection pins 107 are located on at least one side of a plurality of first detection pins 103, and the plurality of first dummy detection pins 107 and the plurality of first detection pins 103 are arranged along the pixel row direction X. Each first dummy detection pin 107 is not connected to a first detection trace 104. The plurality of second dummy detection pins 108 are located on at least one side of a plurality of second detection pins 105, and the plurality of second detection pins 105 are arranged along the pixel row direction X. Each second dummy detection pin 108 is not connected to a second detection trace 106.

[0082] Optionally, the plurality of first dummy detection pins 107 can be divided into two parts: a first part of the first dummy detection pins 107 is located on one side of the plurality of first detection pins 103, and a second part of the first dummy detection pins 107 is located on the other side of the plurality of first detection pins 103. The plurality of second dummy detection pins 108 are divided into two parts: a first part of the second dummy detection pins 108 is located on one side of the plurality of second detection pins 105, and a second part of the second dummy detection pins 108 is located on the other side of the plurality of second detection pins 105.

[0083] refer to Figure 3 The display panel 10 also includes at least a plurality of dummy detection traces 109 located in the first region b1. The dummy detection traces 109 are not connected to the first dummy detection pin 107 and the second dummy detection pin 108, and are not connected to the data line 102.

[0084] The arrangement of the dummy detection trace 109 can be the same as that of the first detection trace 104 or the second detection trace 106, except that the dummy detection trace 109 is not connected to the detection pins or data lines. For example, if the second end of the first detection trace 104 or the second end of the second detection trace 106 is not located in the display area 101a, then the dummy detection trace 109 is also not located in the display area 101a. If the second end of the first detection trace 104 or the second end of the second detection trace 106 is located in the display area 101a, then the dummy detection trace 109 is also located in the display area 101a. Alternatively, the arrangement of the dummy detection trace 109 can be different from that of the first detection trace 104 or the second detection trace 106, and this embodiment does not limit this.

[0085] By designing dummy detection pins and dummy detection traces 109, the pattern uniformity of the first region b1 can be improved. Furthermore, considering the etching process in manufacturing, designing dummy detection pins and dummy detection traces 109 can ensure the manufacturing precision of the detection pins and traces, so that the manufactured detection pins or traces can meet the design requirements as much as possible.

[0086] In this embodiment, the peripheral area 101b may include a second area b2 located between the display area 101a and the first area b1. The display panel 10 also includes a power trace 110 located on the first metal layer. (See reference...) Figure 5 The power supply trace 110 includes a first portion 1101, a second portion 1102, and a third portion 1103. The first portion 1101 is located on the side of the second region b2 away from the display area 101a. The second portion 1102 is located in the second region b2 and includes multiple connecting lines L, with a gap between each pair of adjacent connecting lines L. The third portion 1103 is located on the side of the second region b2 closer to the display area 101a.

[0087] In this design, the widths of the first portion 1101 and the third portion 1103 along the pixel row direction X are greater than a width threshold. That is, the orthographic projections of the first portion 1101 and the third portion 1103 onto the substrate 101 can be sheet-like structures with a certain width. The first end of the first portion 1101 is used to connect to a power supply circuit, the second end of the first portion 1101 is connected to the first ends of multiple connection lines L, the second ends of the multiple connection lines L are connected to the first end of the third portion 1103, and the second end of the third portion 1103 is connected to a structure (e.g., a transistor or cathode layer) in the display area 101a of the display panel 10.

[0088] In this embodiment, the portions of the first detection trace 104 and the second detection trace 106 located in the second region b2 are located in the first metal layer of the display panel 10, and the portions of the first detection trace 104 and the second detection trace 106 other than those located in the second region b2 are located in the second metal layer of the display panel 10. That is, the portion of the first detection trace 104 (or the second detection trace 106) located in the second region b2 is located on the same layer as the power trace 110.

[0089] Optionally, the second region b2 can be a bending region. The substrate 101 can be bent along the second region b2 to bend the remaining portion of the second region b2 away from the display area 101a to the back side of the display panel 10, thereby reducing the bezel size of the display panel 10. The material of the first metal layer is more easily bent than the material of the second metal layer, thus allowing the portions of the first detection trace 104 and the second detection trace 106 located in the second region b2 to be transferred to the first metal layer for easier bending.

[0090] Optionally, the first metal layer can be a source-drain (SD) layer, and the second metal layer can be a gate layer.

[0091] refer to Figure 4 To avoid interference between the power supply trace 110 and the detection traces m (first detection trace 104 or second detection trace 106) located in the second region b2, multiple detection traces m (first detection trace 104 or multiple second detection traces 106) are typically placed on both sides of the power supply trace 110, spaced apart. However, the power supply trace 110 is usually quite wide along the pixel row direction X. If multiple (first detection traces 104 or multiple second detection traces 106) are placed on both sides of the power supply trace 110, the resistance of the detection traces m (first detection trace 104 or second detection trace 106) on both sides of the power supply trace 110 will fluctuate significantly, potentially affecting the display uniformity of the display panel 10.

[0092] In the embodiments of this application, reference is made to Figure 6 The width of each of the multiple first detection traces 104 and multiple second detection traces 106 is smaller than the width of the gap between the connecting lines L. The portion of the target detection trace m in the first detection traces 104 and the second detection traces 106 located in the second region b2 lies within the gap between the connecting lines L. The orthographic projection of the portion of the target detection trace m, excluding the portion located in the second region b2, onto the substrate 101 at least partially overlaps with the orthographic projection of the power supply trace 110 onto the substrate 101.

[0093] The portion of the target detection trace m, excluding the area in the second region b2, is located on the second metal layer, while the power trace 110 is located on the first metal layer c1. Therefore, even if their orthographic projections overlap, it will not affect signal transmission. Furthermore, since the second region b2 has a small dimension along the pixel column direction Y, even if the portion of the power trace 110 located in the second region b2 is designed as multiple connecting lines L, the impact on the signal transmission of the power trace 110 will not be significant.

[0094] in, Figure 6 The connecting line L or detection line located in the second region b2 is connected to a line in the area of ​​the second region b2 closest to the display area 101a (there is a gap between adjacent lines), but due to the large number of lines, Figure 6 The lines in the image are too close together to be clearly shown, hence this explanation.

[0095] Figure 7 This is a partial cross-sectional view of a display panel provided in an embodiment of this application. (Reference) Figure 7 The display panel 10 further includes an insulating layer c3 located between the first metal layer c1 and the second metal layer c2. Each detection trace m in the plurality of first detection traces 104 and the plurality of second detection traces 106 includes: a first segment m1, a first connecting portion m2, a second segment m3, a second connecting portion m4, and a third segment m5.

[0096] In this design, the first line segment m1 is located on the side of the second region b2 away from the display area 101a, and is situated in the second metal layer c2. The first connecting portion m2 is located on the side of the second region b2 away from the display area 101a, and is also located on the side of the first line segment m1 closest to the second region b2. This first connecting portion m2 is located within a first via in the insulating layer c3, and is connected to the first line segment m1. The first end of the second line segment m3 is located on the side of the second region b2 away from the display area 101a, and the second end of the second line segment m3 passes through the second region b2 and is located on the side of the second region b2 closest to the display area 101a. The first end of the second line segment m3 is connected to the first connecting portion m2. This second line segment m3 is situated in the first metal layer c1. The second connecting portion m4 is located on the side of the second region b2 closest to the display area 101a, and is situated within a second via in the insulating layer c3. This second connecting portion m4 is connected to the second end of the second line segment m3. The third segment m5 is located on the side of the second region b2 closer to the display area 101a, and on the side of the second connecting part m4 away from the second region b2. The third segment m5 is connected to the second connecting part m4 and is located in the second metal layer c2.

[0097] In the embodiments of this application, reference is made to Figure 8The first portion 1101 of the power supply trace 110 has a first opening d1, and the first connection portion m2 of the target detection trace is located within the first opening d1 and has a gap with the first opening d1. The third portion 1103 of the power supply trace 110 has a second opening d2, and the second connection portion m4 of the target detection trace is located within the second opening d2 and has a gap with the second opening d2. Therefore, the power supply trace 110 and the target detection trace do not come into contact, ensuring reliable signal transmission. Figure 8 Different line types are used to represent the power supply trace 110 connection line and the detection trace, only to clearly illustrate the arrangement and design of the two, and do not represent the actual shape and thickness.

[0098] Optionally, the power supply trace 110 can be a positive power supply (VDD) trace or a negative power supply (VSS) trace. If the power supply trace 110 is a VDD trace, then the second end of the third portion 1103 of the power supply trace is connected to the transistor. If the power supply trace 110 is a VSS trace, then the second end of the third portion 1103 of the power supply trace is connected to the cathode layer.

[0099] refer to Figure 9 The display panel needs to go through two cutting processes to be formed. The first cutting process is in the EAC stage (as shown in the EAC cutting channel in the figure), and the second cutting process is in the MDL (module) stage (as shown in the MDL cutting channel in the figure).

[0100] Before leaving the factory, display panels typically undergo a cell test. In related technologies, the cell test pin is located between the EAC and MDL cut channels, and is connected via an adapter trace to the signal pin 111 of the third region b3 on the MDL cut channel near the display area 101a, thus providing a test path. The portion of the adapter trace located on the MDL cut channel lies in the second metal layer c2 (the second metal layer has a higher impedance). For large-size products with high current requirements, the adapter trace crossing the MDL cut channel is prone to burn-in defects. Furthermore, refer to... Figure 10 The final display panel 10 will cut off the lamp test pin (the part of the MDL cut channel away from the display area is cut off). Since the lamp test pin needs to be designed between the two cut channels, the space between the two cut channels needs to be reserved, which is not conducive to obtaining a higher number of substrates.

[0101] Optionally, to reduce burn-in defects and increase the number of substrate chips, the lamp test pin can be integrated with signal pin 111 of the third region b3. (See reference) Figure 11Multiple signal pins 111 located in the third region b3 are arranged along the pixel row direction X. These signal pins 111 are used to transmit signals when the display panel 10 is displaying normally, and multiple target pins 111a among the signal pins 111 can also be used to transmit signals during the LED testing of the display panel 10. That is, the multiple target pins 111a among the signal pins 111 can be multiplexed. The third region b3 is located on the side of the first region b1 away from the display area 101a.

[0102] In addition, after integrating the lamp test pin with multiple signal pins 111, in order to make the target pin 111a in the signal pin 111 directly applicable to the lamp test, the tilt angle and width of the signal pin 111 can be adjusted appropriately.

[0103] refer to Figure 11 The extension direction of the central axis t of each signal pin 111 intersects the pixel column direction Y. That is, the signal pins 111 are angled. Optionally, the angle between the extension direction of the central axis t of each signal pin 111 and the pixel column direction Y... The range is from 8 degrees to 15 degrees.

[0104] refer to Figure 11 The multiple target pins 111a include: a first type of target pin 111a1 and a second type of target pin 111a2. The first type of target pin 111a1 is used to transmit DC signals, and the second type of target pin 111a2 is used to transmit AC signals. The width of the first type of target pin 111a1 along the pixel row direction X is greater than the width of the second target pin 111a along the pixel row direction X. By making the width of the first type of target pin 111a1, which transmits DC signals, wider along the pixel row direction X, the loading time for DC signal transmission can be reduced.

[0105] Optionally, the first type of target pin 111a1 can be designed by connecting two or more signal pins 111 in parallel.

[0106] Because the widths of the first type of target pin 111a1 and the second type of target pin 111a2 are different (due to unequal Pitch PIN designs), the pin widths and spacing of the LED testing-related signals in the third region b3 can be adjusted to meet the LED testing process requirements. Furthermore, the tilted design of the signal pin 111 allows for crimping alignment compensation. During LED testing, the signal pin 111 in the third region b3 can be directly crimped. This design meets the requirements of the electrical test structure and avoids the adverse effects of separate designs for LED testing pins and signal pins 111. Moreover, it eliminates the need for dummy pins between the MDL and EAC dicing channels, which helps increase the number of substrates that can be laid out, and also solves the burn-in problem caused by the cross-line design of conventional large-size product dicing channels.

[0107] It should be noted that since the LED test pin and the signal pin 111 of the third area b3 are integrated and both are located in the third area b3 near the display area 101a in the MDL cut channel, therefore, refer to Figure 12 When the display panel 10 leaves the factory, the signal pin 111 is still retained.

[0108] refer to Figure 11 Of the multiple signal pins 111 shown, from left to right, the four leftmost pins are touch-on-cell (TP) pins, the fifth is the VSS trace pin, and the sixth is the VDD trace pin. Other pins can be array substrate row drive (GOA) pins, reset (vinit) pins, high (VGH) pins, low (VGL) pins, lamp test switch (ET Switch) pins, and drive pins, etc. Among these, the VGH, VGL, and vinit pins can be used to transmit DC signals. The ET Switch pin controls the on / off state of the lamp test circuit, and it can write the data signal required for lamp activation to the display area.

[0109] In this embodiment, since the second region b2 is a bent area, when the display panel 10 is shipped, the portion of the second region b2 away from the display area 101a will be bent to the back side of the display panel. The positional relationships of the various regions described in the above embodiments are all based on the state of the second region b2 when it is not bent.

[0110] In the embodiments of this application, reference is made to Figure 12In addition to the first region b1, the second region b2, and the third region b3, the peripheral area 101b also includes the fourth region b4, the fifth region b5, the sixth region b6, and the seventh region b7. Specifically, the first region b1 can be the driver circuit pin setting (IC) area, the second region b2 is the bending area, the third region b3 can be the flexible circuit board on panel (FPC on panel, FOP) area, the fourth region b4 can be the first fanout area (fanout1), the fifth region b5 can be the second fanout area (fanout2), the sixth region b6 can be the detection transistor setting (cell test) area, and the seventh region b7 can be the output line bridge (OLB) area.

[0111] Additionally, refer to Figure 12 The display panel 10 also includes sub-pixels located in the display area 101a and arranged in an array. Each data line 102 can be connected to a column of sub-pixels arranged along the pixel column direction Y, for providing a signal to the column of sub-pixels. Figure 12 The subpixels shown do not represent the actual shape of the subpixels, and Figure 12 Data line 102 is not shown.

[0112] refer to Figure 2 The first region b1 also includes: a driver circuit input pin b11, a driver circuit first output pin b12, a driver circuit second output pin b13, and a driver circuit third output pin b14. In this embodiment, the first detection pin 103 and the second detection pin 105 are located between the driver circuit input pin b11 and the driver circuit first output pin b12.

[0113] In summary, this application provides a display panel including a plurality of first detection pins and a plurality of second detection pins, arranged in two rows. Therefore, given the limited dimensions of the substrate along the pixel row direction in the display panel, the number of detection pins can be increased, thereby increasing the detection ratio of sub-pixels in the display panel, reducing the probability of missed detections, and ensuring the yield of the display panel.

[0114] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 13 The display device may include a power supply component 20 and a display panel 10 provided in the above embodiments.

[0115] The power supply component 20 can be used to supply power to the display panel 10.

[0116] Optionally, the display device can be any suitable display device such as an organic light-emitting diode (OLED) display device, a liquid crystal display (LCD) display device, or a quantum dot (QLED) display device. For example, the display device includes, but is not limited to, any product or component with display functionality such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books.

[0117] Since the display device can have essentially the same technical effects as the display panels described in the preceding embodiments, for the sake of brevity, the technical effects of the display device will not be described again here.

[0118] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: A substrate having a display area and a peripheral area surrounding the display area; At least a plurality of data lines located in the display area, the plurality of data lines extending along the pixel column direction and arranged along the pixel row direction; A plurality of first detection pins are located in a first region within the peripheral area and arranged along the pixel row direction, with a gap between each pair of adjacent first detection pins, and the first region and the display area are arranged along the pixel column direction; A plurality of first detection traces, each corresponding to one of the plurality of first detection pins and located at least in the first region, wherein the first end of each first detection trace is connected to a corresponding first detection pin and the second end is connected to a data line; A plurality of second detection pins are located in the first region and on the side of the plurality of first detection pins away from the display area, the plurality of second detection pins being arranged along the pixel row direction; A plurality of second detection traces, each corresponding to one of the plurality of second detection pins and located at least in the first region, wherein the first end of each second detection trace is connected to a corresponding second detection pin, and the second end passes through the gap and is connected to a data line; A plurality of first dummy detection pins are located in the first region and on at least one side of the plurality of first detection pins. The plurality of first dummy detection pins and the plurality of first detection pins are arranged along the pixel row direction. Each first dummy detection pin is not connected to the first detection trace. And a plurality of second dummy detection pins located in the first region and on at least one side of the plurality of second detection pins, the plurality of second dummy detection pins and the plurality of second detection pins being arranged along the pixel row direction, each of the second dummy detection pins and the second detection trace being unconnected.

2. The display panel according to claim 1, characterized in that, The plurality of second detection pins and the plurality of first detection pins are arranged in an alternating pattern.

3. The display panel according to claim 2, characterized in that, Each second detection pin is connected to a second detection trace located in the gap between two adjacent first detection pins, and there is a second detection trace in the gap between two adjacent first detection pins; The orthographic projection of each of the second detection pins on the substrate and the orthographic projection of the corresponding gap on the substrate are arranged along the pixel column direction.

4. The display panel according to claim 3, characterized in that, The line segment at the connection point of the second detection trace to the second detection pin, as well as the line segment of the second detection trace located in the gap, both extend along the direction of the pixel column.

5. The display panel according to claim 1, characterized in that, The display panel also includes: At least a plurality of dummy detection traces located in the first region, wherein the dummy detection traces are not connected to either the first dummy detection pin or the second dummy detection pin, and the dummy detection traces are not connected to the data line.

6. The display panel according to any one of claims 1 to 5, characterized in that, The surrounding area includes a second area located between the display area and the first area; The display panel further includes: power traces located in the first metal layer of the display panel; the power traces include: The first part is located on the side of the second region away from the display area; The second part, located in the second region, includes multiple connecting lines, with a gap between each pair of adjacent connecting lines; And a third part, which is located on the side of the second region closer to the display area; Wherein, the first end of the first part is used to connect to the power supply circuit, the second end of the first part is connected to the first end of the plurality of connecting lines, the second end of the plurality of connecting lines is connected to the first end of the third part, the second end of the third part is connected to the structure in the display area of ​​the display panel, and the width of the first part and the third part is greater than the width threshold.

7. The display panel according to claim 6, characterized in that, The portions of the first detection trace and the second detection trace located in the second region are located in the first metal layer, and the portions of the first detection trace and the second detection trace located outside the second region are located in the second metal layer of the display panel; The width of each of the plurality of first detection traces and the plurality of second detection traces is smaller than the width of the gap between the connecting lines. The portion of the target detection trace in the first detection trace and the second detection trace located in the second region is located in the gap between the connecting lines. The orthographic projection of the portion of the target detection trace other than that located in the second region on the substrate at least partially overlaps with the orthographic projection of the power supply trace on the substrate.

8. The display panel according to claim 7, characterized in that, The display panel further includes: an insulating layer located between the first metal layer and the second metal layer; each of the plurality of first detection traces and the plurality of second detection traces includes: A first line segment, the first line segment being located on the side of the second region away from the display area, the first line segment being located in the second metal layer; A first connecting portion is located on the side of the second region away from the display area and on the side of the first line segment close to the second region. The first connecting portion is located in a first through hole in the insulating layer and is connected to the first line segment. The second line segment has a first end located on the side of the second region away from the display area, and the first end of the second line segment is connected to the first connecting portion. The second end of the second line segment passes through the second region and is located on the side of the second region closer to the display area. The second line segment is located in the first metal layer. The second connecting part is located on the side of the second region closer to the display area. The second connecting part is located in the second via in the insulating layer and is connected to the second end of the second line segment. The third line segment is located on the side of the second region closer to the display area, and on the side of the second connecting portion away from the second region. The third line segment is connected to the second connecting portion and is located in the second metal layer.

9. The display panel according to claim 8, characterized in that, The first part of the power supply trace has a first opening, and the first connection part of the target detection trace is located inside the first opening and has a gap with the first opening; The third part of the power supply trace has a second opening, and the second connection part of the target detection trace is located inside the second opening and has a gap with the second opening.

10. The display panel according to claim 9, characterized in that, The first metal layer is a source / drain layer, and the second metal layer is a gate layer.

11. The display panel according to any one of claims 1 to 5, characterized in that, The peripheral area includes a third area located in the first area and away from the display area; the display panel further includes: Multiple signal pins located in the third region, the multiple signal pins being arranged along the pixel row direction; The plurality of signal pins are used to transmit signals when the display panel is displaying normally, and the plurality of target pins among the plurality of signal pins are also used to transmit signals when the display panel is tested for lighting.

12. The display panel according to claim 11, characterized in that, The extension direction of the central axis of each of the signal pins intersects the direction of the pixel column.

13. The display panel according to claim 12, characterized in that, The angle between the extension direction of the central axis of each signal pin and the direction of the pixel column ranges from 8 degrees to 15 degrees.

14. The display panel according to claim 11, characterized in that, The plurality of target pins includes a first type of target pins and a second type of target pins; The first type of target pin is used to transmit DC signals, and the second type of target pin is used to transmit AC signals. The width of the first type of target pin along the pixel row direction is greater than the width of the second type of target pin along the pixel row direction.

15. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in any one of claims 1 to 14; The power supply component is used to supply power to the display panel.

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