Display panel, driving method thereof, and display device

Abstract

This invention discloses a display panel, its driving method, and a display device. The display panel includes a gate driving circuit, which comprises multiple cascaded shift registers. Each shift register is connected to the corresponding gate line of its own stage. The scan signal output by the shift register includes a first pulse signal and a second pulse signal. Within a display frame, the second pulse signal of the scan signal output by the Nth stage shift register overlaps with the first pulse signal of the scan signal output by the (N+X)th stage shift register. Here, N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7. Because this solution minimizes the number of rows between the overlapping pixels, even if coupling occurs between the two overlapping pulse signals, dark lines caused by inconsistent brightness can be eliminated during brightness superposition, thereby improving display quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] At present, display panels are widely used in electronic devices such as mobile phones, tablets and smart wear, and with the development of display technology, the requirements for display quality of display panels are also getting higher and higher.

[0003] The existing display panel has the phenomenon of display dark line, which seriously affects the display quality and user experience. SUMMARY

[0004] The present application provides a display panel, a driving method thereof and a display device to improve the display quality of the display panel.

[0005] According to an aspect of the present application, a display panel is provided, comprising a gate drive circuit, the gate drive circuit comprising a plurality of cascaded shift registers, each of the shift registers being connected with a gate line corresponding to the shift register of the current stage;

[0006] The scan signal output by the shift register comprises a first pulse signal and a second pulse signal, and in a display frame, the second pulse signal of the scan signal output by the Nth shift register overlaps with the first pulse signal of the scan signal output by the N+Xth shift register.

[0007] Wherein, N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

[0008] Optionally, in a display frame, the second pulse signal of the scan signal output by the Nth shift register overlaps with the first pulse signal of the scan signal output by the N+Xth shift register.

[0009] Optionally, X is equal to 2.

[0010] Optionally, it further comprises a pixel circuit, the pixel circuit comprising a data writing module, a compensation module, a driving module and a light emitting module, the driving module and the light emitting module being connected between the first power supply line and the second power supply line.

[0011] The control end of the data writing module is connected with the gate line, the first end of the data writing module accesses the data voltage, the second end of the data writing module is connected with the first end of the driving module, the compensation module is connected between the second end and the control end of the driving module, and the data writing module is used for transmitting the data voltage to the control end of the driving module according to the first pulse signal of the scanning signal output by the shift register, and resetting the first end of the driving module according to the second pulse signal of the scanning signal output by the shift register.

[0012] Wherein, N is less than the number of rows of the pixel circuit.

[0013] Optionally, each of the shift registers comprises an input end and an output end, the input end of the first stage shift register accesses a trigger signal, and is used for outputting a scanning signal with the same pulse width as the trigger signal from the output end according to the trigger signal and transmitting a shift signal to the input end of the next stage shift register.

[0014] Wherein, the trigger signal is a double pulse signal.

[0015] Optionally, the shift register comprises a first input module, a second input module, a first output module and a second output module.

[0016] The output end of the first input module is connected with the control end of the first output module, and the first input module is used for transmitting the input signal at the input end to the control end of the first output module in response to a first clock signal.

[0017] The input end of the second input module serves as the trigger signal input end of the shift register, and is used for controlling the potential of the control end of the second output module.

[0018] The output end of the first output module and the output end of the second output module are both connected to the output end of the shift register, the first output module is used for outputting a first level signal according to the potential of the control end, and the second output module is used for outputting a second level signal according to the potential of the control end.

[0019] Preferably, the first input module comprises a first transistor, the second input module comprises a second transistor, the first output module comprises a third transistor and a first capacitor, and the second output module comprises a fourth transistor and a second capacitor.

[0020] The gate of the first transistor is connected to the first clock signal, the first pole of the first transistor is used as the input terminal of the first input module, the second pole of the first transistor is connected to the gate of the third transistor, the first pole of the third transistor is connected to a first potential signal, the second pole of the third transistor is used as the output terminal of the first output module, and the first capacitor is connected between the first pole and the gate of the third transistor.

[0021] The gate of the second transistor is connected to the first clock signal, the first pole of the second transistor is used as the input terminal of the second input module, the second pole of the second transistor is connected to the gate of the fourth transistor, the first pole of the fourth transistor is connected to a second clock signal, the second pole of the fourth transistor is connected to the second pole of the third transistor, and the second capacitor is connected between the gate and the second pole of the fourth transistor.

[0022] Optionally, the shift register further comprises a first output control module and a second output control module, the output terminal of the first output control module is connected to the control terminal of the first output module, and the output terminal of the second output control module is connected to the control terminal of the second output module.

[0023] Preferably, the first output control module comprises a fifth transistor, the gate of the fifth transistor is connected to the output terminal of the second input module, the first pole of the fifth transistor is connected to the first clock signal, and the second pole of the fifth transistor is the output terminal of the first output control module.

[0024] The second output control module comprises a sixth transistor and a seventh transistor, the gate of the sixth transistor is connected to the control terminal of the first output module, the first pole of the sixth transistor is connected to the first potential signal, the second pole of the sixth transistor is connected to the first pole of the seventh transistor, the second pole of the seventh transistor is the output terminal of the second output control module, and the gate of the seventh transistor is connected to the second clock signal.

[0025] Optionally, the shift register further comprises a protection module, which is connected between the output terminal of the second input module and the control terminal of the second output module.

[0026] Preferably, the protection module comprises an eighth transistor, the gate of the eighth transistor is connected to a second potential signal, the first pole of the eighth transistor is connected to the output terminal of the second input module, and the second pole of the eighth transistor is connected to the control terminal of the second output module.

[0027] According to another aspect of the present application, there is provided a driving method of a display panel, the display panel comprising a gate driving circuit, the gate driving circuit comprising a plurality of cascaded shift registers, each of the shift registers being connected with a gate line corresponding to the shift register; wherein the scan signal outputted by the shift register comprises a first pulse signal and a second pulse signal;

[0028] The driving method of the display panel comprises:

[0029] In a display frame, when the second pulse signal outputted by the Nth shift register, the first pulse signal outputted by the N+Xth shift register is controlled;

[0030] Wherein, N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

[0031] According to another aspect of the present application, there is provided a display device comprising the display panel provided by any of the embodiments of the present application.

[0032] The technical solution of the embodiments of the present application, in a display frame, by setting the second pulse signal of the scan signal outputted by the Nth shift register and the first pulse signal of the scan signal outputted by the N+Xth shift register to overlap, wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7, so that the two adjacent rows of pixels are charged at the same time. Since the number of rows of pixels between the two mutually overlapping scan signals is small, even if coupling occurs between the two mutually overlapping pulse signals, the dark line caused by the inconsistency of brightness can be eliminated in the process of brightness superposition, thereby improving the display quality.

[0033] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0035] Figure 1 A structural schematic diagram of a display panel provided by the embodiments of the present application;

[0036] Figure 2 A timing waveform diagram of a scan signal provided by the embodiments of the present application;

[0037] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0039] Figure 5 A timing waveform diagram of another scanning signal provided in an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of a shift register provided in an embodiment of the present invention;

[0042] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0043] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0044] Figure 10 A timing control waveform diagram of a gate driving circuit provided in an embodiment of the present invention;

[0045] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It is to be understood that the terminology "first", "second" and the like used in the specification and the claims of the application as well as the appended drawings is merely intended to distinguish between similar objects and not necessarily for describing a specific sequential or chronological order. It is to be understood that the use of the terms "including", "comprising" or "having" and variations thereof herein is intended to cover the respective steps, units, processes, methods, objects, items and the like subject maters contained therein, but not to preclude or exclude the presence or addition of one or more other steps, units, processes, methods, objects, items or the like annually thereof.

[0048] Figure 1 A structural schematic diagram of a display panel provided by an embodiment of the application is shown in Figure 1 The display panel 10 provided by the embodiment comprises a gate drive circuit 11, the gate drive circuit 11 comprises a plurality of cascaded shift registers 110, each shift register 110 is connected with a gate line 20 corresponding to the shift register 110; wherein the scan signal output by the shift register 110 comprises a first pulse signal and a second pulse signal, in a display frame, the second pulse signal of the scan signal SN output by the Nth shift register 110 overlaps with the first pulse signal of the scan signal S(N+X) output by the (N+X)th shift register 110; wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

[0049] Specifically, the gate drive circuit 11 can be arranged in the side frame of the display panel 10, and the gate drive circuit 11 is configured to provide a scan signal to the gate line 20, wherein the gate lines 20 extending in the X direction are arranged in sequence in the Y direction.

[0050] The gate drive circuit 11 comprises a plurality of cascaded shift registers 110, each shift register 110 is connected with a gate line 20, and the scan signal output by each shift register 110 can be transmitted to a pixel through the gate line, and is used as a driving signal of the pixel; meanwhile, the scan signal is also used as a shift signal of the shift register 110.

[0051] In the embodiment, the scan signal output by the shift register 110 is a double pulse signal. Figure 2 A timing waveform diagram of a scan signal provided by an embodiment of the application is shown in Figure 2The scan signal output by the Nth shift register 110 includes a first pulse signal and a second pulse signal, the scan signal output by the N+1th shift register 110 is shifted on the basis of the scan signal output by the Nth shift register 110, and the scan signal output by the N+2th shift register 110 is shifted on the basis of the scan signal output by the N+1th shift register 110, and so on, so as to realize the step-by-step shift output of the scan signal. The scan signal output by the next stage shift register 110 is delayed from the scan signal output by the current stage shift register 110, and the delay time can be set according to the pulse width of the scan signal.

[0052] In the process of the shift output of the scan signal, the upper and lower two rows (non-adjacent) of the scan signal may overlap. In this embodiment, the pulse width between the first pulse signal and the second pulse signal is reduced, so that the second pulse signal of the scan signal SN output by the Nth shift register 110 overlaps with the first pulse signal of the scan signal S(N+X) output by the N+Xth shift register 110, and the Nth shift register 110 and the N+Xth shift register 110 simultaneously output the effective scan signal, wherein X is a positive integer greater than or equal to 2 and less than or equal to 7. That is, the maximum interval of the overlapping scan signals is 7 rows. Since the number of interval rows is small, even if coupling occurs between the two pulse signals that overlap with each other, the dark line caused by the inconsistent brightness can be eliminated in the process of brightness superposition, so as to improve the display quality.

[0053] With reference to the foregoing Figure 2 In a display frame, the second pulse signal of the scan signal SN output by the Nth shift register 110 overlaps with the first pulse signal of the scan signal S(N+X) output by the N+Xth shift register 110. That is, when the Nth shift register 110 outputs the second pulse signal, the N+Xth shift register 110 outputs the first pulse signal to charge the Nth pixel and the N+Xth pixel at the same time. The purpose of this setting is to facilitate the timing design and reduce the difficulty.

[0054] The display panel provided by the embodiment of the present application is characterized in that, in a display frame, the second pulse signal of the scan signal output by the Nth shift register overlaps with the first pulse signal of the scan signal output by the N+Xth shift register, wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7, so that the two adjacent rows of pixels are charged at the same time. Since the number of interval rows between the two rows of pixels that overlap with each other is small, even if coupling occurs between the two pulse signals that overlap with each other, the dark line caused by the inconsistent brightness can be eliminated in the process of brightness superposition, so as to improve the display quality.

[0055] Figure 3 FIG. 2 is a structural schematic diagram of another display panel provided by the embodiment of the present application, Figure 4A structural schematic diagram of a pixel circuit provided for an embodiment of the present application is shown in reference to Figure 3 and Figure 4 On the basis of the above technical solution, optionally, the display panel further comprises a pixel circuit 30, the pixel circuit 30 comprises a data writing module 302, a compensation module 303, a driving module 301 and a light emitting module 304, the driving module 301 and the light emitting module 304 are connected between the first power supply line and the second power supply line; the control end of the data writing module 302 is connected with the gate line 20, the first end of the data writing module 302 is connected with the data voltage Vdata, the second end of the data writing module 302 is connected with the first end of the driving module 301, and the compensation module 303 is connected between the second end and the control end of the driving module 301.

[0056] The pixel circuit 30 is arranged in an array. During display, for two adjacent shift registers 110, when the first pulse signal of the scan signal corresponding to the upper shift register 110 ends, the first pulse signal of the scan signal corresponding to the lower shift register 110 starts to output. In general, each shift register 110 is connected with a gate line 20, the gate line 20 is connected with a row of pixel circuits 30, the shift register 110 outputs the scan signal to the gate line 20, and the scan signal on the gate line 20 controls the charging of the row of pixel circuits connected with the gate line 20.

[0057] Specifically, the gate line 20 is connected with the control end of the data writing module 302 in the pixel circuit 30. In the data writing stage, the data writing module 302 is turned on in response to the first pulse signal of the scan signal, and the data voltage Vdata on the data line Data is transmitted to the control end of the driving module 301 through the compensation module 303, and the compensation module 303 is used for compensating the threshold voltage of the driving module 301. In the reset stage, the data writing module 302 is turned on in response to the second pulse signal of the scan signal, and the data voltage Vdata on the data line Data is transmitted to the first end of the driving module 301 (at this time, the compensation module 303 is turned off), and the potential of the first end of the driving module 301 is reset, so that the bias state of the driving module 301 is the same, which ensures the uniformity of the driving current output by the driving module 301, and is beneficial to improve the display uniformity. Here, N is less than the number of rows of pixel circuits 30.

[0058] In the prior art, for a double-pulse scanning signal, the second pulse signal of the scanning signal S1 output by the first-stage shift register 110 coincides with the first pulse signal of the scanning signal S9 output by the ninth-stage shift register 110, and thus when the data writing module 302 of the first row of pixel circuits 30 is turned on in response to the second pulse signal of the scanning signal S1, the second pulse signal of the scanning signal S1 couples the first pulse signal of the scanning signal S9 output by the ninth-stage shift register 110, thereby pulling down the first pulse signal of the scanning signal S9 output by the ninth-stage shift register 110, and further making the data voltage Vdata of the ninth row of pixel circuits 30 more fully written (the data writing module 302 includes a P-type transistor), resulting in insufficient opening of the driving module 301 and affecting the driving current, and thus a dark line appears. For example, taking a smart watch as an example, the display panel thereof is circular, and in the scanning process from bottom to top, the second pulse signal of the scanning signal S1 output by the first-stage shift register 110 pulls down the first pulse signal of the scanning signal S9 output by the ninth-stage shift register 110, so that a circular arc-shaped dark line appears at the bottom of the display panel.

[0059] To eliminate the dark line, the embodiment of the present application reduces the time interval between the first pulse signal and the second pulse signal of the scanning signal, and preferably, X = 2. Figure 5 Another timing waveform diagram of the scanning signal provided by the embodiment of the present application is shown in FIG. 3, which is based on the timing waveform diagram of the scanning signal shown in FIG. 2. Figure 5 For example, taking N = 1 and X = 2 as an example, in the embodiment, the second pulse signal of the scanning signal S1 output by the first-stage shift register 110 coincides with the first pulse signal of the scanning signal S3 output by the third-stage shift register 110, and thus when the data writing module 302 of the first row of pixel circuits 30 is turned on in response to the second pulse signal of the scanning signal S1, the second pulse signal of the scanning signal S1 couples the first pulse signal of the scanning signal S3 output by the third-stage shift register 110. The scanning signal S2 output by the second-stage shift register 110 is a normal signal, and coupling with the scanning signal S4 output by the fourth-stage shift register 110 does not pull down the first pulse signal of the scanning signal S4 output by the fourth-stage shift register 110, and thus the subsequent picture can be normally displayed.

[0060] Here, since the first row of pixels and the third row of pixels are relatively close, even if the second pulse signal of the first row of scanning signals S1 couples and pulls down the first pulse signal of the third row of scanning signals S3, so that the third row of pixels are relatively dark, in the case of normal display of the first row of pixels, in the process of brightness superposition, the human eye cannot perceive the phenomenon of inconsistent brightness, and thus the dark line caused by inconsistent brightness can be eliminated, thereby improving the display quality.

[0061] Continuing to refer toFigure 4 Optionally, the pixel circuit 30 further comprises a storage module 305, a first light-emitting control module 306 and a second light-emitting control module 307. The storage module 305 is connected between the first power line and the control end of the driving module 301. The first light-emitting control module 306 is connected between the first power line and the first end of the driving module 101. The second light-emitting control module 307 is connected between the second end of the driving module 301 and the first end of the light-emitting module 304. The second end of the light-emitting module 304 is connected with the second power line. The first power line is used for transmitting the first power voltage VDD, and the second power line is used for transmitting the second power voltage VSS. The storage module 305 is used for storing the voltage of the control end of the driving module 301. In the light-emitting stage, the first light-emitting control module 306 and the second light-emitting control module 307 are turned on in response to the light-emitting control signal (not shown), the first power voltage VDD is transmitted to the first end of the driving module 301, the driving module 301 generates a driving current according to the voltage of the control end and the first end, and the light-emitting module 304 is driven to emit light.

[0062] Optionally, the pixel circuit 30 further comprises a first initialization module 308 and a second initialization module 309. The first initialization module 308 is connected between the first initialization signal line and the control end of the driving module 301, and is used for transmitting the first initialization voltage Vref1 on the first initialization signal line to the control end of the driving module 301, so as to initialize the potential of the control end of the driving module 301. The second initialization module 309 is connected between the second initialization signal line and the first end of the light-emitting module 304, and is used for transmitting the second initialization voltage Vref2 on the second initialization signal line to the first end of the light-emitting module 304, so as to initialize the potential of the first end of the light-emitting module 304.

[0063] It should be noted that the transistors included in each module in the pixel circuit 30 can be P-type tubes or N-type tubes, and the present embodiment does not limit this, and the specific working principle will not be described here.

[0064] Figure 6 A structure schematic diagram of a gate drive circuit provided by the embodiment of the present application is shown in FIG. 1. Figure 6 On the basis of the above technical solutions, the gate drive circuit comprises a plurality of cascaded shift registers 110. Each shift register 110 comprises an input end IN and an output end OUT. The input end IN of the first shift register 110 is connected to a trigger signal SIN. The first shift register 110 is used for outputting a scanning signal with the same period as the trigger signal SIN from the output end OUT according to the trigger signal SIN, and transmitting a shift signal to the input end IN of the next shift register 110. Here, the trigger signal SIN is a double-pulse signal, and therefore the scanning signal output by the shift register 110 is also a double-pulse signal.

[0065] The shift register 110 further comprises a first clock signal input end SC1 and a second clock signal input end SC2. In the embodiment, the first clock signal end SC1 of the odd-numbered stage shift register 110 and the second clock signal end SC2 of the even-numbered stage shift register 110 are connected with the first clock signal line CLK1, and the second clock signal end SC2 of the odd-numbered stage shift register 110 and the first clock signal end SC1 of the even-numbered stage shift register 110 are connected with the second clock signal line CLK2, so as to realize the shift output of the scan driving circuit 100.

[0066] Figure 7 A structural diagram of the shift register provided by the embodiment of the present application is shown in FIG. 1. Figure 7 On the basis of the above technical solutions, the shift register 110 comprises a first input module 101, a second input module 102, a first output module 103 and a second output module 104. The output end of the first input module 101 is connected with the control end of the first output module 103, and the first input module 101 is configured to transmit the input signal at the input end thereof to the control end of the first output module 103 in response to the first clock signal SCK1. The input end of the second input module 102 serves as the input end IN of the shift register 110 and is configured to control the potential of the control end of the second output module 104. The output end of the first output module 103 and the output end of the second output module 104 are both connected with the output end OUT of the shift register 110, and the first output module 103 is configured to output a first voltage level signal VC1 according to the potential of the control end thereof, and the second output module 104 is configured to output a second voltage level signal VC2 according to the potential of the control end thereof.

[0067] The input end of the second input module 102 in the first stage shift register 110 inputs a start signal SIN, and the input end of the second input module 102 in each of the other stages of shift registers 110 is connected with the output end OUT of the previous stage shift register 110. The start signal SIN is a screen body signal on the display panel.

[0068] Specifically, the first input module 101 can be turned on in response to the first clock signal SCK1, and transmit the input signal at the input end thereof to the control end of the first output module 103, so as to control the potential of the control end of the first output module 103, i.e. the potential at the first node N1. The second input module 102 can be turned on according to the signal at the control end (not shown in the figure) thereof, and transmit the signal (for example, the output signal of the previous stage shift register 110) at the input end thereof to the control end of the second output module 104, so as to control the potential of the control end of the second output module 104, i.e. the potential at the second node N2.

[0069] The output end of the first output module 103 is connected with the output end OUT of the first stage shift register 110, for outputting a first level signal VC1 when being turned on according to the potential of the first node N1. The output end of the second output module 104 is also connected with the output end OUT of the first stage shift register 110, for outputting a second level signal VC2 when being turned on according to the potential of the second node N2. The first level signal is different from the second level signal, for example, the first level signal VC1 is a low level signal VGL, and the second level signal VC2 is a high level signal VGH; or the first level signal VC1 is a high level signal VGH, and the second level signal VC2 is a low level signal VGL.

[0070] Figure 8 Another structure diagram of a shift register provided by the embodiment of the present application is shown in FIG. 4. Figure 8 On the basis of the above technical solution, optionally, the shift register 110 further comprises a first output control module 105 and a second output control module 106, the output end of the first output control module 105 is connected with the control end of the first output module 103, and the output end of the second output control module 106 is connected with the control end of the second output module 104. The control end of the first output control module 105 is connected with the output end of the second input module 102 at the third node N3.

[0071] In the embodiment, the input end of the first input module 101 can be connected with a low level signal VGL, the input end of the first output module 103 can be connected with a high level signal VGH, and the input end of the second output module 104 can be connected with a second clock signal SCK2.

[0072] Figure 9 Another structure diagram of a shift register provided by the embodiment of the present application is shown in FIG. 4. Figure 9On the basis of each of the above technical solutions, optionally, the first input module 101 comprises a first transistor M1, the second input module 102 comprises a second transistor M2, the first output module 103 comprises a third transistor M3 and a first capacitor C1, and the second output module 104 comprises a fourth transistor M4 and a second capacitor C2; a gate of the first transistor M1 is connected to a first clock signal SCK1, a first electrode of the first transistor M1 serves as an input end of the first input module 101, a second electrode of the first transistor M1 is connected to a gate of the third transistor M3, a first electrode of the third transistor M3 is connected to a high-level signal VGH, a second electrode of the third transistor M3 serves as an output end of the first output module 103, and the first capacitor C1 is connected between the first electrode and the gate of the third transistor M3; a gate of the second transistor M2 is connected to the first clock signal SCK1, a first electrode of the second transistor M2 serves as an input end of the second input module 102, a second electrode of the second transistor M2 is connected to a gate of the fourth transistor M4, a first electrode of the fourth transistor M4 is connected to a second clock signal SCK2, a second electrode of the fourth transistor M4 is connected to the second electrode of the third transistor M3, and the second capacitor C2 is connected between the gate and the second electrode of the fourth transistor M4.

[0073] The first output control module 105 comprises a fifth transistor M5, a gate of the fifth transistor M5 is connected to an output end of the second input module 102, a first electrode of the fifth transistor M5 is connected to the first clock signal SCK1, and a second electrode of the fifth transistor M5 serves as an output end of the first output control module 105; the second output control module 106 comprises a sixth transistor M6 and a seventh transistor M7, a gate of the sixth transistor M6 is connected to a control end of the first output module 103, a first electrode of the sixth transistor M6 is connected to a first potential signal V1, a second electrode of the sixth transistor M6 is connected to a first electrode of the seventh transistor M7, a second electrode of the seventh transistor M7 serves as an output end of the second output control module 106, and a gate of the seventh transistor M7 is connected to the second clock signal SCK2.

[0074] The shift register 11 further comprises a protection module 107 connected between the output end of the second input module 102 and the control end of the second output module 104. Specifically, the protection module 107 comprises an eighth transistor M8, a gate of the eighth transistor M8 is connected to a low-level signal VGL, a first electrode of the eighth transistor M8 is connected to the output end of the second input module 102, and a second electrode of the eighth transistor M8 is connected to the control end of the second output module 104. That is, the eighth transistor M8 is connected between the second node N2 and the third node N3, and the eighth transistor M8 can be in a constant conduction state in response to the low-level signal VGL.

[0075] Figure 10 A timing control waveform diagram of a gate drive circuit provided by the embodiment of the present application is suitable forFigure 9 The gate drive circuit is combined with Figure 9 and Figure 10 The working process of the gate drive circuit provided by the embodiment includes at least a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8. The start signal SIN can be provided by a start signal line, the first clock signal SCK1 and the second clock signal SCK2 can be provided by corresponding clock signal lines respectively.

[0076] In the first stage t1, the start signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level. Therefore, the first transistor M1 and the second transistor M2 are turned on, the low-level signal VGL is transmitted to the gate of the third transistor M3 through the first transistor M1, the third transistor M3 is turned on, the high-level signal VGH is transmitted to the output end OUT of the shift register 110 through the third transistor M3, and the output end OUT outputs a high level. The signal inputted by the input end of the second input module 102 is transmitted to the gate of the fourth transistor M4 through the second transistor M2. When the shift register 110 is a first-stage shift register 110, the input end of the second input module 102 inputs the start signal SIN, and the fourth transistor M4 is turned off. Therefore, the shift register 110 outputs the high-level signal VGH in the first stage t1. When the shift register 110 is a shift register 110 other than the first stage, the signal inputted by the input end of the second input module 102 is the output signal of the previous-stage shift register 110. Since the first clock signal SCK1 is at a low level, the first transistor M1 is in a turned-on state, the output end OUT of the shift register 110 is at a high level, and the fourth transistor M4 is turned off. Therefore, the output end OUT still outputs the high-level signal VGH.

[0077] It should be noted that the subsequent stages are described by taking the first-stage shift register 110 as an example.

[0078] In the second stage t2, the start signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level. Therefore, the first transistor M1 and the second transistor M2 are turned off, and the seventh transistor M7 is turned on. The low-level signal VGL stored in the first capacitor C1 makes the third transistor M3 and the sixth transistor M6 continuously turned on, the high-level signal VGH is transmitted to the second node N2 through the sixth transistor M6 and the seventh transistor M7, and the fourth transistor M4 remains in a turned-off state. At the same time, the high-level signal VGH is transmitted to the output end OUT of the shift register 110 through the third transistor M3, and the output end OUT outputs the high-level signal VGH.

[0079] In the third stage t3, the start signal SIN is low, the first clock signal SCK1 is low, and the second clock signal SCK2 is high. Therefore, the first transistor M1 and the second transistor M2 are turned on, the first node N1 is at a low potential corresponding to the low signal VGL, the third transistor M3 is turned on, and the high signal VGH is transmitted to the output end OUT of the shift register 110. Since the start signal SIN is low, the second node N2 and the third node N3 are also at low potentials, the fourth transistor M4 and the fifth transistor M5 are turned on, the low of the first clock signal SCK1 is transmitted to the first node N1, and the third transistor M3 is maintained in the turned-on state. Meanwhile, the high of the second clock signal SCK2 is transmitted to the output end OUT of the shift register 110 through the fourth transistor M4. Therefore, in the third stage t3, the third transistor M3 and the fourth transistor M4 are turned on at the same time, so that the output end OUT of the shift register 110 outputs the high signal VGH.

[0080] In the fourth stage t4, the start signal SIN is low, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. Therefore, the first transistor M1 and the second transistor M2 are turned off, the voltage stored by the second capacitor C2 (the low signal VGL in the previous stage) makes the fifth transistor M5 and the fourth transistor M4 turned on, the high of the first clock signal SCK1 makes the third transistor M3 turned off, the high of the second clock signal SCK2 is transmitted to the output end OUT of the shift register 110 through the fourth transistor M4, and the output end OUT outputs the high signal VGH.

[0081] In the fifth stage t5, the start signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is low. The voltage stored by the first capacitor C1 (corresponding to the high signal VGH in the previous stage) makes the third transistor M3 remain in the turned-off state, the voltage stored by the second capacitor C2 (the low signal VGL in the previous stage) makes the fourth transistor M4 continue to be turned on, the low of the second clock signal SCK2 is transmitted to the output end OUT of the shift register 110, and the output end OUT outputs the low signal VGL. Since the second clock signal SCK2 jumps from high to low, under the bootstrap effect of the second capacitor C2, the potential of the gate of the fourth transistor M4 (i.e., the second node N2) is pulled to be lower, the fourth transistor M4 continues to be turned on, and therefore the signal output by the output end OUT is the low signal VGL.

[0082] In the fifth stage t5, the start signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is low. The voltage stored by the first capacitor C1 (corresponding to the high signal VGH in the previous stage) makes the third transistor M3 remain in the turned-off state, the voltage stored by the second capacitor C2 (the low signal VGL in the previous stage) makes the fourth transistor M4 continue to be turned on, the low of the second clock signal SCK2 is transmitted to the output end OUT of the shift register 110, and the output end OUT outputs the low signal VGL. Since the second clock signal SCK2 jumps from high to low, under the bootstrap effect of the second capacitor C2, the potential of the gate of the fourth transistor M4 (i.e., the second node N2) is pulled to be lower, the fourth transistor M4 continues to be turned on, and therefore the signal output by the output end OUT is the low signal VGL.

[0083] In the sixth stage t6, the start signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. The voltage stored by the second capacitor C2 (the low-level signal VGL in the last stage) makes the fourth transistor M4 continue to be turned on, and the high level of the second clock signal SCK2 is transmitted to the output end OUT of the shift register 110, and the output end OUT outputs the high-level signal VGH. Therefore, the second transistor M2 and the third transistor M3 are turned on, and the output end OUT of the shift register 110 outputs the high-level signal VGH.

[0084] The seventh stage t7 has the same working process as the second stage t2, and the eighth stage t8 has the same working process as the first stage t1, which will not be described here.

[0085] The above eight working stages are repeated subsequently to output the second pulse signal of the scanning signal, and the specific working process will not be described here.

[0086] Through the above working stages, the signal output of the first shift register 110 is realized. It should be noted that, since there are multiple shift registers 110 in the gate driving circuit, the output signal of the last shift register 110 can be used as the input signal (shift signal) of the next shift register 110, so that the step-by-step shift transmission of the output signal can be realized, and the working process of the other shift registers 110 can be referred to the above related description, which will not be described here.

[0087] It should be noted that the structure of the shift register 110 in the above technical solution is only one optional structure provided in the embodiment, and other structures can also be included in other embodiments.

[0088] The embodiment of the present application also provides a driving method of a display panel, which is used for driving the display panel provided by any embodiment of the present application. The driving method comprises:

[0089] In a display frame, when the Nth shift register outputs the second pulse signal, the N+Xth shift register outputs the first pulse signal; wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

[0090] The driving method of the display panel provided by the embodiment of the present application is characterized in that, in a display frame, a second pulse signal of a scan signal output by an Nth shift register and a first pulse signal of a scan signal output by an N+Xth shift register are overlapped, where N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7, so that two adjacent rows of pixels are charged at the same time. Since the number of rows of pixels between the two rows of pixels overlapped by the scan signals is small, even if coupling occurs between the two pulse signals overlapped with each other, the dark lines caused by the inconsistency in brightness can be eliminated in the process of brightness superposition, thereby improving the display quality.

[0091] Optionally, the embodiment of the present application further provides a display device, which comprises the display panel provided by any of the embodiments of the present application, and therefore has the beneficial effects described in any of the embodiments. Figure 11 The display device provided by the embodiment of the present application is shown in a structural schematic diagram. Figure 11 The display device can be a mobile phone as shown in the figure, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., and the embodiment of the present application does not make special limitations on this.

[0092] It should be understood that the steps can be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, and the present application does not make limitations here.

[0093] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The gate driving circuit comprises a plurality of cascaded shift registers, each of which is connected with a corresponding gate line of the shift register of the current stage; The scan signal output by the shift register comprises a first pulse signal and a second pulse signal, and in a display frame, the second pulse signal of the scan signal output by the shift register of the Nth stage overlaps with the first pulse signal of the scan signal output by the shift register of the N+Xth stage; N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7; Each of the shift registers comprises an input end and an output end, the input end of the shift register of the first stage is connected with a trigger signal, the shift register is used for outputting a scan signal with a pulse width same as a period of the trigger signal from the output end according to the trigger signal, and transmitting a shift signal to the input end of the shift register of the next stage; The trigger signal is a double pulse signal; The shift register comprises a first input module, a second input module, a first output module and a second output module; The output end of the first input module is connected with the control end of the first output module, and the first input module is used for transmitting the input signal at the input end to the control end of the first output module in response to a first clock signal; The input end of the second input module is used as the trigger signal input end of the shift register, and is used for controlling the potential of the control end of the second output module; The output end of the first output module and the output end of the second output module are both connected with the output end of the shift register, the first output module is used for outputting a first level signal according to the potential of the control end, and the second output module is used for outputting a second level signal according to the potential of the control end; The output end of the second input module is connected with the control end of the second output module, the input end of the first output module is connected with a high level signal, and the input end of the second output module is connected with a second clock signal.

2. The display panel of claim 1, wherein, In a display frame, the second pulse signal of the scan signal output by the shift register of the Nth stage overlaps with the first pulse signal of the scan signal output by the shift register of the N+Xth stage.

3. The display panel of claim 1, wherein, X is equal to 2.

4. The display panel of claim 1, wherein, The pixel circuit comprises a data writing module, a compensation module, a driving module and a light emitting module, the driving module and the light emitting module are connected between a first power supply line and a second power supply line; The control end of the data writing module is connected with the gate line, the first end of the data writing module is connected with a data voltage, the second end of the data writing module is connected with the first end of the driving module, the compensation module is connected between the second end and the control end of the driving module, the data writing module is used for transmitting the data voltage to the first end of the driving module according to the first pulse signal of the scan signal output by the shift register, and resetting the first end of the driving module according to the second pulse signal of the scan signal output by the shift register; N is less than the number of rows of the pixel circuit.

5. The display panel of claim 1, wherein, The first input module comprises a first transistor, the second input module comprises a second transistor, the first output module comprises a third transistor and a first capacitor, and the second output module comprises a fourth transistor and a second capacitor; The gate of the first transistor is connected to the first clock signal, the first pole of the first transistor is used as the input end of the first input module, the second pole of the first transistor is connected to the gate of the third transistor, the first pole of the third transistor is connected to a first potential signal, the second pole of the third transistor is used as the output end of the first output module, and the first capacitor is connected between the first pole and the gate of the third transistor; The gate of the second transistor is connected to the first clock signal, the first pole of the second transistor is used as the input end of the second input module, the second pole of the second transistor is connected to the gate of the fourth transistor, the first pole of the fourth transistor is connected to a second clock signal, the second pole of the fourth transistor is connected to the second pole of the third transistor, and the second capacitor is connected between the gate and the second pole of the fourth transistor.

6. The display panel of claim 1, wherein, The shift register further comprises a first output control module and a second output control module, the output end of the first output control module is connected to the control end of the first output module, and the output end of the second output control module is connected to the control end of the second output module.

7. The display panel of claim 6, wherein, The first output control module comprises a fifth transistor, the gate of the fifth transistor is connected to the output end of the second input module, the first pole of the fifth transistor is connected to the first clock signal, and the second pole of the fifth transistor is used as the output end of the first output control module; The second output control module comprises a sixth transistor and a seventh transistor, the gate of the sixth transistor is connected to the control end of the first output module, the first pole of the sixth transistor is connected to a first potential signal, the second pole of the sixth transistor is connected to the first pole of the seventh transistor, the second pole of the seventh transistor is used as the output end of the second output control module, and the gate of the seventh transistor is connected to a second clock signal.

8. The display panel of claim 6, wherein, The shift register further comprises a protection module connected between the output end of the second input module and the control end of the second output module.

9. The display panel of claim 8, wherein, The protection module comprises an eighth transistor, the gate of the eighth transistor is connected to a second potential signal, the first pole of the eighth transistor is connected to the output end of the second input module, and the second pole of the eighth transistor is connected to the control end of the second output module.

10. A driving method of a display panel, characterized by, The display panel comprises a gate driving circuit, the gate driving circuit comprises a plurality of cascaded shift registers, each of the shift registers is connected with a gate line corresponding to the shift register; each of the shift registers comprises an input end and an output end, the input end of a first stage shift register is connected with a trigger signal, the first stage shift register is configured to output a scanning signal with a same pulse width as the trigger signal from the output end according to the trigger signal, and transmit a shift signal to the input end of a next stage shift register; wherein the scanning signal output by the shift register comprises a first pulse signal and a second pulse signal, and the trigger signal is a double pulse signal. The shift register comprises a first input module, a second input module, a first output module and a second output module. The output end of the first input module is connected with the control end of the first output module, and the first input module is configured to transmit an input signal at the input end to the control end of the first output module in response to a first clock signal. The input end of the second input module is configured as a trigger signal input end of the shift register, and is configured to control a potential at the control end of the second output module. The output end of the first output module and the output end of the second output module are both connected with an output end of the shift register, the first output module is configured to output a first level signal according to the potential at the control end, and the second output module is configured to output a second level signal according to the potential at the control end. The input end of the first output module is connected with a high level signal, and the input end of the second output module is connected with a second clock signal. The driving method of the display panel comprises: In a display frame, when the second pulse signal is output by the Nth stage shift register, the first pulse signal is output by the N+Xth stage shift register. Wherein, N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

11. A display device comprising: The display panel comprises a gate driving circuit, the gate driving circuit comprises a plurality of cascaded shift registers, each of the shift registers is connected with a gate line corresponding to the shift register; each of the shift registers comprises an input end and an output end, the input end of a first stage shift register is connected with a trigger signal, the first stage shift register is configured to output a scanning signal with a same pulse width as the trigger signal from the output end according to the trigger signal, and transmit a shift signal to the input end of a next stage shift register; wherein the scanning signal output by the shift register comprises a first pulse signal and a second pulse signal, and the trigger signal is a double pulse signal. The display panel comprises a gate driving circuit, the gate driving circuit comprises a plurality of cascaded shift registers, each of the shift registers is connected with a gate line corresponding to the shift register; each of the shift registers comprises an input end and an output end, the input end of a first stage shift register is connected with a trigger signal, the first stage shift register is configured to output a scanning signal with a same pulse width as the trigger signal from the output end according to the trigger signal, and transmit a shift signal to the input end of a next stage shift register; wherein the scanning signal output by the shift register comprises a first pulse signal and a second pulse signal, and the trigger signal is a double pulse signal.

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