Receiver circuit, memory device, and operating method using the same

Abstract

A receiver circuit includes a pair of preamplifier circuits and a postamplifier circuit. A first preamplifier circuit includes a pair of first n-type transistors, and gate terminals of the pair of first n-type transistors receive an input signal and a reference voltage signal, respectively. A second preamplifier circuit includes a pair of first p-type transistors, and gate terminals of the pair of first p-type transistors receive the input signal and the reference voltage signal, respectively. The postamplifier circuit outputs a postamplified signal based on first and second preamplified signals. A memory device including the receiver circuit and a method of operating the same are also described.

Description

Technical Field

[0001] This disclosure relates to a receiver circuit for a memory device, and more specifically, to a receiver circuit, a memory device, and an operation method thereon that can reduce power consumption and expand the operating range of a reference voltage. Background Technology

[0002] Memory is widely used to store data in a variety of electronic devices, including mobile devices, computers, autonomous vehicles, and electrical appliances. Memory includes input / output (I / O) circuitry for receiving and transmitting signals between the memory and other circuitry. I / O circuitry may include at least one receiver that operates according to a reference voltage.

[0003] Since receivers in different electronic devices operate within different reference voltage ranges, it is desirable for the receiver to operate over a wide reference voltage range. Furthermore, due to the recent increase in demand for low-power electronic devices, it is desirable for the receiver to have low power consumption. Summary of the Invention

[0004] This disclosure describes a receiver circuit, a memory device, and a method of operating thereof that can expand the operating range of the reference voltage and reduce power consumption.

[0005] In some embodiments, the receiver circuit includes a pair of preamplifier circuits and a postamplifier circuit. The pair of preamplifier circuits are configured to receive an input signal and a reference voltage signal, and output a first preamplified signal and a second preamplified signal based on the difference between the input signal and the reference voltage signal. The pair of preamplifier circuits includes a first preamplifier circuit and a second preamplifier circuit, wherein the first preamplifier circuit includes a pair of first n-type transistors, and the gate terminals of the pair of first n-type transistors respectively receive the input signal and the reference voltage signal. The second preamplifier circuit includes a pair of first p-type transistors, wherein the gate terminals of the pair of first p-type transistors respectively receive the input signal and the reference voltage signal. The postamplifier circuit is configured to receive the first preamplified signal and the second preamplified signal from the pair of preamplifier circuits, and output a postamplified signal based on the first preamplified signal and the second preamplified signal.

[0006] In some embodiments, the memory device includes a memory core circuit having a plurality of memory cells and a receiver circuit. The receiver circuit includes a pair of preamplifier circuits and a postamplifier circuit. The pair of preamplifier circuits are configured to receive an input signal and a reference voltage signal, and output a first preamplified signal and a second preamplified signal based on the difference between the input signal and the reference voltage signal. The pair of preamplifier circuits includes a first preamplifier circuit and a second preamplifier circuit, wherein the first preamplifier circuit includes a pair of first n-type transistors, and the gate terminals of the pair of first n-type transistors respectively receive the input signal and the reference voltage signal. The second preamplifier circuit includes a pair of first p-type transistors, wherein the gate terminals of the pair of first p-type transistors respectively receive the input signal and the reference voltage signal. The postamplifier circuit is configured to receive the first preamplified signal and the second preamplified signal from the pair of preamplifier circuits, and output a postamplified signal based on the first preamplified signal and the second preamplified signal.

[0007] In some embodiments, the method of operation includes the following steps: receiving an input signal and a reference voltage signal by a pair of preamplifier circuits; outputting a first preamplified signal and a second preamplified signal by the pair of preamplifier circuits based on the difference between the input signal and the reference voltage signal; receiving the first preamplified signal and the second preamplified signal from the pair of preamplifier circuits by a postamplifier circuit; and outputting a postamplified signal by the postamplifier circuit based on the first preamplified signal and the second preamplified signal. The pair of preamplifier circuits includes a first preamplifier circuit and a second preamplifier circuit. The first preamplifier circuit includes a pair of first n-type transistors, wherein the gate terminals of the pair of first n-type transistors respectively receive the input signal and the reference voltage signal. The second preamplifier circuit includes a pair of first p-type transistors, wherein the gate terminals of the pair of first p-type transistors respectively receive the input signal and the reference voltage signal.

[0008] According to embodiments of this disclosure, a first preamplifier circuit including a pair of p-type transistors for receiving input signals may be referred to as a p-type amplifier circuit; and a second preamplifier circuit including an n-type transistor for receiving input signals may be referred to as an n-type amplifier circuit. Since the p-type amplifier circuit operates effectively in a lower reference voltage range (also referred to as a first reference voltage range), and the n-type amplifier circuit operates effectively in a higher reference voltage range (also referred to as a first reference voltage range), the receiver circuit in this disclosure can operate effectively in a wider reference voltage range (i.e., both the higher and lower ranges). Furthermore, since one of the preamplifier circuits can be disabled during operation of the receiver circuit, the power consumption of the receiver circuit is reduced. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating a memory system according to some embodiments;

[0010] Figure 2 This is a schematic diagram illustrating a receiver circuit according to some embodiments;

[0011] Figure 3 Illustrations based on some embodiments Figure 2 The specific structure of the receiver circuit in the image;

[0012] Figure 4 This is a flowchart illustrating the operation method of a receiver circuit according to some embodiments.

[0013] Explanation of icon numbers

[0014] 100: Memory system;

[0015] 101, 102: Preamplifier circuit;

[0016] 103: Power amplifier circuit;

[0017] 110: Memory device;

[0018] 112: Memory core circuit;

[0019] 114: Input / output circuit;

[0020] 116: Voltage generator;

[0021] 120: Memory controller;

[0022] 401, 402, 403, 404: Frames;

[0023] 1011, 1011_1, 1011_2, 1021, 1021_1, 1021_2: Preamplifier signals;

[0024] 1121: Decoder circuit;

[0025] 1123: Memory array;

[0026] 1125: Read / write circuit;

[0027] 1141: Receiver circuit;

[0028] 1143: Calibration circuit;

[0029] EN1, EN2: Enable signals;

[0030] GND: Power supply voltage / Ground voltage;

[0031] IN: Input signal;

[0032] N11, N12, N21, N22, N31, N32: n-type transistors;

[0033] ND11, ND12, ND21, ND22: Connection nodes;

[0034] OUT: Output signal;

[0035] P11, P12, P21, P22, P31, P32: p-type transistors;

[0036] RD: Read data;

[0037] T1, T2: Enable switch;

[0038] VDD: Power supply voltage;

[0039] Vref: Reference voltage signal;

[0040] WD: Write data. Detailed Implementation

[0041] Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0042] Figure 1 A schematic diagram of a memory system 100 including a memory device 110 and a memory controller 120 according to some embodiments is shown. The memory device 110 may include memory core circuitry 112 and input / output (I / O) circuitry 114. The memory core circuitry 112 is configured to store data and perform memory operations such as read operations, program operations, and erase operations. The I / O circuitry 114 is configured to receive and transmit signals between the memory device 110 and the memory controller 120. In an embodiment, the memory device 110 is dynamic random-access memory (DRAM), but this disclosure is not limited thereto. Any other type of memory device 110 falls within the scope of this disclosure.

[0043] In one embodiment, the memory core circuitry 112 includes a decoder circuitry 1121, a memory array 1123, and a read / write circuitry 1125. The memory array 1123 includes a plurality of memory cells (not shown) for storing data, each of which is associated with a memory address. The decoder circuitry 1121 is coupled to the memory array and the I / O circuitry 114, configured to decode address signals received from the I / O circuitry 114 to select at least one memory cell for memory operation. The read / write circuitry 1125 is coupled to the memory array 1123 and the I / O circuitry 114, and configured to perform memory operations on the memory cells of the memory array 1123. In one example, the read / write circuitry 1125 may perform read operation data on read data RD from a selected memory cell in the memory array 1123, and output the read data RD to the memory controller 120. In another example, the read / write circuitry 1125 may perform a program operation on write data WD of a selected memory cell in the memory array 1123. The write data WD can be obtained from the memory controller 120 via the I / O circuitry 114.

[0044] In one embodiment, the IO circuit 114 includes a receiver circuit 1141 that receives an input signal IN and a reference voltage signal Vref. The receiver circuit 1141 is configured to amplify the difference between the reference voltage signal Vref and the input signal IN to generate an output signal OUT. The output signal OUT can be supplied to the memory core circuit 112 for decoding and memory operations. In one embodiment, the receiver circuit 1141 is a single-ended receiver circuit that receives only one input signal (i.e., the input signal IN) and operates according to the reference signal Vref to output the output signal OUT. For example, the receiver circuit 1141 is a command and address receiver circuit that receives an address / command (C / A signal) and is configured to amplify the difference between the reference voltage signal Vref and the C / A signal to generate the output signal OUT. The C / A signal may include at least one of an address signal and a command signal, wherein the address signal defines the memory address of the selected memory cell for operation, and the command signal defines the operation performed on the selected memory cell.

[0045] In some embodiments, the IO circuit 114 further includes a calibration circuit 1143 coupled to the receiver circuit 1141 and configured to calibrate a reference voltage signal Vref during a calibration mode of the receiver circuit 1141. During the calibration mode, the level of the reference voltage signal Vref varies incrementally or decrementally, and the output signal OUT of the receiver circuit 1141 is analyzed to determine the operable voltage range of the reference voltage signal Vref that allows the receiver circuit 1141 to operate correctly. In an example, a test mode (not shown) and each level of the reference voltage signal Vref are input to the receiver circuit 1141, and the output signal OUT of the receiver circuit 1141 is analyzed to determine whether the receiver circuit 1141 correctly receives the test mode at each level of the reference voltage signal Vref. In this way, the operable voltage range of the reference voltage signal Vref can be determined in the calibration mode of the receiver circuit 1141.

[0046] In an embodiment, the calibration mode of receiver circuit 1141 may be triggered by an activation signal (not shown). In an example, the calibration mode of receiver circuit 1141 is triggered whenever receiver circuit 1141 is powered on to calibrate the reference voltage signal Vref. It should be understood that this disclosure is not limited to the conditions under which the calibration mode of receiver circuit 1141 is triggered. Furthermore, the location of calibration circuit 1143 is not limited in this disclosure. For example, calibration circuit 1143 may be located inside receiver circuit 1141. Receiver circuit 1141 may include circuitry (not shown) designed to receive or transmit signals between memory device 110 and memory controller 120.

[0047] After the receiver circuit 1141 enters the calibration mode, the operable voltage range of the reference voltage signal Vref is determined. In an embodiment, the fixed level of the reference voltage signal Vref (i.e., the fixed reference voltage signal) is selected from the operable voltage range of the reference voltage signal Vref, such that the fixed reference voltage signal is used in the operating mode of the receiver circuit 1141. In an embodiment, the fixed reference voltage signal is an intermediate voltage within the operable voltage range of the reference voltage signal Vref, but this disclosure is not limited to any particular way of selecting the fixed reference voltage for the operating mode.

[0048] In this embodiment, at least one of the operable voltage ranges of the reference voltage Vref and the fixed reference voltage signal Vref is stored in a register or non-volatile memory contained in the memory device 110. The fixed reference voltage signal Vref may be stored in a memory cell of the memory core circuitry 112 or in any other register or memory of the memory device 110. The fixed reference voltage signal Vref is used during the operation mode of the receiver circuitry 1141.

[0049] In some embodiments, the memory device 110 further includes a voltage generator 116 configured to generate a voltage for operation of the memory device 110. The voltage generator 116 can generate a reference voltage signal Vref and provide the generated reference voltage signal Vref to a receiver circuit 1141 in the I / O circuit 114. In some embodiments, the voltage generator 116 generates a reference voltage signal Vref with a varying level in a calibration mode of the receiver circuit 1141. The level of the reference voltage signal Vref can vary incrementally or decrementally. In an operating mode, the voltage generator 116 is configured to generate a fixed reference voltage signal Vref and supply it to the receiver circuit 1141.

[0050] Figure 2 A schematic diagram of a receiver circuit 1141, comprising a pair of preamplifier circuits 101 and 102, and a postamplifier circuit 103, is shown according to some embodiments. Preamplifier circuit 101 receives an input signal IN and a reference voltage signal Vref, and outputs a preamplified signal 1011 based on the difference between the input signal IN and the reference voltage signal Vref. Similarly, preamplifier circuit 102 receives an input signal IN and a reference voltage signal Vref, and outputs a preamplified signal 1021 based on the difference between the input signal IN and the reference voltage signal Vref. In embodiments, preamplifier circuits 101 and 102 are differential amplifiers of different types. In an example, preamplifier circuit 101 is a p-type differential amplifier, and preamplifier circuit 102 is an n-type differential amplifier. Preamplifier circuits 101 and 102 are configured to amplify the difference between the input signal IN and the reference voltage signal Vref to generate preamplified signals 1011 and 1021, respectively.

[0051] The post-amplifier circuit 103 is coupled to the pre-amplifier circuits 101 and 102 to receive pre-amplified signals 1011 and 1021 from the pre-amplifier circuits 101 and 102. The post-amplifier circuit 103 is configured to generate an output signal OUT (also referred to as a post-amplified signal) based on the pre-amplified signals 1011 and 1021. The output signal OUT can be further supplied to the memory core circuitry 112 for further processing.

[0052] Figure 3The diagram illustrates the specific structure of a receiver circuit 1141 comprising preamplifier circuits 101 and 102, and a postamplifier circuit 103, according to some embodiments. The preamplifier circuit 101 includes a pair of p-type transistors P11 and P12, wherein the source terminals of p-type transistors P11 and P12 are coupled to a reference node receiving the power supply voltage VDD, and the gate terminals of p-type transistors P11 and P12 are coupled to their drain terminals. In other words, p-type transistors P11 and P12 are designed as diodes in the preamplifier circuit 101. The preamplifier circuit 101 further includes a pair of n-type transistors N11 and N12, wherein the drain terminals of n-type transistors N11 and N12 are coupled to the drain terminals of p-type transistors P11 and P12 via connection nodes ND11 and ND12. The gate terminals of n-type transistors N11 and N12 receive the input signal IN and the reference voltage signal Vref, respectively.

[0053] The preamplifier circuit 101 receives the input signal IN and the reference voltage signal Vref through the gate terminals of n-type transistors N11 and N12. The preamplifier circuit 101 is configured to amplify the difference between the input signal IN and the reference voltage signal Vref to generate preamplified signals 1011_1 and 1011_2 through connection nodes ND11 and ND12, respectively. Preamplified signals 1011_1 and 1011_2 can be considered as differential output signals of the preamplifier circuit 101. The preamplifier circuit 101 outputs preamplified signals 1011_1 and 1011_2 to the subsequent amplifier circuit 103 through connection nodes ND11 and ND12.

[0054] The preamplifier circuit 102 may include a pair of n-type transistors N21 and N22, wherein the source terminals of n-type transistors N21 and N22 are coupled to a reference node receiving the power supply voltage GND, and the gate terminals of n-type transistors N21 and N22 are coupled to their respective drain terminals. In other words, n-type transistors N21 and N22 are designed as diodes in the preamplifier circuit 102. The preamplifier circuit 102 further includes a pair of p-type transistors P21 and P22, wherein the drain terminals of p-type transistors P21 and P22 are coupled to the drain terminals of n-type transistors N21 and N22 through connection nodes ND21 and ND22. The gate terminals of p-type transistors P21 and P22 receive the input signal IN and the reference voltage signal Vref, respectively.

[0055] The preamplifier circuit 102 receives the input signal IN and the reference voltage signal Vref through the gate terminals of p-type transistors P21 and P22. The preamplifier circuit 102 is configured to amplify the difference between the input signal IN and the reference voltage signal Vref to generate preamplified signals 1021_1 and 1021_2 respectively through connection nodes ND21 and ND22. Preamplified signals 1021_1 and 1021_2 can be considered as differential output signals of the preamplifier circuit 102. The preamplifier circuit 102 outputs preamplified signals 1021_1 and 1021_2 to the subsequent amplifier circuit 103 through connection nodes ND21 and ND22.

[0056] In the above embodiments, the preamplifier circuit 101, which includes a pair of n-type transistors N11 and N12 for receiving the input signal IN and the reference voltage signal Vref, can be referred to as an n-type amplifier circuit; and the preamplifier circuit 102, which includes a pair of p-type transistors P21 and P22 for receiving the input signal IN and the reference voltage signal Vref, can be referred to as a p-type amplifier circuit. When the reference voltage signal Vref is in a first reference voltage range (i.e., a higher voltage range or high voltage range), the n-type amplifier circuit operates well, while the p-type amplifier circuit may lose gain. Conversely, when the reference voltage signal Vref is in a second reference voltage range (i.e., a lower voltage range), the p-type amplifier circuit operates well, while the n-type amplifier circuit may lose gain. In the embodiments of this disclosure, the receiver circuit 1141 includes both an n-type amplifier circuit (i.e., the preamplifier circuit 101) and a p-type amplifier circuit (i.e., the preamplifier circuit 102), and the receiver circuit 1141 operates well in both the higher and lower reference voltage signal Vref voltage ranges. In other words, receiver circuit 1141 can operate well over a wide range of reference voltage signal Vref without losing the gain performance of receiver circuit 1141.

[0057] In some embodiments, preamplifier circuits 101 and 102 further include enable switches T1 and T2 configured to enable or disable preamplifier circuits 101 and 102. Specifically, preamplifier circuit 101 includes enable switch T1 configured to enable or disable preamplifier circuit 101 according to enable signal EN1. Preamplifier circuit 102 includes enable switch T2 configured to enable or disable preamplifier circuit 102 according to enable signal EN2. In an embodiment, one of preamplifier circuits 101 and 102 can be disabled during the operation mode of receiver circuit 1141 to save power consumption.

[0058] In this embodiment, one of the n-type amplifier circuit (i.e., preamplifier circuit 101) and the p-type amplifier circuit (i.e., preamplifier circuit 102) can be disabled to save power consumption of receiver circuit 1141 without degrading its performance. For example, when the reference voltage signal Vref is relatively high (i.e., in a higher voltage range), the p-type amplifier circuit, which performs poorly at high reference voltage signals Vref, can be disabled to save power consumption. Similarly, when the reference voltage signal Vref is relatively low (i.e., in a low voltage range), the n-type amplifier circuit, which performs poorly at low reference voltage signals Vref, can be disabled to save power consumption. In this way, the power consumption of receiver circuit 1141 is reduced without degrading its performance.

[0059] In some embodiments, the post-amplifier circuit 103 includes p-type transistors P31 and P32, and n-type transistors N31 and N32, wherein p-type transistors P31 and P32 are coupled to the pre-amplifier circuit 101, and n-type transistors N31 and N32 are coupled to the pre-amplifier circuit 102. Specifically, the gate terminals of p-type transistors P31 and P32 are coupled to connection nodes ND11 and ND12 of the pre-amplifier circuit 101 to receive pre-amplified signals 1011_1 and 1011_2 from connection nodes ND11 and ND12. The gate terminals of n-type transistors N31 and N32 are coupled to connection nodes ND21 and ND22 of the pre-amplifier circuit 102 to receive pre-amplified signals 1021_1 and 1021_2 from connection nodes ND21 and ND22.

[0060] In this embodiment, p-type transistor P31 and its source terminal receive the power supply voltage VDD. The drain terminal of p-type transistor P31 is coupled to the gate terminal of n-type transistor N32, and the drain terminal of p-type transistor P32 is coupled to the drain terminal of n-type transistor N32. Furthermore, n-type transistors N31 and N32 receive the ground voltage GND. The drain terminal of n-type transistor N31 is coupled to the gate terminal of transistor P32, and the drain terminal of n-type transistor N32 is coupled to the drain terminal of p-type transistor P32.

[0061] In this embodiment, the post-amplifier circuit 103 is configured to combine the pre-amplifier signals 1011_1 and 1011_2, and the pre-amplifier signals 1021_1 and 1021_2, to generate an output signal OUT. The output signal OUT, also referred to as the post-amplified signal, is an amplified signal of the difference between the input signal IN and the reference voltage signal Vref. The receiver circuit 1141 amplifies the difference between the input signal IN and the reference voltage signal Vref by a gain, wherein the gain is determined based on the n-type and p-type transistors included in the pre-amplifier circuits 101 and 102, and the post-amplifier circuit 103. In this embodiment, the gain is determined based on the sizes of p-type transistors P31, P32, P11, and P12, and the sizes of n-type transistors N31, N32, N21, and N22. The transistor sizes may be referenced to the transistor width, the transistor length, or the ratio of the transistor's length to its width.

[0062] In this embodiment, p-type transistors P31 and P32 are identical in size and are collectively referred to as transistor pm2; p-type transistors P11 and P12 are identical in size and are collectively referred to as transistor pm1; n-type transistors N31 and N32 are identical in size and are collectively referred to as transistor nm2; and n-type transistors N21 and N22 are identical in size and are collectively referred to as transistor nm1. In this embodiment, the gain depends on the ratio of the size of transistor pm2 to the size of transistor pm1. The gain also depends on the ratio of the size of transistor nm2 to the size of transistor nm1.

[0063] Figure 4This is a flowchart illustrating the operation of a receiver circuit according to some embodiments. Receiver circuit 1141 includes a pair of preamplifier circuits and a postamplifier circuit. In block 401, the pair of preamplifier circuits receive an input signal and a reference voltage signal. In block 402, the pair of preamplifier circuits output a first preamplified signal and a second preamplified signal based on the difference between the input signal and the reference voltage signal. In block 403, the postamplifier circuit receives the first preamplified signal and the second preamplified signal from the pair of preamplifier circuits. In block 404, the postamplifier circuit outputs a postamplified signal based on the first preamplified signal and the second preamplified signal. The pair of preamplifier circuits includes: a first preamplifier circuit including a pair of first n-type transistors, wherein the gate terminals of the pair of first n-type transistors respectively receive the input signal and the reference voltage signal; and a second preamplifier circuit including a pair of first p-type transistors, wherein the gate terminals of the pair of first p-type transistors respectively receive the input signal and the reference voltage signal.

[0064] In summary, receiver circuit 1141 includes both an n-type amplifier circuit and a p-type amplifier circuit, wherein the n-type amplifier circuit operates well over the higher voltage range of the reference voltage, and the p-type amplifier circuit operates well over the lower voltage range of the reference voltage. In this way, receiver circuit 1141 can operate well over a wide range of the reference voltage signal Vref. Furthermore, receiver circuit 1141 can be disabled based on the level of the reference voltage signal Vref, either the n-type amplifier circuit or the p-type amplifier circuit, thereby reducing the power consumption of receiver circuit 1141.

[0065] Although embodiments of the present disclosure have been described in detail, the present disclosure is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present disclosure as disclosed in the claims.

Claims

1. A receiver circuit, comprising: A pair of preamplifier circuits receive an input signal and a reference voltage signal, and output a first preamplifier signal through a first connection node and a second connection node, and output a second preamplifier signal through a third connection node and a fourth connection node, based on the difference between the input signal and the reference voltage signal. The power amplifier circuit receives the first preamplified signal and the second preamplified signal from the pair of preamplifier circuits through the first connection node, the second connection node, the third connection node, and the fourth connection node, and outputs the power amplifier signal based on the first preamplified signal and the second preamplified signal. The pair of preamplifier circuits mentioned above include: A first preamplifier circuit, comprising: A first p-type transistor, wherein the gate terminal of the first p-type transistor is coupled to the drain terminal of the first p-type transistor, and the drain terminal of the first p-type transistor is coupled to the first connection node; and The second p-type transistor, wherein the gate terminal of the second p-type transistor is coupled to the drain terminal of the second p-type transistor, and the drain terminal of the second p-type transistor is coupled to the second connection node. The pair of preamplifier circuits includes a second preamplifier circuit, the second preamplifier circuit further comprising: A third p-type transistor, wherein the gate terminal of the third p-type transistor receives the input signal, and the drain terminal of the third p-type transistor is coupled to the third connection node; A fourth p-type transistor, wherein the gate terminal of the fourth p-type transistor receives the reference voltage signal, and the drain terminal of the second p-type transistor is coupled to the fourth connection node; A first n-type transistor, wherein the gate terminal of the first n-type transistor is coupled to the drain terminal of the first n-type transistor, and the drain terminal of the first n-type transistor is coupled to the third connection node; A second n-type transistor, wherein the gate terminal of the second n-type transistor is coupled to the drain terminal of the second n-type transistor, and the drain terminal of the second n-type transistor is coupled to the fourth connection node; and A first enable switch is connected between the first power supply terminal and the source terminals of the third and fourth p-type transistors, and is configured to enable the second preamplifier circuit according to a first enable signal. When the reference voltage signal is within the first reference voltage range, the first enable switch is configured to disable the second preamplifier circuit by stopping power supply to the second preamplifier circuit.

2. The receiver circuit according to claim 1, wherein the first preamplifier circuit further comprises: A third n-type transistor, wherein the gate terminal of the third n-type transistor receives the input signal, and the drain terminal of the third n-type transistor is coupled to the first connection node; as well as A fourth n-type transistor, wherein the gate terminal of the fourth n-type transistor receives the reference voltage signal, and the drain terminal of the fourth n-type transistor is coupled to the second connection node.

3. The receiver circuit according to claim 2, wherein the first preamplifier circuit further comprises: A second enable switch, coupled between the second power supply terminal and the source terminals of the third and fourth n-type transistors, is configured to enable the first preamplifier circuit according to a second enable signal. When the reference voltage signal is within the second reference voltage range, the second enable switch is configured to disable the first preamplifier circuit by stopping the supply of power to the first preamplifier circuit.

4. The receiver circuit according to claim 1, wherein the subsequent amplifier circuit comprises: A pair of p-type transistors, wherein the gate terminals of the pair of p-type transistors are coupled to the first preamplifier circuit to receive the first preamplifier signal from the first preamplifier circuit; A pair of n-type transistors, wherein the gate terminals of the pair of n-type transistors are coupled to the second preamplifier circuit to receive the second preamplifier signal from the second preamplifier circuit.

5. A memory device, comprising: The core circuitry of the memory contains multiple memory cells; as well as A receiver circuit, coupled to the memory core circuit, generates a post-amplified signal to control the plurality of memory cells in the memory core circuit. The receiver circuit includes: A pair of preamplifier circuits receive an input signal and a reference voltage signal, and output a first preamplifier signal through a first connection node and a second connection node based on the difference between the input signal and the reference voltage signal, and output a second preamplifier signal through a third connection node and a fourth connection node. The power amplifier circuit receives the first preamplified signal and the second preamplified signal from the pair of preamplifier circuits through the first connection node, the second connection node, the third connection node, and the fourth connection node, and outputs the power amplifier signal based on the first preamplified signal and the second preamplified signal. The pair of preamplifier circuits mentioned above include: A first preamplifier circuit includes a pair of first n-type transistors, wherein the gate terminals of the pair of first n-type transistors respectively receive the input signal and the reference voltage signal; and The second preamplifier circuit includes a pair of first p-type transistors, wherein the gate terminals of the pair of first p-type transistors receive the input signal and the reference voltage signal, respectively. The first preamplifier circuit further includes a pair of second p-type transistors, the pair of second p-type transistors being coupled to the pair of first n-type transistors through the first connection node, wherein the pair of second p-type transistors includes: A first p-type transistor, wherein the gate terminal of the first p-type transistor is coupled to the drain terminal of the first p-type transistor, and the drain terminal of the first p-type transistor is coupled to the first connection node; and The second p-type transistor, wherein the gate terminal of the second p-type transistor is coupled to the drain terminal of the second p-type transistor, and the drain terminal of the second p-type transistor is coupled to the second connection node. The second preamplifier circuit further includes: A pair of second n-type transistors coupled to the pair of first p-type transistors via a second connection node, each of the pair of second n-type transistors including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a first reference node, and the drain terminal is coupled to the gate terminal; and A first enable switch is connected between the power supply terminal and the source terminal of the third p-type transistor and the source terminal of the fourth p-type transistor in the pair of first p-type transistors, and is configured to enable the second preamplifier circuit according to a first enable signal. When the reference voltage signal is within the first reference voltage range, the first enable switch is configured to disable the second preamplifier circuit by stopping power supply to the second preamplifier circuit.

6. The memory device according to claim 5, wherein The source terminal of each of the pair of second p-type transistors is coupled to the second reference node.

7. The memory device of claim 5, wherein the post-amplifier circuit comprises: A pair of third p-type transistors, wherein the gate terminals of the pair of third p-type transistors are coupled to the first preamplifier circuit to receive the first preamplifier signal from the first preamplifier circuit; A pair of third n-type transistors, wherein the gate terminals of the pair of third n-type transistors are coupled to the second preamplifier circuit to receive the second preamplifier signal from the second preamplifier circuit.

8. The memory device according to claim 5, further comprising: A voltage generator that generates a voltage for the memory device; A calibration circuit, coupled to the receiver circuit, calibrates the reference voltage signal during the calibration mode of the receiver circuit to determine the reference voltage signal for the operating mode of the receiver circuit. During the calibration mode, the calibration circuit determines an operable voltage range of a reference voltage that allows the receiver circuit to operate correctly, and the calibration circuit determines the reference voltage signal for the operating mode based on the operable voltage range of the reference voltage. During the operating mode of the receiver circuit, the calibration circuit controls the voltage generator to generate the reference voltage signal for the operating mode.

9. The memory device according to claim 5, wherein When the reference voltage signal is in a second reference voltage range that is different from the first reference voltage range, the first preamplifier circuit is disabled.

10. A method of operating a receiver circuit, the method comprising: The input signal and reference voltage signal are received by a pair of preamplifier circuits; The pair of preamplifier circuits output a first preamplifier signal through a first connection node and a second connection node respectively, based on the difference between the input signal and the reference voltage signal, and output a second preamplifier signal through a third connection node and a fourth connection node respectively; The post-amplifier circuit receives the first pre-amplifier signal and the second pre-amplifier signal from the pair of pre-amplifier circuits through the first connecting section, the second connecting node, the third connecting node, and the fourth connecting node, respectively. as well as The post-amplifier circuit outputs a post-amplified signal based on the first pre-amplified signal and the second pre-amplified signal. The pair of preamplifier circuits includes a first preamplifier circuit, which includes: A first p-type transistor, wherein the gate terminal of the first p-type transistor is coupled to the drain terminal of the first p-type transistor, and the drain terminal of the first p-type transistor is coupled to the first connection node; as well as The second p-type transistor, wherein the gate terminal of the second p-type transistor is coupled to the drain terminal of the second p-type transistor, and the drain terminal of the second p-type transistor is coupled to the second connection node.

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