Apparatus comprising an internal testing mechanism and associated methods

Abstract

This application relates to apparatuses including internal testing mechanisms and associated methods. The apparatuses can include a self-test circuit configured to implement at least a portion of a self-test process that determines operating conditions of the apparatuses. The test verification circuit can be configured to generate a flag based on comparing (1) an input stream or a portion thereof associated with the self-test and (2) test data associated with the self-test. The flag can represent a validity associated with implementation of the self-test process or a portion thereof.

Description

Technical Field

[0001] The present invention relates to devices, such as semiconductor devices including memory and processor, and several embodiments relate to semiconductor devices including internal testing mechanisms. Background Technology

[0002] A device (e.g., a processor, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and / or process information. For example, the device may include a memory device, such as a volatile memory device, a non-volatile memory device, or a combination thereof. Memory devices, such as dynamic random access memory (DRAM) and / or high-bandwidth memory (HBM), can utilize electrical energy to store and access data.

[0003] With advancements in embedded systems technology and their increasing applications, the market continuously seeks faster, more efficient, and smaller devices. To meet these market demands, semiconductor devices are pushed to their limits through various improvements. Generally, device improvements may include increasing circuit density, increasing operating speed or otherwise reducing operating latency, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. However, attempts to meet market demands, such as by reducing the overall device footprint, often present challenges in other areas, such as maintaining circuit robustness and / or fault detectability. Summary of the Invention

[0004] In one aspect, this application provides an apparatus comprising: a self-test circuit configured to perform a self-test process or a portion thereof to determine operating conditions of the apparatus, wherein the self-test process includes (1) receiving an input stream from an external device and (2) storing test data at a predetermined location; an external connector coupled to the self-test circuit and configured to provide an interface between the apparatus and the external device; and a test verification circuit coupled to the self-test circuit and the external connector, the test verification circuit being configured to generate a flag based on comparing the input stream or a portion thereof with content stored at the predetermined location, wherein the flag indicates validity associated with the implementation of the self-test process or a portion thereof.

[0005] In another aspect, this application provides a method of operating a device, the method comprising: receiving an input stream from an external device, wherein the input stream is used to implement a self-test process that interacts with the external device and verifies the operating conditions of the device; accessing a set of registers corresponding to test data associated with the self-test process; and generating a status flag based on an internal comparison of the contents of the set of registers with the input stream, wherein the status flag indicates the validity associated with the implementation of the self-test process or a portion thereof. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of a system-in-package device according to an embodiment of the present technology.

[0007] Figure 2 This is a block diagram of a memory device according to an embodiment of the present technology.

[0008] Figure 3 This is a schematic diagram of a first example test verification circuit according to an embodiment of the present technology.

[0009] Figure 4 This is a schematic diagram of a second example test verification circuit according to an embodiment of the present technology.

[0010] Figure 5 This is a flowchart illustrating an example method of operating a device according to an embodiment of the present invention.

[0011] Figure 6 This is a flowchart illustrating an example method of manufacturing equipment according to an embodiment of the present invention.

[0012] Figure 7 This is a block diagram of a system comprising a device configured according to an embodiment of the present invention. Detailed Implementation

[0013] As described in more detail below, the techniques disclosed herein relate to devices, systems having memory devices, and related methods for facilitating self-testing, such as those for memory systems. Devices (e.g., memory devices, such as HBM and / or RAM, and / or corresponding systems) may include internal mechanisms (e.g., internal test analyzers) configured to verify and / or latch test data. The internal mechanisms can verify test data to provide a higher-level overview of the transmitted test data, thereby reducing the total amount of data exchanged with external devices (e.g., external testers) for testing. For example, upon detecting a specific test result, the internal mechanisms may also selectively latch one or more portions of the test data, thereby improving the timing and efficiency associated with external communication.

[0014] Conventional devices (e.g., conventional HBM devices) are typically configured to perform self-tests, for example, through a built-in self-test (BIST) circuitry / function. An external tester interacts with the BIST circuitry to perform the test and reads the test result messages back to the external tester for analysis. For example, some HBM devices send values ​​stored in the BIST status register and / or other relevant registers (e.g., a multi-input shift register (MISR)) at the end of the test. Typically, when a fault is detected by the test, the transmitted data (e.g., data from the BIST register and / or MISR signature) is highly likely to deviate from the expected values. This conventional design limits the minimum duration of each test based on the overhead required for readback, thus limiting the minimum test time capability. In other words, the tester's limited memory requires overhead associated with additional / segmented communication and comparisons. Given the size of the test results (e.g., 1564 bits and 968 bits per channel), communication and off-memory comparisons can take a significant amount of time (e.g., 40 to 50 ms per test). When extrapolating to critical parts of the device (e.g., each chip), the resulting overhead time can range from tens of minutes to over an hour.

[0015] Conversely, embodiments of the device according to the invention may include internal mechanisms for analyzing test results within the device and providing a higher-level overview of the test results to external test equipment. In some embodiments, the internal mechanisms may include a set of registers and comparison circuitry (e.g., XOR gates) to hold expected data and compare it with final test data. The internal mechanisms may further include two or more comparison circuits, each configured to analyze a corresponding aspect of the test results (e.g., a specific data pattern).

[0016] Instance Environment

[0017] Figure 1 This is a schematic cross-sectional view illustrating a system-in-package (SiP) device 100 (i.e., an example device) according to an embodiment of the present technology. SiP 100 may include a memory device 102 and a processor 110, which are packaged together with an inserter 112 on a package substrate 114. The processor 110 may act as the host device of SiP 100.

[0018] In some embodiments, the memory device 102 may be an HBM device, which includes an interface die (or logic die) 104 and one or more memory core dies 106 stacked on the interface die 104. The memory device 102 may include one or more through-silicon vias (TSVs) 108, which can be used to couple the interface die 104 and the core die 106.

[0019] Insertor 112 provides electrical connectivity between processor 110, memory device 102, and / or package substrate 114. For example, both processor 110 and memory device 102 can be coupled to insertor 112 via multiple internal connectors (e.g., microbumps 111). Insertor 112 may include channels 105 (e.g., interfaces or connection circuitry) electrically coupled to processor 110 and memory device 102 via corresponding microbumps 111. Although... Figure 1 Only three channels 105 are shown, but more or fewer channels 105 can be used. The inserter 112 can be coupled to the package substrate via one or more additional connections (e.g., intermediate bump 113, such as C4 bump).

[0020] The package substrate 114 provides an external interface for the SiP 100. The package substrate 114 may include external bumps 115, some of which may be coupled to the processor 110, the memory device 102, or both. The package substrate may further include direct access (DA) bumps coupled to the interface die 104 through the package substrate 114 and the inserter 112.

[0021] In some embodiments, direct access bumps 116 (e.g., one or more of bumps 115) and / or other bumps may be incorporated into a probe pad (e.g., a set of test connectors). For example, an external device 150 of the tester may be coupled to the probe pad to communicate directly with the memory device 102. In other words, after the memory device 102 is mounted on the inserter 112, the external device 150 can send signals to and / or receive signals from the memory device 102 without passing through the processor 110. The external device 150 can be used to test the memory device before the memory device 102 is mounted on the inserter 112 and / or coupled to the processor 110.

[0022] An external tester can act as a host device for testing, interacting with the built-in self-test (BIST) circuitry of the memory device 102 to perform the tests. The tester can load one or more test modes into the test mode memory (e.g., a predetermined register) of the interface die 104. The tester can then provide one or more test instructions along direct access terminals 116. The interface die 104 can perform one or more tests on the memory device 102 based on the test instructions and the loaded test modes, and can generate result information. Test results can be monitored during testing to determine when a failure occurred or to read a pass / fail conclusion at the end of the test.

[0023] The test modes and instructions may correspond to one or more tests performed on the memory device 102. Tests may involve loading a data pattern into one or more memory cells of the memory device 102 as part of a write operation; retrieving stored information from a memory cell as part of a read operation; and comparing the written data with the read data. Tests can be performed using the BIST circuitry of the memory device 102. Tests can be performed using extremely long test modes with random characteristics, which may require more storage space than the actual storage space in the BIST circuitry. Such tests can be performed by sending the test mode and instructions directly via the DA terminal 116.

[0024] Example circuit system

[0025] Figure 2 The memory device 200 (i.e., instance device, for example) according to embodiments of the present technology is an example of this technology. Figure 1 A block diagram of a memory device 202 or a portion thereof. The memory device 200 may include an interface die 204 and one or more core dies 206. For clarity, Figure 2 Only a single core die 206 is shown in the image, but it should be understood that multiple core dies 206 may be coupled to the interface die 204 (e.g., there may be 2, 7 or other numbers of core dies 206).

[0026] The memory device 200 may include different interface terminals for accessing one or more circuits for the core die 206 and / or the memory. In some embodiments, the different interface terminals may include a local microbump (uBump) 205, a DA uBump 216, and / or a test interface uBump 220. The test interface uBump 220 may be part of a specific interface protocol, such as an IEEE 1500 interface (also referred to as a P1500 interface). In some embodiments, the local uBump 205 may be included in... Figure 1 In uBump111. Local uBump 205 can be accessed via one or more connections (e.g., Figure 1 Channel 105) is coupled to the processor (e.g., Figure 1 The processor 110. The local uBump 205 and its connections enable the processor to access information in the core die 206 (via, for example, read or write operations and corresponding information exchange). For example, the core die 206 can receive commands (e.g., read commands) and address information (AWORD) specifying the location of memory access, such as row address, column address, bank address, die identifier, etc. The AWORD may also contain command information, such as clock signals for operation timing and command identifiers. Accessed information (DWORDs), such as writing or reading data, can also be exchanged via the local uBump 205.

[0027] In some embodiments, interface die 204 may include a serializer 233 configured to process DWORDs between core die 206 and local uBump 205. For example, serializer 233 may receive information in parallel along a first number of data lines (e.g., from core 206) and subsequently provide the information serially along a second number of data lines (e.g., to local uBump 205). Serializer 233 may be used to multiplex multiple outputs (e.g., from core 206) to a smaller number of data lines (e.g., to local uBump 205).

[0028] In addition to the operational configuration associated with the local uBump 205 (e.g., local operation mode), the memory device 200 can be configured to operate in a test mode (e.g., BIST mode or other self-test modes). In test mode, the memory device 200 can determine one or more characteristics of the memory device 200 (e.g., aspects related to signal response, manufacturing defects, faults or errors, or other aspects of the circuitry). The memory device 200 can utilize the P1500 uBump 220 and / or DAuBump 216 as test interfaces. For example, the P1500 uBump 220 can be used to transmit signals to a host device according to a predetermined sequence or protocol for sending and receiving signals.

[0029] The memory device 200 may use a BIST sequencer 228 to process signals transmitted via the P1500 uBump 220 and / or DAuBump 216. The BIST sequencer 228 may be coupled to test interface circuitry 224 (e.g., P1500 circuitry), which is configured to interpret signals according to the P1500 protocol. For example, the P1500 circuitry 224 may convert signals received at the P1500 uBump into signals usable by other circuitry of the memory device 200, and vice versa.

[0030] During test mode (e.g., BIST operation mode), instructions can be received (from, for example...) Figure 1An external device 150 is used to operate the BIST sequencer 228 to perform tests on the memory device 200. The BIST sequencer 228 can generate test sequences (e.g., logical bit strings) to write to memory cells in the core die 206. The BIST sequencer 228 may include multiple registers that can be used to store the addresses of the memory cells to be tested and the test sequences. In some embodiments, the test sequences and / or addresses can be generated within the BIST sequencer 228 based on instructions. For example, the BIST sequencer 228 can perform a test on a specific address value, increment the address value by one, and then perform the test again. In some embodiments, to save space in the BIST sequencer 228, the BIST sequencer 228 can load the test sequences into a lookup table, such as a data topology (DTOPO) circuit 230. Each entry in the DTOPO circuit 230 can be associated with a pointer value (e.g., an index value), and the BIST sequencer 228 can generate a series of pointer values ​​in an address-like manner.

[0031] During the write portion of the test, the BIST sequencer 228 may provide address information (e.g., one or more row and column addresses) and a test sequence (e.g., data to be written to the memory cell specified by the address information) to the input buffer 234 (e.g., a register, such as a write FIFO (WFIFO)). In some embodiments, the BIST sequencer 228 may provide address information to the input buffer 234 and may provide index information to the DTOPO circuitry 230, which may provide the test sequence to the input buffer 234. Based on the address information provided from the WFIFO 234, the test sequence may be written to the memory cell specified by the address information.

[0032] During the read portion of the test, the BIST sequencer 228 can provide address information to retrieve the test sequence previously stored in the core die 206. Information can be read from the memory cell specified by the address information to the output buffer 235 (e.g., read FIFO (RFIFO)). The output buffer circuitry 235 can be generally similar to the input buffer 234, except that the output buffer 235 can receive information from the core die 206 and subsequently provide the information to other circuitry on the interface die 204.

[0033] Interface die 204 may include error capture memory (ECM) circuitry 232, configured to generate error-related results based on a read test sequence. ECM circuitry 232 may be coupled to address information and test sequences provided to input buffer 234, and includes one or more registers (e.g., BIST register and / or MISR output register) for storing write test sequences and address information. When a read operation is performed, ECM circuitry 232 compares the read test sequence from output buffer 235 with test sequences written to those memory cells as part of an earlier write operation. Based on this comparison, ECM circuitry 232 may generate results (e.g., indications of mismatches, faulty memory cells, etc.). ECM circuitry 232 may then provide the result information to P1500 circuitry 224, which may then provide the result information from memory via P1500 uBump 220 and / or DA uBump 216.

[0034] In addition to or replacing the P1500 uBump 220, the memory device 200 can be connected via the DA uBump 216 (e.g., Figure 1 The DA bumps 216 provide access to the core die 206. The memory device 200 can be configured to provide direct access to, for example, by passing through the DA bumps 216, bypassing other components of the SiP (e.g., processor 110). In some embodiments, these DA uBumps 216 can be organized into a probe pad, wherein an external device (e.g., external device 150) can be coupled to the DA uBumps 216 to access the interface die 204 (and through it, the core die 206). For example, the memory device 200 can communicate directly with an external tester via the DA uBumps 216 to perform tests. Signals can be transmitted according to the P1500 interface protocol. Therefore, the DA uBumps 216 can be used to perform the self-test described above for the P1500 uBump 220, for example by loading information to / from test circuitry (e.g., DTOPO circuitry 230 and / or ECM circuitry 232) via the DA uBumps 216. Test information can be transmitted between the DA uBump 216 and the P1500 circuit 224, and then transmitted to / from other circuits, as described above.

[0035] As an illustrative example, a test sequence can be loaded into a self-test circuit (e.g., BIST sequencer 228, DTOPO circuit 230, ECM 232, and / or) via the DA uBump 216. Figure 2This is described in one or more circuits. Each test sequence can represent a string of logic bits that can be provided (serially or in parallel) to the core die. A test sequence can have multiple bits to match the amount of data in one or more DWORDs. In example operation, when the self-test circuit is loaded, the tester can provide the bit string to DAuBump 216, which can route the DA uBump to P1500 circuit 224. The P1500 circuit can then provide the bit string to the self-test circuit, where the bits can be stored.

[0036] The DA uBump 216 facilitates functionality / communication similar to the local uBump 205, for example, for testing purposes. The DA uBump 216 can be used to transmit AWORD and DWORD in a manner similar to the local uBump 205. In some embodiments, the number of DA uBumps 216 may be less than the number of local uBumps 205. To simulate the operation of signals along the local uBump 205, the interface die 204 may include a deserializer circuit 222. The deserializer circuit 222 can receive AWORD and DWORD from the DA uBump 216 and then split the received serial data into multiple parallel channels. In some embodiments, the deserializer circuit 222 can split the AWORD and DWORD into multiple parallel channels corresponding to circuit paths associated with the local uBump 205. In some embodiments, the interface die 204 may include a DA converter 226 configured to route transmitted information to the core die 206 for testing purposes.

[0037] Returning to the reference test capacity, memory device 200 (at, for example, interface die 204) may include test verification circuitry 250, configured to verify overall testing. Test verification circuitry 250 verifies whether tests (e.g., self-tests and / or tests performed with external device 150) are executed accurately. In other words, test verification circuitry 250 may be configured to detect error passing. For example, a fault in BIST sequencer 228 could prevent memory device 200 from performing a self-test. Therefore, ECM circuitry 232 would not perform any comparisons to catch any errors, thus unintentionally indicating a test pass. Test verification circuitry 250 can prevent such failure modes by storing comparison / template data (e.g., an input stream or portion thereof provided by external device 150) and comparing said comparison / template data with a report stream to verify the self-test. The stored comparisons can be configured according to manufacturer, system requirements, test details, etc. Details regarding test verification circuitry 250 are described below.

[0038] Figure 3 This is a first example of a test verification circuit 300 according to an embodiment of the present technology (e.g., Figure 2A schematic diagram of the test verification circuit 250). The test verification circuit 300 may include an analysis circuit 302 coupled to a set of registers 304, for example... Figure 2 The analysis circuitry 302 corresponds to the internal test output / result, specifically the ECM circuitry 232 or a portion thereof (e.g., the MISR and / or BIST status registers). The analysis circuitry 302 can be configured, for example, to pass test data stored in the set of registers 304 to the input stream 320 (e.g., by...). Figure 1 External device 150, for example via Figure 2 DA uBump216 and / or Figure 2 The analysis circuit 302 internally verifies the status of the self-test by comparing the data provided by the P1500uBump 220 with the data provided by the P1500uBump 220. For example, when the test data from the set of registers 304 differs from the input stream 320, the analysis circuit 302 can provide a fault flag 306. Therefore, the analysis circuit 302 can detect / prevent one or more errors or faults, such as incorrect test implementation (e.g., false pass), and provide a distinction between errors caused by incorrect test implementation and errors caused by faults in the test target. Alternatively or additionally, the comparison results can be monitored directly using an external device 150, thereby providing timing granularity or the occurrence of miscomparison events.

[0039] As an illustrative example, analysis circuitry 302 may include a comparison device 312, such as XOR, coupled to the set of registers 304 (e.g., its outputs) and input stream 320. Comparison device 312 compares two inputs (e.g., bit-by-bit comparison) and determines whether the two inputs match or differ. Comparison device 312 may be coupled to enable circuitry 314 (e.g., NAND), which also receives a comparison signal 322. Enable circuitry 314 may be configured to allow the comparison result to proceed based on comparison signal 322. Test verification circuitry 250 and / or... Figure 2 Other circuitry within the memory device 200 may include logic (not shown) controlling the comparison signal 322. Therefore, the analysis circuitry 302 can compare the target portion of the test and / or the input stream 320. In other words, the enable circuitry 314 allows the output of the comparator 312 to control the fault flag 306 when the comparison signal 322 is activated. When the comparison signal 322 is not activated, the output of the comparator 312 can be blocked, thereby providing operational efficiency to the memory device 200 (by, for example, reducing power consumption).

[0040] The output of enable circuit 314 can be provided in real time to one or more circuits as a fault monitor signal. For example, the fault monitor signal can be provided to external device 150 via an output pin to provide visibility into the flow portion that caused the fault. The fault monitor signal can be used to analyze faults individually or in addition to analysis using fault flag 306 (e.g., analysis of fault modes with no real-time monitoring or invariant or “sticky” bits).

[0041] Analysis circuit 302 may include reset circuit 316 coupled to enable circuitry. Reset circuit 316 may be configured to reset fault flag 306 based on a reset flag. For example, fault flag 306 may notify memory device 200, external device 150, and / or test operator that a self-test or a specific portion thereof may not have been performed as intended. Reset circuit 316 may be used to reset fault flag 306 to continue subsequent portions of the same test, to perform different tests, and / or to test different devices.

[0042] Figure 4 This is a second example of a test verification circuit 400 according to an embodiment of the present technology (e.g., Figure 2 A block diagram of the test verification circuit 400 (250). The test verification circuit 400 can be configured to independently compare multiple parts of the test. The test verification circuit 400 may include analysis circuitry 402 coupled to a set of registers 404. Similar to... Figure 3 The test verification circuit 300 and analysis circuit 402 may include a comparison device 412, such as XOR, coupled to the set of registers 404 (e.g., its output) and input stream 420. The comparison device 412 may be configured to determine whether two inputs match or differ from each other.

[0043] Analysis circuit 402 may include circuit segments 4050-405 n It is configured to control the analysis of individual parts of the test (e.g., between reset flag adjustments). For example, circuit segment 4050-405... n It may include a set of enable circuits 4140-414 n Each enable circuit receives comparison signals 4220-422. n One corresponding to each of the circuits. Enable circuit 4140-414 n Each of these can be configured to allow comparison results based on comparison signals 4220-422. n The process continues for each corresponding case, thereby generating fault flags 4060-406 respectively. n The control logic (not shown) can activate the comparison signal 4220-422 at different parts / times of the self-test. n And capture comparison results at different parts or times of the self-test (e.g., fault codes 4060-406). n).

[0044] In some embodiments, from the set of enable circuits 4140-414 n The comparison result can represent a fault monitor signal, which is configured to facilitate real-time fault capture / analysis. For example, the comparison result can be combined by OR circuitry. Thus, the test verification circuitry 400 can notify in real time that an error has occurred. The fault monitor signal can be provided to one or more circuits (e.g., via an output pin to an external device 150) to provide real-time visibility into the flow / test portion that caused the fault. The fault monitor signal can be used to analyze faults individually, or in addition to analysis using fault flag 306 (e.g., analysis of fault modes with no real-time monitoring or invariant or “sticky” bits).

[0045] Analysis circuit 402 may include reset circuit system 416, which is configured to reset fault flags 4060-406. n In some embodiments, the reset circuit system 416 may include circuit segments 4050-4050, each corresponding to a circuit segment 4050-4050. n The reset circuit system 416 can be controlled according to the reset flag, so that each of the parts resets the fault flags 4060-406. n One of them corresponds to the one in the list. In other words, the reset circuit system 416 can reset the fault flags 4060-406 according to the reset flag. n .

[0046] Figure 5 This describes an operating device (e.g., according to embodiments of the technology of the present invention) Figure 1 SiP 100, Figure 1 Memory device 102, Figure 2 Memory device 200, Figure 3 Test and verification circuit 300 Figure 4 The flowchart illustrates an example method 500 (of a test verification circuit 400, a portion thereof, or a combination thereof). Method 500 may include implementation of a verification self-test process.

[0047] At box 502, the device can receive an input stream from an external device (e.g., Figure 3 and / or Figure 4 The input stream 320 can be used for the self-test process. For example, the memory device 102 / 200 can be accessed via... Figure 2 DA uBump 216 and / or Figure 2 The P1500uBump 220 from Figure 1 External device 150 receives input stream 320.

[0048] At box 504, the device can access a set of registers associated with the self-test (e.g., Figure 3 and / or Figure 4 (The set of registers 304). For example, the contents of the set of registers 304 may be determined by... Figure 3 and / or Figure 4 The comparison device 312 (e.g., an XOR device) accesses or provides the comparison device. The contents from the set of registers may correspond to test data (e.g., intermediate communication data) associated with the self-test procedure. When the self-test procedure is correctly implemented or executed, the stored test data may match one or more target portions of the input stream.

[0049] At box 506, the device can generate status flags for self-testing (e.g., Figure 3 Fault code 306 and / or Figure 4 Fault label 4060-406 n As an illustrative example, at block 512, comparison device 312 may compare the contents of the set of registers with the input stream (via, for example, an XOR comparison or another bitwise comparison). Comparison device 312 may generate a comparison result based on the comparison of the contents of the set of registers with the input stream. The comparison result may correspond to a status flag and indicate the validity associated with the implementation of the self-test procedure or its corresponding portion. In some embodiments, comparison device 312 may determine whether the self-test procedure or its portion has been implemented correctly. In other words, comparison device 312 may detect inaccurate or erroneous pass results caused by incorrect implementation or non-implementation of the self-test procedure.

[0050] At box 514, the device (e.g., comparison device 312) may, for example, be in Figure 3 Enable circuit 314 and / or Figure 4 The set of enable circuits 4140-414 n The comparison signal is received at the location. The comparison signal can be used to identify and / or select the corresponding target portion of the contents of the set of registers and the input stream.

[0051] At block 516, the device can generate a status flag based on a comparison signal. Test verification circuitry 300 / 400 can generate the status flag based on determining whether a target portion of the contents of the set of registers matches the input stream. In some embodiments, test verification circuitry 400 can generate multiple flags (e.g., fault flags 4060-406) based on comparing and evaluating multiple target portions during a self-test process (e.g., between flag resets). n ).

[0052] At block 508, the device can transmit status flags to an external device. For example, the test verification circuitry 300 / 400 can send status flags to external device 150 via one or more of the uBumps described above. Instead of the contents of the set of registers 304, the test verification circuitry 300 / 400 can send status flags. In other words, the test verification circuitry 300 / 400 can perform intermediate analysis of the self-test process and provide the analysis results as an overview with a smaller size than the analyzed data. In some embodiments, the status flags can indicate whether the self-test process was correctly implemented / executed.

[0053] At block 510, the device may, for example, reset a status flag at the end of a self-test process or at a predetermined time during the self-test process. The memory device 200 may control the reset flag to reset the status flags. In some embodiments, the memory device 200 may use a common reset flag to reset multiple status flags (e.g., fault flags 4060-406). n ).

[0054] Figure 6 This describes a manufacturing apparatus (e.g., according to embodiments of the technology of the present invention) Figure 1 Memory device 102, Figure 2 A flowchart of an example method 600 for a memory device 200, a portion thereof, or a combination thereof. Method 600 (e.g., providing a process) may include, for example, forming a semiconductor through a semiconductor manufacturing process (e.g., doping, masking, removal / etching, etc.). Figure 3 Test and verification circuit 300 Figure 4 The test and verification circuit 400, a part thereof, or a combination thereof.

[0055] At block 602, method 600 may include circuitry providing functionality (e.g., Figure 2 Core nude 206 and / or Figure 2 (One or more portions of the interface die 204). For example, one or more dies including memory arrays, RAM devices, etc., can be fabricated. Moreover, one or more circuits of the interface die 204 can be formed on a silicon substrate.

[0056] At block 604, method 600 may include providing a self-test circuitry system. For example, the semiconductor substrate of interface die 204 may be processed to form... Figure 2 P1500 circuit 224, Figure 2 BIST sequencer 228 Figure 2 ECM circuit 232, etc. The self-test circuit system may include the following components: Figure 3 and / or Figure 4 The set of registers 304 is as illustrated in box 612.

[0057] At block 606, method 600 may include forming test and verification circuitry. The semiconductor substrate for interface die 204 may be processed to form... Figure 2 The test and verification circuit 250, for example Figure 3 Test and verification circuit 300 or Figure 4 The test and verification circuit 400 (e.g., its analysis circuit).

[0058] As an illustrative example, at block 622, method 600 may include providing a comparison device (e.g., an XOR device). The comparison device may be coupled and / or configured to compare test data or contents stored in the set of registers 304 with the input stream 320. At block 624, method 600 may include enabling circuitry (e.g., Figure 3 Enable circuit 314 or Figure 4 Enable circuit 4140-414 n ) is connected to the comparator. At block 626, method 600 may include connecting a reset circuit (e.g., Figure 3 The reset circuit 316 or Figure 4 The reset circuit system 416) is connected to the comparator.

[0059] At box 608, method 600 may include forming an external connector, for example... Figure 2 DA uBump 216 Figure 2 Examples include the P1500 uBump 220. Method 600 can therefore form or provide an HBM interface die 204 and / or a memory device 102 / 200.

[0060] In some embodiments, the memory device 102 / 200 may include test and verification circuitry. The provided memory device can be processed, for example, by installing the memory device... Figure 1 On the inserter 112, Figure 1 The processor 110 is installed into the inserter 112, etc. Figure 1 SiP 100.

[0061] Figure 7 This is a schematic diagram of a system including an apparatus according to an embodiment of the technology according to the present invention. (See above reference) Figures 1 to 6 Any of the aforementioned devices (e.g., memory devices) described can be incorporated into or implemented in a memory (e.g., memory device 700) or any of a large number of larger and / or more complex systems, a representative example of which is... Figure 7 The system 780 is schematically shown in the diagram. System 780 may include a memory device 700, a power supply 782, a driver 784, a processor 786, and / or other subsystems or components 788. The memory device 700 may include components similar to those described above. Figures 1 to 6The described devices share generally similar features and therefore may include various features from a host device for performing direct read requests. The resulting system 780 can perform any of a wide range of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 780 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 780 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 780 may also include remote devices and any of a variety of computer-readable media.

[0062] In summary, it should be understood that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Furthermore, certain aspects of the new technology described in the context of specific embodiments may be combined or removed in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are required to exhibit such advantages to fall within the scope of the present invention. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

[0063] In the embodiments described above, the devices have been described in the context of HBM and DRAM devices. However, devices configured according to other embodiments of the present invention may include other types of suitable storage media besides or replacing HBM and / or DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0064] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting, and / or manipulating data structures. The term "data structure" includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. Furthermore, as used herein, the term "dynamic" describes a process, function, action, or implementation that occurs during the operation, use, or deployment of the corresponding device, system, or embodiment, and after or concurrently with the running of the manufacturer's firmware or third-party firmware. Dynamic processes, functions, actions, or implementations may occur after or after design, manufacturing, and initial testing, setup, or configuration.

[0065] The embodiments described above are given in sufficient detail to enable those skilled in the art to make and use them. However, those skilled in the art will understand that the technology may have additional embodiments, and that the technology may be implemented without the foregoing reference. Figures 1 to 7 The described embodiments are practiced in several details.

Claims

1. A memory device comprising: A self-test circuit configured to perform a self-test process or a portion thereof to determine the operating conditions of the memory device, wherein the self-test process includes (1) receiving an input stream from an external device and (2) storing test data at a predetermined location, wherein the test data is associated with the self-test process. An external connector coupled to the self-test circuit and configured to provide an interface between the memory device and the external device; and A test verification circuit, coupled to the self-test circuit and the external connector, is configured to generate a flag based on comparing the input stream or a portion thereof with content stored at the predetermined location, wherein the flag indicates the validity associated with the implementation of the self-test process or a portion thereof.

2. The memory device of claim 1, wherein the test verification circuit is configured to provide the flag, rather than the content stored at the predetermined location, wherein the flag is accessed by the external device via the external connector and corresponds to fewer bits than the compared portion of the content stored at the predetermined location.

3. The memory device of claim 1, wherein the predetermined location includes a set of registers configured to internally store the test data, wherein the test verification circuitry is coupled to the set of registers and the external connector and is located between the set of registers and the external connector.

4. The memory device of claim 1, wherein the test verification circuitry is configured to generate a comparison output based on performing a bit-by-bit comparison between the input stream and the content stored at the predetermined location.

5. The memory device of claim 4, wherein the test verification circuit comprises an XOR device.

6. The memory device of claim 4, further comprising: An enable circuit, coupled to the test verification circuit and configured to generate the flag based on a comparison signal, wherein the enable circuit uses the comparison signal to generate the flag, the flag representing a comparison between one or more target portions of the input stream and the content stored at the predetermined location.

7. The memory device of claim 6, further comprising: An external connector electrically coupled to the output of the enable circuit, wherein The output of the activation circuit includes a fault monitor signal, which represents a real-time output of the comparison between one or more target portions of the input stream and the content stored at the predetermined location. The external connector is configured to provide the fault monitor signal to the external device in real time.

8. The memory device of claim 6, wherein the enable circuit includes a first enable circuit, the flag includes a first flag, and the flag is a first flag indicating the comparison between a first target portion of the input stream and the content stored at the predetermined location, the memory device further comprising: A second enable circuit is coupled to the test verification circuit and configured to generate a second flag based on a second comparison signal, wherein the second enable circuit uses the second comparison signal to generate the second flag, the second flag representing a comparison between a second target portion of the input stream and the content stored at the predetermined location.

9. The memory device of claim 8, further comprising: A reset circuit coupled to the first enable circuit and the second enable circuit, the reset circuit being configured to reset the first and second flags based on a reset flag.

10. The memory device of claim 8, further comprising: The OR circuit is configured to (1) receive a first output from the first enable circuit and a second output from the second enable circuit, and (2) generate a fault monitor signal based on a logical OR operation of the received signals, wherein the fault monitor signal represents a real-time output of the comparison between the target portion of the input stream and the content stored at the predetermined location.

11. The memory device according to claim 1, wherein: The memory device includes a memory unit configured to store data; The self-test process is configured to verify the memory device's ability to read and write data; and The flag is configured to indicate whether the self-test process was performed accurately and is separate from the result of the self-test process.

12. The memory device of claim 11, wherein the test verification circuit is configured to detect inaccurate pass results caused by incorrect implementation or non-implementation of the self-test process.

13. A method for operating a memory device, the method comprising: Receive an input stream from an external device, wherein the input stream is used to perform a self-test process that interacts with the external device and verifies the operating conditions of the memory device; Access a set of registers corresponding to the test data associated with the self-test process; and A status flag is generated by internally comparing the contents of the set of registers with the input stream, wherein the status flag indicates the validity associated with the implementation of the self-test process or a portion thereof.

14. The method of claim 13, further comprising: Transmit the status flags, instead of the contents of the set of registers, to report the results of the self-test process or a portion thereof to the external device.

15. The method of claim 13, wherein generating the status flag comprises performing a bit-by-bit comparison between the input stream and the contents of the set of registers.

16. The method of claim 15, wherein generating the status flag comprises providing the contents of the set of registers and the input stream to the XOR device.

17. The method of claim 13, wherein: The set of registers is configured to store the test data that matches the input stream when the self-test process is performed correctly; and Generating the status flag includes determining whether the self-test process or a portion thereof has been correctly implemented.

18. The method of claim 13, wherein generating the status flag comprises generating the status flag based on a comparison signal corresponding to one or more target portions of the contents of the set of registers and the input stream.

19. The method of claim 18, wherein generating the status flag includes generating a first flag based on a first comparison signal, the first comparison signal corresponding to a first target portion of the content and the input stream, further comprising: A second flag is generated based on a second comparison signal, the second comparison signal corresponding to a second target portion of the input stream and the content thereof.

20. The method of claim 19, further comprising: The first and second flags are reset based on a common reset flag.

21. The method according to claim 13, wherein: The memory device includes a memory unit configured to store data; The self-test process is configured to verify the memory device's ability to read and write data; and The status flag is configured to indicate whether the self-test process was performed accurately and is separate from the result of the self-test process.

22. The method of claim 21, wherein generating the status flag includes detecting inaccurate pass results caused by erroneous implementation or non-implementation of the self-test process.

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