Semiconductor Structure and Method of Manufacturing the Same

Abstract

Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a semiconductor structure including a plurality of spaced semiconductor layers and isolation layers located between adjacent semiconductor layers, with trenches in the semiconductor layers and the isolation layers, the trenches including a first region, a second region, and a third region arranged in sequence; forming a sacrificial layer on the inner wall of the trenches in the first region and the second region; forming an insulating layer that fills the trenches on the surface of the sacrificial layer; removing the sacrificial layer in the second region and a first thickness of the isolation layer to form pores surrounding the semiconductor layers; forming a gate dielectric layer on the sidewalls of the exposed semiconductor layers; stacking a first gate electrode layer and a second gate electrode layer in sequence on the gate dielectric layer in the direction from the first region to the third region, the first gate electrode layer also being located on the top surface of the remaining isolation layer, and the work function value of the second gate electrode layer being different from that of the first gate electrode layer. Embodiments of the present application are beneficial to reducing the drain leakage current in the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the integration density of dynamic memories develops towards higher levels, while researching the arrangement of transistors in the dynamic memory array structure and how to reduce the size of a single functional device in the dynamic memory array structure, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When using a vertical Gate-All-Around (GAA) transistor structure as a dynamic memory access transistor, the area it occupies can reach 4F2 (F: the minimum pattern size obtainable under given process conditions). In principle, a higher density efficiency can be achieved. However, due to the reduction in the spacing between the gate electrode layer and the semiconductor layer, the impact of gate-induced drain leakage (GIDL) on the electrical performance of the semiconductor structure increases. Summary of the Invention

[0004] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial to reducing the drain leakage current of the semiconductor structure.

[0005] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including a plurality of spaced semiconductor layers and isolation layers located between adjacent semiconductor layers, the semiconductor layers and the isolation layers having trenches, the semiconductor layers being spaced apart along a first direction and a second direction respectively, the trenches extending along the second direction, and the trenches being spaced along the first direction, the second direction being different from the first direction, the trenches including a first region, a second region, and a third region sequentially distributed in a direction from the bottom of the trench to the top of the trench; forming a sacrificial layer on the inner walls of the trenches in the first region and the second region; forming an insulating layer that fills the trenches on the surface of the sacrificial layer, and the insulating layer also exposing at least a part of the surface of the isolation layer; removing the sacrificial layer in the second region and removing a first thickness of the isolation layer to form pores surrounding the semiconductor layers, the pores exposing part of the side walls of the semiconductor layers; forming a gate dielectric layer on the exposed side walls of the semiconductor layers; forming a first gate electrode layer on part of the gate dielectric layer, the first gate electrode layer also being located on the top surface of the remaining isolation layer; forming a second gate electrode layer on the remaining gate dielectric layer, the work function value of the second gate electrode layer being different from the work function value of the first gate electrode layer, and the first gate electrode layer and the second gate electrode layer being stacked in a direction from the first region to the third region.

[0006] In addition, the process steps for forming the sacrificial layer and the insulating layer include: forming a sacrificial film, the sacrificial film being located on the entire inner wall of the trench; forming a first insulating layer that fills the trench on the sacrificial film; removing the sacrificial film on the inner wall of the trench in the third region, and the remaining sacrificial film serving as the sacrificial layer; forming a second insulating layer on the inner wall of the trench in the third region, and the second insulating layer also being located on the side wall of the first insulating layer, the second insulating layer and the first insulating layer serving as the insulating layer.

[0007] In addition, while removing the sacrificial film on the inner wall of the trench in the third region, a second thickness of the isolation layer is also removed, and the remaining isolation layer exposes part of the side walls of the semiconductor layers; in the process step of forming the second insulating layer, the second insulating layer is also located on the side walls of the semiconductor layers exposed by the remaining isolation layer.

[0008] In addition, a wet etching process is used to etch and remove the sacrificial film on the inner wall of the trench in the third region, and the wet etching process has the same etching rate for the isolation layer and the sacrificial film.

[0009] In addition, the process steps for forming the second insulating layer include: forming an insulating film that fills the region between the inner wall of the trench in the third region and the first insulating layer, and is also located on the top surface of the remaining isolation layer and the sidewalls of the exposed semiconductor layer, and is also located on the top surface of the semiconductor layer; performing a re-etch on the insulating film to remove the insulating film higher than the top surface of the semiconductor layer, and also removing at least a portion of the insulating film on the top surface of the isolation layer, with the remaining insulating film serving as the second insulating layer.

[0010] In addition, the process steps for forming the sacrificial layer include: forming a sacrificial film that covers the entire inner wall of the trench and is also located on the top surface of the semiconductor layer; performing a re-etch on the sacrificial film to etch away the sacrificial film located at the bottom of the trench, on the top surface of the semiconductor layer, and on the inner wall of the trench in the third region, with the remaining sacrificial film serving as the sacrificial layer.

[0011] In addition, in the process step of performing a re-etch on the sacrificial film, a second thickness of the isolation layer is also removed, and an opening is formed between the adjacent semiconductor layer and the remaining isolation layer; the process steps for forming the insulating layer include: forming an insulating film that fills the trench on the sacrificial layer, and the insulating film also fills the opening; removing at least a portion of the insulating film within the opening to expose at least a portion of the top surface of the remaining isolation layer, with the remaining insulating film and the first insulating layer serving as the insulating layer.

[0012] In addition, in the process step of performing a re-etch on the sacrificial film, it also includes: removing the sacrificial layer in the second region; the process steps for forming the gate dielectric layer include: forming a dielectric layer at least on the inner walls of the trenches in the second region and the third region, and the dielectric layer on the inner wall of the trench in the second region serves as the gate dielectric layer.

[0013] In addition, before forming the insulating layer, it also includes: performing a first metallization process on the semiconductor layer below the bottom of the trench to convert a portion of the thickness of the semiconductor layer into bit lines, and the bit lines extend along the first direction, and the material of the bit lines is a metal semiconductor compound.

[0014] In addition, the process steps for forming the sacrificial layer include: forming a sacrificial film on all inner walls of the trench; the first metallization process includes: forming a metal layer on the surface of the sacrificial film, and the metal layer is also located at the bottom of the trench; performing an annealing process to cause the metal layer to react with the semiconductor layer to form the bit lines; removing the remaining unreacted metal layer.

[0015] In addition, the manufacturing method also includes: after forming the sacrificial layer, performing a second metallization process on the semiconductor layer above the top surface of the second gate electrode layer to form a metal silicide layer.

[0016] In addition, the first metallization process and the second metallization process are performed in the same process step.

[0017] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a semiconductor structure, including: a substrate, the substrate includes a plurality of spaced semiconductor layers and isolation layers located between adjacent semiconductor layers, trenches are formed in the semiconductor layers and the isolation layers, the semiconductor layers extend in a first direction, the trenches extend in a second direction, the second direction is different from the first direction, the trenches include a first region, a second region, and a third region sequentially distributed from the bottom of the trench to the top of the trench; a sacrificial layer, the sacrificial layer is located on the inner wall of the trench in the first region; a gate dielectric layer, a first gate electrode layer, and a second gate electrode layer, the first gate electrode layer and the second gate electrode layer are both located on the gate dielectric layer and are jointly located in the trench in the second region and surround the semiconductor layer, and the first gate electrode layer is further located on the top surface of the isolation layer, the second gate electrode layer and the first gate electrode layer are stacked in the direction from the first region to the third region, and the work function value of the second gate electrode layer is different from the work function value of the first gate electrode layer; an insulating layer, the insulating layer is located in the trench and isolates two opposite gate electrode layers located in the same trench, and the insulating layer is further located in the trench filled with the third region.

[0018] In addition, the top surface of the isolation layer directly below the first gate electrode layer is flush with the top surface of the sacrificial layer.

[0019] In addition, the semiconductor structure further includes: bit lines extending in the first direction, the bit lines are located at the bottom of the trenches and directly below the bottoms of adjacent trenches, and the material of the bit lines is a metal semiconductor compound.

[0020] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0021] In the above technical solution, in the direction from the first region to the third region, a first gate electrode layer and a second gate electrode layer are sequentially stacked on the gate dielectric layer, and the work function value of the second gate electrode layer is different from that of the first gate electrode layer. Thus, it is beneficial to reduce the work function value of the gate electrode layer composed of the first gate electrode layer and the second gate electrode layer by adjusting the work function values of the second gate electrode layer and the first gate electrode layer, as well as the size ratio of the first gate electrode layer to the second gate electrode layer, so as to reduce the difference between the work function value of the gate electrode layer and the work function value of the semiconductor layer. On the one hand, it is beneficial to reduce the lateral electric field at the corresponding position between the gate electrode layer and the semiconductor layer, reduce GIDL, and thus is beneficial to improving the on / off ratio of the channel region to improve the sensitivity of controlling the on / off of the channel region. On the other hand, it is beneficial to reduce the threshold voltage of the transistor while making the gate electrode layer applicable to different types of transistors, which is beneficial to reducing the manufacturing process of the semiconductor structure and the manufacturing cost.

[0022] In addition, a vertical GAA transistor is formed on the substrate, and the bit line is located between the substrate and the GAA transistor, so that a 3D stacked semiconductor structure can be formed, which is beneficial to improving the integration density of the semiconductor structure. Moreover, by forming pores, a gate dielectric layer and a gate electrode layer are sequentially formed on the sidewalls of the semiconductor layer exposed in the pores, which is beneficial to forming a gate dielectric layer and a gate electrode layer with precise dimensions in the pores by a self-alignment method, beneficial to simplifying the formation steps of the gate dielectric layer and the gate electrode layer, and by controlling the size of the pores, a small-sized gate dielectric layer and a gate electrode layer can be obtained. Description of the Drawings

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0024] Figures 1 to 42 Structural schematic diagrams corresponding to the steps of the manufacturing method of the semiconductor structure provided by an embodiment of the present application;

[0025] Figures 43 to 48 Structural schematic diagrams corresponding to the steps of the manufacturing method of the semiconductor structure provided by another embodiment of the present application;

[0026] Figures 49 to 54 Structural schematic diagrams corresponding to the steps of the manufacturing method of the semiconductor structure provided by still another embodiment of the present application. Detailed Description of the Embodiment

[0027] As can be seen from the background art, in the currently formed semiconductor structure, the drain leakage current needs to be reduced, and the electrical performance of the semiconductor structure needs to be improved.

[0028] Upon analysis, it is found that in the GAA transistor of the semiconductor structure, in order to improve the conductivity of the source, drain, and channel regions, the semiconductor layer including the source, drain, and channel regions is doped, and the concentration of doped ions in the source, drain, and channel regions is relatively high. This increases the lateral electric field at the corresponding position between the gate electrode layer and the semiconductor layer, enhances the GIDL, and reduces the on / off ratio of the channel region, making it difficult for the gate electrode layer to control the closing of the channel region, thereby reducing the electrical performance of the semiconductor structure. In addition, the threshold voltage of the transistor is mainly determined by the difference between the work function value of the gate electrode layer and the work function value of the semiconductor layer. Since the work function values of the semiconductor layers of different types of transistors (such as PMOS or NMOS) are different, in order to reduce the difference between the work function value of the gate electrode layer and the work function value of the semiconductor layer to reduce the threshold voltage of the transistor, it is necessary to configure gate electrode layers of different materials for different transistors, increasing the manufacturing process and cost of the semiconductor structure.

[0029] The present application provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first gate electrode layer and a second gate electrode layer with different work function values are sequentially stacked on the gate dielectric layer. The first gate electrode layer and the second gate electrode layer together form the gate electrode layer. In this way, it is beneficial to adjust the relevant parameters of the first gate electrode layer and the second gate electrode layer to reduce the work function value of the gate electrode layer, so as to reduce the difference between the work function value of the gate electrode layer and the work function value of the semiconductor layer. On the one hand, it is beneficial to reduce the lateral electric field at the corresponding position between the gate electrode layer and the semiconductor layer, reduce the GIDL, and thus improve the on / off ratio of the channel region to improve the sensitivity of controlling the on / off of the channel region. On the other hand, it is beneficial to reduce the threshold voltage of the transistor while making the gate electrode layer suitable for different types of transistors by regulating the relevant parameters of the first gate electrode layer and the second gate electrode layer, thereby reducing the manufacturing process and cost of the semiconductor structure.

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0031] An embodiment of the present application provides a manufacturing method of a semiconductor structure. The following will detail the manufacturing method of the semiconductor structure provided by an embodiment of the present application with reference to the accompanying drawings. Figures 1 to 42Schematic diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present application. It should be noted that, for the convenience of description and to clearly illustrate the steps of the semiconductor structure manufacturing method, in this embodiment, Figures 1 to 42 are all partial structure schematic diagrams of the semiconductor structure.

[0032] Among them, Figure 2 is Figure 1 a top view of the structure shown, Figure 6 is a cross-sectional schematic diagram along the first cross-sectional direction AA1 after forming a first protective layer and an initial sacrificial film on the basis of Figure 2 , Figure 7 is a cross-sectional schematic diagram along the second cross-sectional direction BB1 after forming a first protective layer and an initial sacrificial film on the basis of Figure 2 , Figure 8 is a cross-sectional schematic diagram along the third cross-sectional direction CC1 after forming a first protective layer and an initial sacrificial film on the basis of Figure 2 , Figure 9 is a cross-sectional schematic diagram along the fourth cross-sectional direction DD1 after forming a first protective layer and an initial sacrificial film on the basis of Figure 2 . It should be noted that subsequently, one, two, three, or four of the cross-sectional schematic diagram along the first cross-sectional direction AA1, the cross-sectional schematic diagram along the second cross-sectional direction BB1, the cross-sectional schematic diagram along the third cross-sectional direction CC1, and the cross-sectional schematic diagram along the fourth cross-sectional direction DD1 will be set according to the expression needs.

[0033] Referring to Figure 1 and Figure 2 , a substrate 100 is provided. The substrate 100 includes a plurality of semiconductor layers 101 arranged at intervals and isolation layers 102 located between adjacent semiconductor layers 101. The semiconductor layers 101 and the isolation layers 102 have trenches 103. The semiconductor layers 101 extend along a first direction X, the trenches 103 extend along a second direction Y, and the trenches 103 are arranged at intervals along the first direction X. The second direction Y is different from the first direction X. The trenches 103 include a first region a, a second region b, and a third region c distributed in sequence in the direction Z from the bottom of the trench 103 to the top of the trench 103.

[0034] Wherein, in the direction Z pointing from the bottom of the trench 103 to the top of the trench 103, the semiconductor layer 101 includes an initial bit line 124, a first doped region I, a channel region II, and a second doped region III arranged in sequence. It should be noted that both the first doped region I and the second doped region III can serve as the source or drain of the GAA transistor formed subsequently with the semiconductor layer 101, the channel region II corresponds to the gate electrode layer of the GAA transistor, and the initial bit line 124 is prepared for forming the bit line subsequently. In addition, the first region a of the trench 103 corresponds to the first doped region I of the semiconductor layer 101, the second region b of the trench 103 corresponds to the channel region II of the semiconductor layer 101, and the third region c of the trench 103 corresponds to the second doped region III of the semiconductor layer 101. That is, when the plane formed by the set direction Y and the direction Z is the first plane, the orthographic projection of the first region a on the first plane covers the orthographic projection of the first doped region I on the first plane, and in the direction Z, the height of the orthographic projection of the first region a on the first plane is equal to the height of the orthographic projection of the first doped region I on the first plane. The relationship between the orthographic projection of the second region b and the channel region II on the first plane and the relationship between the orthographic projection of the third region c and the second doped region III on the first plane are the same as the relationship between the orthographic projection of the first region a and the first doped region I on the first plane, which will not be elaborated here.

[0035] In some embodiments, the steps of providing the substrate 100 include the following:

[0036] Referring to Figure 3 , an initial substrate 110 is provided. Specifically, the material type of the initial substrate 110 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0037] The initial substrate 110 is subjected to doping treatment and annealing treatment so that N-type ions or P-type ions are doped in the initial substrate 110 for subsequently forming a bit line and a semiconductor layer on the basis of the initial substrate 110. Specifically, the N-type ions can be at least one of arsenic ions, phosphorus ions, or antimony ions; the P-type ions can be at least one of boron ions, indium ions, or gallium ions. For example, the doping concentration of the doping ions in the initial substrate 110 can be 1×10 19 atom / cm 3 ~1×10 20 atom / cm 3 , and the doping depth of the doping ions in the initial substrate 110 can be 150 nm to 250 nm.

[0038] Continuing to refer to Figure 3, a first mask layer 120 is formed on the initial substrate 110. The first mask layer 120 has a plurality of discrete first openings d that extend along a first direction X, and the length of the first openings d is consistent with the length of the bit lines to be formed subsequently.

[0039] With reference to Figure 3 and Figure 4 , the initial substrate 110 is etched using the first mask layer 120 as a mask to form a plurality of first trenches e, and the first mask layer 120 is removed. In some embodiments, along the direction Z perpendicular to the surface of the substrate 100, the depth of the first trenches e can be 250 - 300 nm. The doping depth of the doping ions in the initial substrate 110 pointing towards the first mask layer 120 within the initial substrate 110 can be 150 nm - 250 nm. Since the depth of the first trenches e is greater than the doping depth of the doping ions in the initial substrate 110, it is beneficial to ensure that the initial substrate 110 doped with doping ions is etched uniformly, facilitating the subsequent formation of a semiconductor layer and bit lines with a high doping concentration of doping ions.

[0040] With reference to Figure 4 and Figure 5 , a deposition process is performed to form an isolation film covering the top surface of the initial substrate 110 and filling the first trenches e; the isolation film is subjected to chemical mechanical planarization until the top surface of the initial substrate 110 is exposed; a second mask layer 130 is formed on the top surface jointly formed by the isolation film and the remaining initial substrate 110. The second mask layer 130 has a plurality of discrete second openings that extend along a second direction Y, and the length of the second openings is consistent with the length of the gate electrode layer to be formed subsequently.

[0041] In some embodiments, with reference to Figures 3 to 5 , the first direction X is perpendicular to the second direction Y, such that the formed semiconductor layer 101 exhibits an arrangement pattern of 4F 2 (F: the minimum pattern size that can be obtained under given process conditions), which is beneficial to improving the integration density of the semiconductor structure. In other embodiments, the first direction intersects with the second direction, and the included angle between the two can be not 90°.

[0042] With reference to Figure 5 and Figure 1 , the initial substrate 110 is etched using the second mask layer 130 as a mask (reference Figure 4) and the isolation film to form the substrate 100, the substrate 100 includes: a plurality of trenches 103, a plurality of semiconductor layers 101 and a plurality of isolation layers 102, wherein the semiconductor layer 101 includes an initial bit line 124, a first doped region I, a channel region II, and a second doped region III arranged in sequence, and the first doped region I, the channel region II, and the second doped region III constitute a semiconductor channel. In the direction Z perpendicular to the surface of the substrate 100, the depth of the trench 103 is less than the depth of the first trench e (reference Figure 4 ), which is beneficial to forming a plurality of mutually separated semiconductor channels on one side of the initial bit line 124 while forming the initial bit line 124, and the initial bit line 124 is in contact with the first doped region I of the semiconductor channel; remove the second mask layer 130.

[0043] To achieve electrical insulation between adjacent initial bit lines 124 and adjacent semiconductor channels, after etching the initial substrate 110 and the isolation film using the second mask layer 130 as a mask, the remaining isolation film is also located in the space between adjacent initial bit lines 124 and in the space between adjacent semiconductor channels.

[0044] Among them, the method for forming the initial bit line 124, the semiconductor channel, and the isolation layer 102 includes self-aligned quadruple patterning (SAQP, Self-Aligned Quadruple Patterning) or self-aligned double patterning (SADP, Self-aligned Double Patterning).

[0045] In some embodiments, the depth of the trench 103 is 100 nm to 150 nm. Since the doping depth of the doped ions in the initial substrate 110 (reference Figure 4 ) is 150 nm to 250 nm, it is beneficial to convert most or all of the initial substrate 110 doped with doped ions into a semiconductor channel through two etching processes. In addition, in some embodiments, reference Figure 5 , the material of the initial substrate 110 is silicon, and the material of the isolation film is silicon oxide. In the step of etching the initial substrate 110 and the isolation film using the second mask layer 130 as a mask, the etching rate of the silicon oxide is greater than the etching rate of the silicon, so that part of the sidewall of the initial bit line 124 will be exposed. In other embodiments, in the step of etching the initial substrate and the isolation film using the second mask layer as a mask, the etching rate of the initial substrate and the etching rate of the isolation layer can be the same, so that the sidewalls of the initial bit line are surrounded by the isolation layer.

[0046] It should be noted that a plurality of spaced-apart initial bit lines 124 can be formed on the initial substrate 110, and each initial bit line 124 can be in contact with at least one first doped region I. Figure 5Taking four mutually spaced initial bit lines 124 as an example, and each initial bit line 124 being in contact with four first doped regions I. In practical applications, the number of initial bit lines 124 and the number of first doped regions I in contact with each initial bit line 124 can be reasonably set according to actual electrical requirements.

[0047] In addition, the device formed by the semiconductor channel is a junctionless transistor, that is, the types of doped ions in the first doped region I, the channel region II, and the second doped region III are the same. For example, the doped ions are all N-type ions, and the doped ions in the first doped region I, the channel region II, and the second doped region III can be the same. Here, "junctionless" means no PN junction, that is, there is no PN junction in the transistor formed by the semiconductor layer 101, that is, the doping concentrations of the doped ions in the first doped region I, the channel region II, and the second doped region III are the same. The advantages include: on the one hand, there is no need for additional doping of the first doped region I and the second doped region III, thus avoiding the problem that the doping process of the first doped region I and the second doped region III is difficult to control. Especially as the transistor size is further reduced, if the first doped region I and the second doped region III are additionally doped, the doping concentration is even more difficult to control; on the other hand, since the device is a junctionless transistor, it is beneficial to avoid the phenomenon of making a super-steep source-drain concentration gradient doping process to form a super-steep PN junction in the nanoscale range. Therefore, problems such as threshold voltage drift and increased leakage current caused by doping mutations can be avoided, and it is also beneficial to suppress the short-channel effect and still work in the range of a few nanometers. Therefore, it helps to further improve the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping here refers to the doping carried out to make the types of doped ions in the first doped region I and the second doped region III different from those in the channel region II.

[0048] In some embodiments, a GAA transistor with a semiconductor channel perpendicular to the top surface of the initial bit line 124 can form a 3D stacked semiconductor structure, which is beneficial to designing GAA transistors with smaller size features without adversely affecting the electrical performance of the GAA transistors, so as to improve the integration density of the semiconductor structure.

[0049] In this embodiment, by using the first mask layer 120 and the second mask layer 130, the initial bit line 124 and the semiconductor layer 101 are simultaneously formed through two etching processes. On the one hand, it is beneficial to control the size of the semiconductor layer 101 by regulating the sizes of the first opening d and the second opening, and a semiconductor layer 101 with higher dimensional accuracy is formed; on the other hand, both the initial bit line 124 and the semiconductor layer 101 are formed by etching the initial substrate 110, that is, the initial bit line 124 and the semiconductor layer 101 are formed using the same film layer structure, so that the initial bit line 124 and the semiconductor layer 101 are an integral structure, thereby improving the interfacial state defects between the initial bit line 124 and the semiconductor layer 101 and improving the performance of the semiconductor structure.

[0050] Reference Figure 2 and Figures 6 to 33 , a sacrificial layer 125 is formed on the inner wall of the trench 103 in the first region a and the second region b; an insulating layer 126 filling the trench 103 is formed on the surface of the sacrificial layer 125, and at least part of the surface of the isolation layer 102 is also exposed by the insulating layer 126.

[0051] Among them, forming the sacrificial layer 125 and the insulating layer 126 includes the following process steps:

[0052] Reference Figures 6 to 16 , a sacrificial film 115 is formed, and the sacrificial film 115 is located on the entire inner wall of the trench 103.

[0053] In some embodiments, before forming the sacrificial film, referring to Figures 6 to 9 , a first protective layer 160 is formed on the top surface of the semiconductor layer 101 far from the initial bit line 124 and on the top surface of the isolation layer 102 far from the initial bit line 124. The first protective layer 160 is used to protect the second doped region III during the subsequent first metallization process of the initial bit line 124 to prevent the second doped region III from being metallized. Among them, the material of the first protective layer 160 can be silicon oxide, silicon oxynitride or silicon nitride.

[0054] Continue to refer to Figures 6 to 9 , an initial sacrificial film 105 is formed. The initial sacrificial film 105 is not only located on the entire inner wall of the trench 103, but also on the surface exposed by the first protective layer 160 and the bottom surface of the trench 103.

[0055] In other embodiments, referring to Figures 10 to 12 , after providing the substrate 100 (referring to Figure 1 ), before forming the initial sacrificial film 105, the top surface of the semiconductor layer 101 far from the initial bit line 124 and the top surface of the isolation layer 102 far from the initial bit line 124 are both exposed. Subsequently, both the first metallization process of the initial bit line 124 and the second metallization process of the second doped region III are performed.

[0056] Among them, when the initial sacrificial film 105 is formed on the entire inner wall of the trench 103, the initial sacrificial film 105 is also located on the top surface of the semiconductor layer 101 away from the initial bit line 124, the top surface of the isolation layer 102 away from the initial bit line 124, and the bottom surface of the trench 103.

[0057] In the above two embodiments, the material of the initial sacrificial film 105 can be silicon oxide, silicon oxynitride or silicon nitride. In addition, the material of the initial sacrificial film 105 can be the same as the material of the isolation layer 102, which is convenient for subsequent removal of the initial sacrificial film 105 on the inner wall of the trench 103 and the second thickness of the isolation layer 102 located in the second region b through an etching process, so as to form pores surrounding the side wall of the channel region II, which is beneficial to the subsequent preparation of the gate electrode layer. Among them, the materials of both the initial sacrificial film 105 and the isolation layer 102 can be silicon oxide.

[0058] In other embodiments, the materials of the initial sacrificial film and the isolation layer can also be different, as long as the materials of the initial sacrificial film and the isolation layer are both materials with good insulation effects, and then the initial sacrificial film on the inner wall of the trench in the second region and the second thickness of the isolation layer can be removed step by step.

[0059] In the above two embodiments, with reference to Figures 6 to 9 and Figures 13 to 14 , or with reference to Figures 10 to 12 and Figures 15 to 16 , a sacrificial film 115 is formed, and the sacrificial film 115 is located on the entire inner wall of the trench 103.

[0060] Among them, an unmasked dry etching process is performed on the initial sacrificial film 105 until the substrate 100 located at the bottom of the trench 103 is exposed (refer to Figure 1 ). During the same etching time, the etching process etches the initial sacrificial film 105 with the same thickness in different regions to form the sacrificial film 115.

[0061] In some embodiments, with reference to Figures 17 to 19 , when the first protective layer 160 is formed on both the top surface of the semiconductor layer 101 away from the initial bit line 124 and the top surface of the isolation layer 102 away from the initial bit line 124, before forming the insulating layer 126, the manufacturing method may further include: performing a first metallization process on the semiconductor layer 101 below the bottom of the trench 103 (i.e., the initial bit line 124) to convert a part of the semiconductor layer 101 with a certain thickness into the bit line 104, and the bit line 104 extends along the first direction X (refer to Figure 1 ), and the material of the bit line 104 is a metal semiconductor compound.

[0062] Among them, the first metallization process includes: forming a metal layer (not shown in the figure) on the surface jointly formed by the sacrificial film 115 and the first protective layer 160, and the metal layer is also located at the bottom of the trench 103; performing an annealing process to enable the metal layer to react with the semiconductor layer 101 to form a bit line 104; removing the remaining unreacted metal layer.

[0063] It should be noted that in some embodiments, the material of the region of the initial bit line directly below the first doping region is a semiconductor material, and the material of the partial region of the initial bit line not covered by the first doping region is a metal semiconductor compound. It can be understood that as the device size continues to shrink or the manufacturing process parameters are adjusted, the material of the partial region of the initial bit line directly below the first doping region is a semiconductor material, and the material of the remaining region of the initial bit line directly below the first doping region can also be a metal semiconductor compound. The position of the "remaining region" here is located on the periphery of the "partial region".

[0064] For example, referring to Figures 17 to 19 , multiple metal semiconductor compounds in the semiconductor layer 101 are interconnected to form a bit line 104, and the bit line 104 is composed of a partially metallized first doping region I and a partially metallized initial bit line 124, that is, the material of the entire bit line 104 is a metal semiconductor compound; or, referring to Figure 20 , multiple metal semiconductor compounds in the semiconductor layer 101 are spaced apart from each other, and the bit line 104 is composed of a partially metallized first doping region I, a partially metallized initial bit line 124, and the initial bit line 124 that is not metallized between adjacent metal semiconductor compounds, that is, the material of the bit line 104 is a mixed material of a metal semiconductor compound and a semiconductor material.

[0065] It should be noted that Figure 17 and Figure 20 The region of the semiconductor layer 101 defined by the dashed line box similar to an ellipse is a metal semiconductor compound, and in practical applications, the size of the region where adjacent metal semiconductor compounds are in contact with each other is not limited. In other embodiments, the entire thickness of the initial bit line can be converted into a bit line.

[0066] In other embodiments, referring to Figures 21 to 22 , when the top surface of the semiconductor layer 101 far from the initial bit line 124 and the top surface of the isolation layer 102 far from the initial bit line 124 are both exposed, before forming the insulating layer 126, the manufacturing method may further include: for the third region c (refer to Figure 1) The semiconductor layer 101 corresponding to the trench 103 (i.e., the second doped region III) is subjected to a second metallization process. It can be understood that if the subsequently formed second gate electrode layer is used as a reference, the semiconductor layer 101 above the top surface of the second gate electrode layer is subjected to the second metallization process to form a metal silicide layer 114. Among them, the material of the metal silicide layer 114 is also a metal-semiconductor compound, and the metal silicide layer 114 is a part of the second doped region III.

[0067] It should be noted that Figure 21 and Figure 22 The region of the second doped region III defined by the dashed line frame similar to the ellipse in is a metal-semiconductor compound.

[0068] Among them, the first metallization process and the second metallization process can be carried out in the same process step. That is, a metal layer (not shown in the figure) is formed on the surface jointly formed by the sacrificial film 115 and the semiconductor layer 101, that is, the metal layer is located at the bottom of the trench 103 and the top surface of the second doped region III; an annealing process is carried out to make the metal layer react with the semiconductor layer 101 to form a bit line 104 and a metal silicide layer 114; the remaining metal layer that has not reacted is removed. In other embodiments, the first metallization process and the second metallization process can also be carried out separately.

[0069] In the above embodiment, taking the material of the semiconductor layer 101 as silicon as an example, the material of the metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum, and the metal-semiconductor compound includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide. Compared with the unmetallized semiconductor material, the metal-semiconductor compound has a relatively smaller resistivity. Therefore, compared with the unmetallized semiconductor layer 101, the bit line 104 has a smaller resistivity, which is beneficial to reducing the resistance of the bit line 104 and reducing the contact resistance between the bit line 104 and the first doped region I, and further improving the electrical performance of the semiconductor structure.

[0070] In addition, since other conductive structures, such as a capacitor contact structure (not shown in the figure), are formed on the metal silicide layer 114 subsequently, the metal silicide layer 114 and the capacitor contact structure form an ohmic contact, avoiding the direct contact between the capacitor contact structure and the semiconductor material to form a Schottky barrier contact. The ohmic contact is beneficial to reducing the contact resistance between the second doped region III and the capacitor contact structure, thereby reducing the energy consumption during the operation of the semiconductor structure and improving the RC delay effect to improve the electrical performance of the semiconductor structure.

[0071] Refer to Figures 23 to 25 , a first insulating layer 106 filling the trench 103 is formed on the sacrificial film 115;

[0072] In some embodiments, with reference to Figures 17 to 19 and Figures 23 to 25 , when a first protective layer 160 is formed on both the top surface of the semiconductor layer 101 away from the initial bit line 124 and the top surface of the isolation layer 102 away from the initial bit line 124, the following process steps can be used to form the first insulating layer 106: perform a deposition process to form a first insulating film covering the top surface of the first protective layer 160, the top surface of the sacrificial film 115, and filling the trench 103; perform chemical mechanical planarization on the first insulating film, the first protective layer 160, and the sacrificial film 115 until the top surface of the second doped region III is exposed, and the remaining first insulating film serves as the first insulating layer 106.

[0073] In other embodiments, with reference to Figures 21 to 25 , when both the top surface of the semiconductor layer 101 away from the initial bit line 124 and the top surface of the isolation layer 102 away from the initial bit line 124 are exposed, the following process steps can be used to form the first insulating layer 106: perform a deposition process to form a first insulating film on the top surface of the second doped region III and filling the trench 103; perform chemical mechanical planarization on the first insulating film until the top surface of the second doped region III is exposed, and the remaining first insulating film serves as the first insulating layer 106.

[0074] In the above embodiments, the material of the first insulating film can be silicon oxide, silicon nitride, or silicon oxynitride. In addition, the material of the sacrificial film 115 can be different from the material of the first insulating film, which is convenient for subsequent etching of part of the sacrificial film 115 using the first insulating layer 106 as a mask. For example, the material of the sacrificial film 115 is silicon oxide, and the material of the first insulating layer 106 is silicon nitride.

[0075] With reference to Figures 23 to 25 and Figures 26 to 28 , remove the sacrificial film 115 on the inner wall of the trench 103 in the third region c, and the remaining sacrificial film 115 serves as the sacrificial layer 125, that is, the sacrificial layer 125 exposes part of the side walls of the second doped region III of the semiconductor layer 101.

[0076] Among them, when removing the sacrificial film 115 on the inner wall of the trench 103 in the third region c, the second thickness of the isolation layer 102 is also removed, and the remaining isolation layer 102 exposes part of the side walls of the semiconductor layer 101. It should be noted that in the direction Z (refer to Figure 1 ) perpendicular to the surface of the substrate 100 (refer to Figure 1 ), the second thickness is the height of the third region c, so the remaining isolation layer 102 exposes part of the side walls of the second doped region III, and the sacrificial layer 125 and the remaining isolation layer 102 together expose all the side walls of the second doped region III. In some embodiments, in the direction Z, the height of the second doped region III is 30 nm to 50 nm.

[0077] Wherein, a sacrificial film 115 on the inner wall of the trench 103 in the third region c is etched away by a wet etching process, and the wet etching process has the same etching rate for the isolation layer 102 and the sacrificial film 115. Thus, it is beneficial to expose all sidewalls of the second doped region III.

[0078] Reference Figures 29 to 31 , a second insulating layer 116 is formed on the inner wall of the trench 103 in the third region c (reference Figure 28 ), and the second insulating layer 116 is also located on the sidewall of the first insulating layer 106. The second insulating layer 116 and the first insulating layer 106 serve as the insulating layer 126.

[0079] Wherein, the second insulating layer 116 surrounds all sidewalls of the second doped region III. The second insulating layer 116 encloses a through hole, and the bottom of the through hole exposes the isolation layer 102, and the material of the second insulating layer 116 is different from that of the isolation layer 102. In addition, while surrounding the sidewall of the second doped region III, the second insulating layer 116 also covers the top surface of the sacrificial layer 125 and a part of the top surface of the isolation layer 102, and the through hole exposes a part of the top surface of the isolation layer 102.

[0080] In some embodiments, reference Figures 32 to 33 , forming the second insulating layer 116 includes the following process steps: forming an insulating film 136, the insulating film 136 filling the region between the inner wall of the trench 103 in the third region c (reference Figure 28 ) and the first insulating layer 106, and also located on the top surface of the remaining isolation layer 102 and the sidewall of the exposed semiconductor layer 101, and also located on the top surface of the semiconductor layer 101; back-etching the insulating film 136 to remove the insulating film 136 higher than the top surface of the semiconductor layer 101, and also removing at least a part of the insulating film 136 on the top surface of the isolation layer 102, and the remaining insulating film 136 serves as the second insulating layer 116. Among them, the insulating film 136 can be etched by a maskless dry etching process, and within the same etching time, the etching process etches the insulating film 136 with the same thickness in different regions, forming the second insulating layer 116 that surrounds all sidewalls of the second doped region III.

[0081] Combined with reference Figures 29 to 31 and Figures 34 to 36 , the sacrificial layer 125 in the second region b is removed, and a first thickness of the isolation layer 102 is removed to form a pore f surrounding the semiconductor layer 101, and the pore f exposes a part of the sidewall of the semiconductor layer.

[0082] Wherein, in the direction Z (reference Figure 1) Above, the first thickness is the height of the second region b. That is, the sacrificial layer 125 and the isolation layer 102 that surround the entire sidewall of the channel region II are removed, and the formed pore f exposes all the sidewalls of the channel region II. The remaining sacrificial layer 125 and isolation layer 102 surround the sidewall of the first doped region I. Since the second insulating layer 116 exposes a part of the top surface of the isolation layer 102, and the material of the insulating layer 126 is different from the materials of both the sacrificial layer 125 and the isolation layer 102, an etching solution can be injected at the position where the second insulating layer 116 exposes the isolation layer 102, and the sacrificial layer 125 and the isolation layer 102 with the first thickness in the second region b can be removed through a wet etching process.

[0083] In addition, the first insulating layer 106 and the second insulating layer 116 together form a support framework. The support framework is in contact connection with the second doped region III, and part of the support framework is embedded in the sacrificial layer 125. In the step of the wet etching process, on the one hand, the support framework plays a role in supporting and fixing the semiconductor layer 101. When the etching solution flows, it generates a squeezing force on the semiconductor layer 101, which is beneficial to avoiding the inclination or offset of the semiconductor layer 101 caused by extrusion, so as to improve the stability of the semiconductor structure; on the other hand, the support framework wraps the sidewall of the second doped region III, which is beneficial to avoiding damage to the second doped region III by the etching solution.

[0084] Refer to Figures 37 to 38 , a gate dielectric layer 107 is formed on the exposed sidewall of the semiconductor layer 101.

[0085] In some embodiments, since the material of the semiconductor layer 101 is silicon, the step of forming the gate dielectric layer 107 includes: performing a thermal oxidation treatment on the exposed sidewall of the channel region II to form the gate dielectric layer 107, and the gate dielectric layer 107 covers the sidewall surface of the remaining channel region II. Among them, the material of the gate dielectric layer 107 is silicon oxide. In other embodiments, the gate dielectric layer covering the sidewall surface of the channel region can also be formed by a deposition process.

[0086] Since the exposed sidewall of the channel region II is subjected to a thermal oxidation treatment, a part of the channel region II is converted into the gate dielectric layer 107, so that the positive projection of the channel region II on the substrate 100 (refer to Figure 1 ) is smaller than the positive projection of the second doped region III on the substrate 100, and smaller than the positive projection of the first doped region I on the substrate 100. This is beneficial to forming a channel region II with a smaller cross-sectional area in the cross-section perpendicular to the direction Z (refer to Figure 1 ) without using an etching process, which is beneficial to improving the control ability of the subsequently formed gate electrode layer over the channel region II, and thus it is easier to control the on or off of the GAA transistor. In some embodiments, in the direction Z, the height of the channel region II can be 30 nm to 50 nm.

[0087] Moreover, the orthographic projection of the periphery of the gate dielectric layer 107 on the substrate 100 is smaller than the orthographic projection of the periphery of the second insulating layer 116 on the substrate 100, that is, the outer wall of the gate dielectric layer 107 away from the semiconductor layer 101 is closer to the semiconductor layer 101 than the outer wall of the second insulating layer 116 away from the semiconductor layer 101, so as to ensure that there is a gap i between the gate dielectric layer 107 and the first insulating layer 106, enabling the subsequent gate electrode layer to surround the gate dielectric layer 107 located on the sidewall of the channel region II. In addition, the outer wall of the gate dielectric layer 107 away from the semiconductor layer 101 can also be closer to the semiconductor layer 101 than the outer wall of the isolation layer 102 away from the semiconductor layer 101.

[0088] In addition, since the top surface of the second doped region III is exposed, during the thermal oxidation process, a partial region near the top surface of the second doped region III will be converted into an insulating material layer 117. In some embodiments, the insulating material layer located on the top surface of the remaining second doped region can be removed in subsequent process steps. In other embodiments, the insulating material layer located on the top surface of the remaining second doped region can be removed after the thermal oxidation process.

[0089] Reference Figures 39 to 41 , a first gate electrode layer 118 is formed on a part of the gate dielectric layer 107, and the first gate electrode layer 118 also lies on the top surface of the remaining isolation layer 102; a second gate electrode layer 128 is formed on the remaining gate dielectric layer 107, the work function value of the second gate electrode layer 128 is different from the work function value of the first gate electrode layer 118, and the first gate electrode layer 118 and the second gate electrode layer 128 are stacked in the direction pointing from the first region a (reference Figure 1 ) to the third region c (reference Figure 1 ).

[0090] Among them, the step of forming the first gate electrode layer 118 may include: forming an initial gate electrode layer that fills the gap surrounded by the gate dielectric layer 107 and the insulating layer 126. Specifically, the initial gate electrode layer is located between the gate dielectric layer 107 and the first insulating layer 106, and between the gate dielectric layers 107 on the sidewalls of adjacent channel regions II on adjacent bit lines 104; removing the initial gate electrode layer corresponding to the third region c and a part of the second region b (reference Figure 1 ), and the remaining initial gate electrode layer serves as the first gate electrode layer 118. Among them, the initial gate electrode layer can be formed by a deposition process, and the material of the initial gate electrode layer includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, cobalt, aluminum, lanthanum, copper, or tungsten.

[0091] The initial gate electrode layer fills the gap surrounded by the gate dielectric layer 107 and the insulating layer 126 in a self-aligned manner, which is beneficial to forming a first gate electrode layer 118 with precise dimensions in a self-aligned manner. There is no need to design the dimensions of the first gate electrode layer 118 through an etching process, which is beneficial to simplifying the formation steps of the first gate electrode layer 118. Moreover, by adjusting the size of the gap, a small-sized first gate electrode layer 118 can be obtained.

[0092] In addition, the steps of forming the second gate electrode layer 128 are the same as those of forming the first gate electrode layer 118, which will not be elaborated here. The second gate electrode layer 128 and the first gate electrode layer 118 together constitute the gate electrode layer 108.

[0093] Since the work function value of the second gate electrode layer 128 is different from that of the first gate electrode layer 118, in the embodiments of the present application, by adjusting the work function values of the second gate electrode layer 128 and the first gate electrode layer 118, and the size ratio of the first gate electrode layer 118 relative to the second gate electrode layer 128, the work function value of the gate electrode layer 108 is reduced to reduce the difference between the work function value of the gate electrode layer 108 and the work function value of the semiconductor layer 101. On the one hand, it is beneficial to reduce the lateral electric field at the corresponding position of the gate electrode layer 108 and the semiconductor layer 101, reduce GIDL, and thus is beneficial to improving the on / off ratio of the channel region II to improve the sensitivity of controlling the on / off of the channel region II; on the other hand, it is beneficial to reduce the threshold voltage of the transistor while making the gate electrode layer 108 suitable for different types of transistors by adjusting the relevant parameters of the first gate electrode layer 118 and the second gate electrode layer 128, thereby being beneficial to reducing the preparation process of the semiconductor structure and the preparation cost.

[0094] Reference Figure 42 After forming the gate electrode layer 108, a first dielectric layer 109 is further formed, and the first dielectric layer 109 fills the void surrounded by the second insulating layer 116.

[0095] Among them, the first dielectric layer 109 can be formed by the following process steps: performing a deposition process to form a dielectric film covering the top surface of the insulating material layer 117 located on the top surface of the second doped region III and filling the void surrounded by the second insulating layer 116; performing chemical mechanical planarization on the dielectric film until the top surface of the insulating material layer 117 is exposed, and the remaining dielectric film serves as the first dielectric layer 109. Among them, the material of the dielectric film can be silicon nitride. In other embodiments, the dielectric film can also be chemically mechanically planarized until the top surface of the second doped region is exposed, that is, the insulating material layer located on the top surface of the second doped region is removed synchronously, and the remaining dielectric film serves as the dielectric layer.

[0096] In some embodiments, on the side of the first dielectric layer away from the substrate 100 (reference Figure 1) forms a capacitive contact structure and a capacitive structure (not shown in the figure) on its surface. In some embodiments, the insulating material layer 117 located on the top surface of the second doped region III is removed, a capacitive contact structure is formed on the top surface of the second doped region III, and a third insulating layer is formed between the capacitive contact structures located on the top surfaces of adjacent second doped regions III, and the third insulating layer exposes the top surface of the capacitive contact structure away from the second doped region III; a capacitive structure is formed on the top surface of the capacitive contact structure away from the second doped region III.

[0097] In other embodiments, after forming the gate electrode layer, a wet etching process can be used to remove the insulating layer to form a through hole exposing the gate electrode layer and the sacrificial layer; a deposition process is used to form a second dielectric layer filling the through hole. Since the second dielectric layer is an integral structure, the second dielectric layer has a higher density and fewer internal defects, which is beneficial to enhancing the isolation effect between the adjacent semiconductor layer and the adjacent bit lines. In some embodiments, the material of the second dielectric layer and the material of the first dielectric layer can be the same. In some examples, the materials of both the second dielectric layer and the first dielectric layer are silicon nitride.

[0098] In summary, in the direction from the first region a to the third region c, a first gate electrode layer 118 and a second gate electrode layer 128 are sequentially stacked on the gate dielectric layer 107, and the work function value of the second gate electrode layer 128 is different from the work function value of the first gate electrode layer 118. Thus, it is beneficial to reduce the difference between the work function value of the gate electrode layer 108 and the work function value of the semiconductor layer 101 by adjusting the relevant parameters of the second gate electrode layer 128 and the first gate electrode layer 118. On the one hand, it is beneficial to reduce GIDL to improve the on / off ratio of the channel region II; on the other hand, it is beneficial to reduce the threshold voltage of the transistor while making the gate electrode layer 108 applicable to different types of transistors, thereby facilitating the reduction of the manufacturing process of the semiconductor structure and the manufacturing cost.

[0099] Another embodiment of the present application further provides a manufacturing method of a semiconductor structure. The manufacturing method of this semiconductor structure is substantially the same as the previous embodiment, and the main differences include different process steps of removing the sacrificial layer and the first thickness of the isolation layer in the second region and forming the insulating layer. The following will detail the manufacturing method of the semiconductor structure provided by another embodiment of the present application with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as the previous embodiment, reference can be made to the detailed description of the previous embodiment and will not be repeated here.

[0100] Figures 43 to 48 are the structure schematic diagrams corresponding to the steps of the manufacturing method of the semiconductor structure provided by another embodiment of the present application. It should be noted that for the convenience of description and clearly showing the steps of the manufacturing method of the semiconductor structure, in this embodiment Figures 43 to 48They are all schematic diagrams of partial structures of semiconductor structures. Subsequently, according to the expression needs, one, two, or three of the schematic cross-sectional diagrams of the structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, the third cross-sectional direction CC1, and the fourth cross-sectional direction DD1 will be set.

[0101] In the embodiments of the present application, referring to Figures 43 to 45 , the steps of forming the semiconductor layer 201, the initial bit line 224, performing the first metallization process on the initial bit line 224 to form the bit line 204, and performing the second metallization process on the second doped region III to form the metal silicide layer 214 on the substrate are the same as those in the above embodiments and will not be elaborated here.

[0102] Continuing to refer to Figures 43 to 45 , before forming the insulating layer, forming the sacrificial layer 225 includes the following process steps:

[0103] Form a sacrificial film that covers the entire inner wall of the trench 203 and is also located on the top surface of the semiconductor layer 201. Among them, the step of forming the sacrificial film is the same as that in the above embodiments and will not be elaborated here.

[0104] Etch back the sacrificial film to etch away the sacrificial film located at the bottom of the trench 203, on the top surface of the semiconductor layer 201, and on the inner wall of the trench 203 in the third region c (refer to Figure 1 ), and the remaining sacrificial film serves as the sacrificial layer 225.

[0105] Continuing to refer to Figures 43 to 45 , in the process step of etching back the sacrificial film, the second thickness of the isolation layer 202 is also removed, and an opening g is formed between the adjacent semiconductor layer 201 and the remaining isolation layer 202. It should be noted that in the direction Z perpendicular to the substrate surface (refer to Figure 1 ), the second thickness is the height of the third region c, so that the sacrificial layer 225 and the remaining isolation layer 202 jointly expose all the side walls of the second doped region III.

[0106] After forming the sacrificial layer 225, referring to Figures 46 to 48 , the process steps of forming the insulating layer 226 include:

[0107] Form an insulating film that fills the trench 203 on the sacrificial layer 225, and the insulating film also fills the opening g (refer to Figure 45 ); remove at least part of the insulating film in the opening g to expose at least part of the top surface of the remaining isolation layer 202, and the remaining insulating film serves as the insulating layer 226. Among them, the step of forming the insulating film is the same as that in the above embodiments and will not be elaborated here.

[0108] Among them, since the insulating layer 226 is an integral structure, the insulating layer 226 has a high density and few internal defects, which is beneficial to enhancing the isolation effect between the adjacent semiconductor layers 201, the adjacent first gate electrode layer, and the adjacent second gate electrode layer.

[0109] It should be noted that Figure 47 and Figure 48 take the part of the top surface of the isolation layer 202 exposed by the insulating layer 226 as an example. In practical applications, the insulating layer can also expose the entire top surface of the isolation layer 202, as long as it is ensured that the insulating layer is located between the adjacent sacrificial layers in the trench for positioning when forming the first gate electrode layer and the second gate electrode layer subsequently.

[0110] In the embodiment of the present application, the steps of removing the sacrificial layer 225 in the second region b, removing the isolation layer 202 with the first thickness, forming the gate dielectric layer on the sidewall of the exposed semiconductor layer 201, forming the first gate electrode layer and the second gate electrode layer, and forming the first dielectric layer are the same as those in the above embodiment, and will not be elaborated here.

[0111] In addition, a capacitor contact structure and a capacitor structure can also be formed on the top surface of the second doped region III. Among them, the steps of forming the capacitor contact structure and the capacitor structure are the same as those in the above embodiment, and will not be elaborated here.

[0112] In summary, in the direction pointing from the first region a (refer to Figure 1 ) to the third region c (refer to Figure 1 ), the first gate electrode layer and the second gate electrode layer are sequentially stacked on the gate dielectric layer, and the work function value of the second gate electrode layer is different from that of the first gate electrode layer. In this way, it is beneficial to reduce the difference between the work function value of the gate electrode layer and the work function value of the semiconductor layer 201 by adjusting the relevant parameters of the second gate electrode layer and the first gate electrode layer. On the one hand, it is beneficial to reduce GIDL to improve the on / off ratio of the channel region II; on the other hand, it is beneficial to reduce the threshold voltage of the transistor while making the gate electrode layer applicable to different types of transistors, thereby facilitating the reduction of the manufacturing process of the semiconductor structure and the manufacturing cost.

[0113] Another embodiment of the present application further provides a manufacturing method of a semiconductor structure. The manufacturing method of this semiconductor structure is substantially the same as that of the previous embodiment, and the main differences include different process steps for removing the sacrificial layer in the second region and the isolation layer with the first thickness and forming the gate dielectric layer. The following will specifically describe the manufacturing method of the semiconductor structure provided by another embodiment of the present application with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference can be made to the detailed description of the foregoing embodiments, and will not be elaborated here.

[0114] Figures 49 to 54Structural schematic diagrams corresponding to the respective steps of the manufacturing method of the semiconductor structure provided in another embodiment of the present application. It should be noted that, for the convenience of description and to clearly illustrate the steps of the semiconductor structure manufacturing method, the Figures 49 to 54 are all partial structural schematic diagrams of the semiconductor structure. Subsequently, according to the expression needs, one, two, or three of the cross-sectional schematic diagrams along the first cross-sectional direction AA1 of the structure, the cross-sectional schematic diagram along the second cross-sectional direction BB1, the cross-sectional schematic diagram along the third cross-sectional direction CC1, and the cross-sectional schematic diagram along the fourth cross-sectional direction DD1 will be set.

[0115] In the embodiment of the present application, referring to Figures 49 to 51 , the steps of forming the semiconductor layer 301, the initial bit line 324, performing the first metallization process on the initial bit line 324 to form the bit line 304, performing the second metallization process on the second doped region III to form the metal silicide layer 314, and forming the first insulating layer 306 on the substrate are the same as those in the above embodiment and will not be elaborated here.

[0116] Continuing to refer to Figures 49 to 51 , in the process step of back-etching the sacrificial film, it further includes: removing the sacrificial layer 325 in the second region b (refer to Figure 1 ), and the remaining sacrificial layer 325 surrounds part of the sidewalls of the first doping I.

[0117] Among them, when removing the sacrificial layer 325 in the second region b, the first thickness of the isolation layer 302 is also removed to expose all the sidewalls of the channel region II and the second doped region III. Among them, in the direction Z (refer to Figure 1 ), the first thickness is the height of the second region b, that is, the sacrificial layer 325 and the isolation layer 302 surrounding the entire sidewall of the channel region II are removed, and the remaining sacrificial layer 325 and isolation layer 302 surround the sidewalls of the first doped region I.

[0118] Referring to Figures 52 to 54 , the process step of forming the gate dielectric layer includes: forming the third dielectric layer 317 on at least the inner walls of the trenches in the second region b (refer to Figure 1 ) and the third region c (refer to Figure 1 ), and the third dielectric layer 317 on the inner wall of the trench in the second region b serves as the gate dielectric layer.

[0119] In some embodiments, since the material of the semiconductor layer 301 is silicon, the step of forming the third dielectric layer 317 includes: performing a thermal oxidation process on the exposed sidewalls and the top surface of the channel region II and the second doped region III to form the third dielectric layer 317, and the third dielectric layer 317 covers the sidewall surfaces of the remaining channel region II and the remaining second doped region III. In other embodiments, the third dielectric layer covering the sidewalls of the channel region and the sidewalls and the top surface of the second doped region can also be formed by a deposition process.

[0120] Due to the thermal oxidation treatment of the exposed channel region II and the sidewalls of the second doped region III, a part of the channel region II and the second doped region III is converted into the third dielectric layer 317, such that the positive projections of the channel region II and the second doped region III on the bit line 304 are both smaller than the positive projection of the first doped region I on the bit line 304. This is conducive to forming a channel region II and a second doped region III with a smaller cross-sectional area in the cross-section in the Z direction without using an etching process, which is beneficial to reducing the threshold voltage of the transistor formed by the semiconductor layer 301, enabling the transistor to be turned on or off at a lower threshold voltage.

[0121] It should be noted that, in some embodiments, the third dielectric layer located on the top surface of the remaining second doped region can be removed in subsequent process steps; or, in other embodiments, the third dielectric layer located on the top surface of the remaining second doped region can be removed after the thermal oxidation treatment, and only the third dielectric layer covering the sidewall surfaces of the remaining channel region and the remaining second doped region is retained.

[0122] Continue to refer to Figures 52 to 54 , the gate electrode layer 308 and the second insulating layer 316 are formed. Among them, the steps of forming the gate electrode layer 308 and the second insulating layer 316 are the same as those in the above embodiments, and the first insulating layer 306 and the second insulating layer 316 together constitute the insulating layer 326, which will not be elaborated here. In addition, a capacitor contact structure and a capacitor structure can be formed on the top surface of the second doped region III. Among them, the steps of forming the capacitor contact structure and the capacitor structure are the same as those in the above embodiments, which will not be elaborated here.

[0123] In summary, in the direction from the first region a (refer to Figure 1 ) to the third region c (refer to Figure 1 ), the first gate electrode layer 318 and the second gate electrode layer 328 are sequentially stacked on the gate dielectric layer, and the work function value of the second gate electrode layer 328 is different from the work function value of the first gate electrode layer 318. Thus, it is beneficial to reduce the difference between the work function value of the gate electrode layer 308 and the work function value of the semiconductor layer 301 by adjusting the relevant parameters of the second gate electrode layer 328 and the first gate electrode layer 318. On the one hand, it is beneficial to reduce GIDL to improve the on / off ratio of the channel region II; on the other hand, it is beneficial to make the gate electrode layer 308 applicable to different types of transistors while reducing the threshold voltage of the transistor, thereby facilitating the reduction of the manufacturing process of the semiconductor structure and the manufacturing cost.

[0124] Another embodiment of the present application further provides a semiconductor structure, which can be prepared by the manufacturing method of the semiconductor structure provided by any of the above embodiments.

[0125] In some embodiments, refer toFigure 42 , the semiconductor structure includes: a substrate 100 (refer to Figure 1 ), the substrate 100 includes a plurality of spaced semiconductor layers 101 and isolation layers 102 located between adjacent semiconductor layers 101. Grooves 103 are formed in the semiconductor layers 101 and the isolation layers 102. The semiconductor layers 101 extend along a first direction X (refer to Figure 1 ), and the grooves 103 extend along a second direction Y (refer to Figure 1 ). The second direction Y is different from the first direction X. The groove 103 includes a first region a (refer to Figure 1 ), a second region b (refer to Figure 1 ), and a third region c (refer to Figure 1 ) that are sequentially distributed in a direction from the bottom of the groove 103 to the top of the groove 103; a sacrificial layer 125, the sacrificial layer 125 is located on the inner wall of the groove 103 in the first region a; a gate dielectric layer 107, a first gate electrode layer 118, and a second gate electrode layer 128. The first gate electrode layer 118 and the second gate electrode layer 128 are both located on the gate dielectric layer 107 and are jointly located in the groove 103 in the second region b and surround the semiconductor layer 101. Moreover, the first gate electrode layer 118 is also located on the top surface of the isolation layer 102. The second gate electrode layer 128 and the first gate electrode layer 118 are stacked in a direction from the first region a to the third region c, and the work function value of the second gate electrode layer 128 is different from the work function value of the first gate electrode layer 118; an insulating layer 126, the insulating layer 126 is located in the groove 103 and isolates two opposite gate electrode layers 108 located in the same groove 103. The insulating layer 126 also fills the groove 103 in the third region c.

[0126] Wherein, the insulating layer 126 can be jointly constituted by a first insulating layer 106 and a second insulating layer 116. The first insulating layer 106 fills the gap between adjacent isolation layers 102, and the top surface of the first insulating layer 106 is not lower than the top surface of the second doped region III. The second insulating layer 116 is on the inner wall of the groove 103 in the third region c and the side wall of the first insulating layer 106; alternatively, the insulating layer 126 is an integral structure. The insulating layer 126 fills the gap between adjacent isolation layers 102 and the gap between adjacent semiconductor layers 101, and the top surface of the insulating layer 126 is not lower than the top surface of the second doped region III.

[0127] Refer to Figures 52 to 54 , the mutual relationship among the semiconductor layer 301, the isolation layer 302, the sacrificial layer 325, the gate dielectric layer, the first gate electrode layer 318, the second gate electrode layer 328, and the insulating layer 326 in the semiconductor structure is the same as that in the above embodiment, and will not be elaborated here.

[0128] Wherein, the semiconductor structure has a third dielectric layer 317, and the third dielectric layer 317 is at least located in the second region b (refer to Figure 1 ) and the third region c (refer toFigure 1 ) of the inner wall of the trench, and the third dielectric layer 317 on the inner wall of the trench located in the second region b serves as the gate dielectric layer.

[0129] In the above two embodiments, the first gate electrode layer and the second gate electrode layer together form the gate electrode layer, and the top surface of the isolation layer directly below the first gate electrode layer is flush with the top surface of the sacrificial layer. In this way, on the one hand, it is beneficial to improve the insulation effect between the structure composed of the isolation layer and the sacrificial layer and the first doped region and the adjacent bit line; on the other hand, it is beneficial to improve the accuracy of the size of the gate electrode layer to improve the control ability of the gate electrode layer over the channel region.

[0130] Among them, the semiconductor structure may further include: a bit line extending along the first direction X, the bit line is located at the bottom of the trench and directly below the bottom of the adjacent trench, and the material of the bit line is a metal semiconductor compound. Compared with the unmetallized semiconductor material, the metal semiconductor compound has a relatively smaller resistivity. Therefore, compared with the unmetallized semiconductor layer, the resistivity of the bit line is smaller, which is beneficial to reducing the resistance of the bit line and reducing the contact resistance between the bit line and the first doped region, and further improving the electrical performance of the semiconductor structure. Among them, the metal semiconductor compound may be at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.

[0131] In addition, the semiconductor structure may further include: a metal silicide layer, which is located in the second doped region, and the top surface of the metal silicide layer is the top surface of the second doped region that has not been second-metallized. Since other conductive structures, such as capacitor contact structures, will be formed on the metal silicide layer subsequently, an ohmic contact is formed between the metal silicide layer and the capacitor contact structure, avoiding the formation of a Schottky barrier contact between the capacitor contact structure and the semiconductor material directly. The ohmic contact is beneficial to reducing the contact resistance between the second doped region III and the capacitor contact structure, thereby reducing the energy consumption during the operation of the semiconductor structure and improving the RC delay effect to improve the electrical performance of the semiconductor structure.

[0132] Again, the semiconductor structure may further include: a capacitor contact structure and a capacitor structure, the capacitor contact structure is located on the surface formed by the first dielectric layer and the insulating layer together, or on the surface formed by the third dielectric layer and the insulating layer together, and the capacitor structure is located on the side of the capacitor contact structure away from the substrate.

[0133] In summary, since the first gate electrode layer and the second gate electrode layer together constitute the gate electrode layer, and the work function value of the second gate electrode layer is different from that of the first gate electrode layer, thus, it is beneficial to adjust the relevant parameters of the second gate electrode layer and the first gate electrode layer to reduce the difference between the work function value of the gate electrode layer and the work function value of the semiconductor layer. On the one hand, it is beneficial to reduce GIDL to improve the on / off ratio of the channel region II and improve the electrical performance of the semiconductor structure; on the other hand, it is beneficial to reduce the threshold voltage of the transistor while making the gate electrode layer applicable to different types of transistors, thereby facilitating the reduction of the manufacturing process of the semiconductor structure and the manufacturing cost.

[0134] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, a substrate is provided, the substrate includes a plurality of semiconductor layers arranged at intervals and isolation layers located between adjacent semiconductor layers, trenches are formed in the semiconductor layers and the isolation layers, the semiconductor layers extend in a first direction, the trenches extend in a second direction, and the trenches are arranged at intervals in the first direction, the second direction is different from the first direction, and the trenches include a first region, a second region, and a third region sequentially distributed in a direction from the bottom of the trench to the top of the trench; a sacrificial layer is formed on the inner wall of the trench in the first region and the second region; an insulating layer filling the trench is formed on the surface of the sacrificial layer, and at least part of the surface of the isolation layer is also exposed by the insulating layer; the sacrificial layer in the second region is removed, and a first thickness of the isolation layer is removed to form a pore surrounding the semiconductor layer, and part of the side wall of the semiconductor layer is exposed by the pore; a gate dielectric layer is formed on the exposed side wall of the semiconductor layer; a first gate electrode layer is formed on part of the gate dielectric layer, and the first gate electrode layer is also located on the top surface of the remaining isolation layer; a second gate electrode layer is formed on the remaining gate dielectric layer, the work function value of the second gate electrode layer is different from the work function value of the first gate electrode layer, and the first gate electrode layer and the second gate electrode layer are stacked in a direction from the first region to the third region.

2. The manufacturing method according to claim 1, characterized in that, the process steps of forming the sacrificial layer and the insulating layer include: forming a sacrificial film, the sacrificial film is located on the entire inner wall of the trench; forming a first insulating layer filling the trench on the sacrificial film; removing the sacrificial film on the inner wall of the trench in the third region, and the remaining sacrificial film serves as the sacrificial layer; forming a second insulating layer on the inner wall of the trench in the third region, and the second insulating layer is also located on the side wall of the first insulating layer, and the second insulating layer and the first insulating layer serve as the insulating layer.

3. The manufacturing method according to claim 2, characterized in that, while removing the sacrificial film on the inner wall of the trench in the third region, a second thickness of the isolation layer is also removed, and part of the side wall of the semiconductor layer is exposed by the remaining isolation layer; in the process steps of forming the second insulating layer, the second insulating layer is also located on the side wall of the semiconductor layer exposed by the remaining isolation layer.

4. The manufacturing method according to claim 3, characterized in that, a wet etching process is used to etch and remove the sacrificial film on the inner wall of the trench in the third region, and the wet etching process has the same etching rate for the isolation layer and the sacrificial film.

5. The manufacturing method according to claim 2, characterized in that, The process steps for forming the second insulating layer include: forming an insulating film, which fills the region between the inner wall of the trench in the third region and the first insulating layer, and is also located on the top surface of the remaining isolation layer and the side walls of the exposed semiconductor layer, and is also located on the top surface of the semiconductor layer; performing a re-etch on the insulating film to remove the insulating film above the top surface of the semiconductor layer, and also removing at least part of the insulating film on the top surface of the isolation layer, with the remaining insulating film serving as the second insulating layer.

6. The manufacturing method according to claim 1, wherein, the process steps for forming the sacrificial layer include: forming a sacrificial film, which covers the entire inner wall of the trench, and is also located on the top surface of the semiconductor layer; performing a re-etch on the sacrificial film to etch and remove the sacrificial film located at the bottom of the trench, the top surface of the semiconductor layer, and the inner wall of the trench in the third region, with the remaining sacrificial film serving as the sacrificial layer.

7. The manufacturing method according to claim 6, wherein, in the process step of re-etching the sacrificial film, at least a second thickness of the isolation layer is also removed, and an opening is formed between the adjacent semiconductor layer and the remaining isolation layer; the process steps for forming the insulating layer include: forming an insulating film that fills the trench on the sacrificial layer, and the insulating film also fills the opening; removing at least part of the insulating film within the opening to expose at least part of the top surface of the remaining isolation layer, with the remaining insulating film and the first insulating layer serving as the insulating layer.

8. The manufacturing method according to claim 6, wherein, in the process step of re-etching the sacrificial film, it further includes: removing the sacrificial layer in the second region; the process steps for forming the gate dielectric layer include: forming a dielectric layer at least on the inner wall of the trench in the second region and the third region, and the dielectric layer on the inner wall of the trench in the second region serves as the gate dielectric layer.

9. The manufacturing method according to claim 1, wherein, before forming the insulating layer, it further includes: performing a first metallization process on the semiconductor layer below the bottom of the trench to convert part of the thickness of the semiconductor layer into bit lines, and the bit lines extend along the first direction, and the material of the bit lines is a metal semiconductor compound.

10. The manufacturing method according to claim 9, wherein, the process steps for forming the sacrificial layer include: forming a sacrificial film on all inner walls of the trench; the first metallization process includes: forming a metal layer on the surface of the sacrificial film, and the metal layer is also located at the bottom of the trench; performing an annealing process to cause the metal layer to react with the semiconductor layer to form the bit lines; removing the remaining unreacted metal layer.

11. The manufacturing method according to claim 9, wherein, it further includes: after forming the sacrificial layer, performing a second metallization process on the semiconductor layer above the top surface of the second gate electrode layer to form a metal silicide layer.

12. The manufacturing method according to claim 11, wherein, The first metallization process and the second metallization process are carried out in the same process step.

13. A semiconductor structure, characterized in that, comprising: a substrate, the substrate includes a plurality of spaced semiconductor layers and isolation layers located between adjacent semiconductor layers, the semiconductor layers and the isolation layers have trenches, the semiconductor layers extend in a first direction, the trenches extend in a second direction, the second direction is different from the first direction, and the trenches include a first region, a second region, and a third region sequentially distributed in a direction from the bottom of the trench to the top of the trench; a sacrificial layer, the sacrificial layer is located on the inner wall of the trench in the first region; a gate dielectric layer, a first gate electrode layer, and a second gate electrode layer, the first gate electrode layer and the second gate electrode layer are both located on the gate dielectric layer and are jointly located in the trench in the second region and surround the semiconductor layer, and the first gate electrode layer is also located on the top surface of the isolation layer, the second gate electrode layer and the first gate electrode layer are stacked in a direction from the first region to the third region, and the work function value of the second gate electrode layer is different from the work function value of the first gate electrode layer; an insulating layer, the insulating layer is located in the trench and isolates two opposite gate electrode layers in the same trench, and the insulating layer is also located in the trench filling the third region.

14. The semiconductor structure according to claim 13, characterized in that, the top surface of the isolation layer directly below the first gate electrode layer is flush with the top surface of the sacrificial layer.

15. The semiconductor structure according to claim 13, characterized in that, further comprising: a bit line extending in the first direction, the bit line is located at the bottom of the trench and directly below the bottom of adjacent trenches, and the material of the bit line is a metal semiconductor compound.

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