Semiconductor element, packaging structure of semiconductor element, and packaging method thereof
By optimizing the mesh size of the shallow trench isolation layer in the solder pad area, the delamination problem between the solder pad and the redistribution layer during the packaging process was solved, resulting in more stable electrical connections and improved product performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA WAFER LEVEL CSP
- Filing Date
- 2022-11-22
- Publication Date
- 2026-05-12
AI Technical Summary
During the packaging process of semiconductor components, the design of shallow trench isolation layers can cause delamination at the electrical connection between the solder pads and subsequent redistribution layers, affecting product performance.
The mesh size of the shallow trench isolation layer in the area where the solder pads are located is designed to be 2.29μm~2.49μm to avoid delamination during silicon via etching and to ensure stable electrical connection between the solder pads and the redistribution layer.
By optimizing the mesh size of the shallow trench isolation layer, delamination was avoided, improving the stability of the packaging structure and product performance.
Smart Images
Figure CN115939157B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor element, a packaging structure for the semiconductor element, and a packaging method for the packaging structure of the semiconductor element. Background Technology
[0002] In current technology, CMOS image sensors (CIS) are developing towards high speed, large pixels, and low cost, while wafer-level packaging technology has received widespread attention in recent years due to its advantages of miniaturization and low cost. CIS can be divided into three structures: front-side illuminated (FSI), back-side illuminated (BSI), and stacked.
[0003] A stacked CIS includes a stack wafer, and shallow trench isolation is used in 3D stack wafers. Shallow trench isolation (STI) is typically used in processes below 0.25µm. It is achieved by depositing, patterning, and etching silicon using a silicon nitride mask to form trenches, which are then filled with deposited oxides for isolation from silicon.
[0004] During the packaging stage, the low-k material (dielectric layer) in the metal pads of a stack wafer is extremely fragile, posing a significant challenge to packaging. To meet the needs of emerging CIS wafer-level packaging, vertical through-hole (VB) packaging technology is often employed. This technology can satisfy the packaging requirements of chips with more I / Os, higher reliability requirements, and more complex metal pad structures.
[0005] However, in actual packaging, due to the design of STI, delamination was found at the STI area after etching the vias. (Refer to...) Figure 1 As shown, a is a through-silicon via (TSV), b is a shallow trench isolation layer, c is the metal layer of the solder pad, and h is the delamination gap. This prevents the subsequently formed metal conductive leads (rewiring layers) from achieving a good electrical connection with the pads, thus reducing product performance.
[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0007] The purpose of this invention is to provide a semiconductor element, a semiconductor element packaging structure, and a packaging method for the semiconductor element packaging structure, which can solve the problem of STI (shallow trench isolation) delamination during subsequent packaging processes due to the presence of STI.
[0008] To achieve the above objectives, embodiments of the present invention provide a semiconductor device including a substrate, a functional structure formed within the substrate, and bonding pads connected to the functional structure. The functional structure includes a shallow trench isolation layer with a mesh structure. The shallow trench isolation layer does not extend to the bonding pads, or the shallow trench isolation layer extends to the bonding pads and is part of the bonding pads. The mesh of the shallow trench isolation layer satisfies the following condition: the mesh width ranges from 2.29 μm to 2.49 μm.
[0009] In one or more embodiments of the present invention, the mesh size of the shallow trench isolation layer satisfies the following conditions: the mesh depth ranges from 0.2 μm to 0.4 μm, and the mesh spacing is from 2.76 μm to 2.96 μm.
[0010] In one or more embodiments of the present invention, the shallow trench isolation layer does not extend to the bonding pad; the functional structure further includes a polysilicon layer that does not extend to the bonding pad.
[0011] In one or more embodiments of the present invention, the shallow trench isolation layer extends to and is part of the solder pad; the functional structure further includes a polysilicon layer that extends to and is part of the solder pad, and the polysilicon layer is formed on the shallow trench isolation layer.
[0012] In one or more embodiments of the present invention, the polysilicon layer includes a plurality of polysilicon units arranged in an array, each of the polysilicon units being formed on the mesh gaps of the shallow trench isolation layer.
[0013] In one or more embodiments of the present invention, the pad includes a metal layer, the metal layer including multiple sub-metal layers spaced apart, and adjacent sub-metal layers are electrically connected.
[0014] In one or more embodiments of the present invention, a dielectric layer is disposed between adjacent sub-metal layers.
[0015] In one or more embodiments of the present invention, a metal plug is formed within the dielectric layer, and an electrical connection is formed between adjacent sub-metal layers through the metal plug.
[0016] In one or more embodiments of the present invention, the shallow trench isolation layer extends to the solder pad, and the mesh of the shallow trench isolation layer satisfies the following conditions: width of 2.39 μm, depth of 0.3 μm, and mesh spacing of 2.86 μm.
[0017] An embodiment of the present invention also provides a semiconductor device packaging structure, including: a semiconductor device as described above, solder bumps disposed on the surface of the semiconductor device, and a redistribution layer; a through-hole is formed in the semiconductor device, the through-hole exposes the solder pad, and the redistribution layer is electrically connected between the solder bumps and the solder pad through the through-hole.
[0018] An embodiment of the present invention also provides a packaging method for a semiconductor element packaging structure, comprising: providing a wafer having a plurality of semiconductor elements arranged in an array; forming a through-hole extending to the bonding pad from the surface of the semiconductor element; forming a passivation layer on the sidewall of the through-hole and on the surface of the semiconductor element; forming a redistribution layer covering the sidewall of the through-hole, the bottom wall and the surface of the semiconductor element; and forming solder bumps electrically connected to the redistribution layer on the redistribution layer.
[0019] Compared with the prior art, the semiconductor device of the present invention does not have a shallow trench isolation layer and a polysilicon layer in the area where the solder pad is located, which makes the structure simpler and avoids delamination when etching silicon vias.
[0020] The semiconductor device of the present invention has a shallow trench isolation layer with a width of 2.29μm to 2.49μm in the area where the solder pads are located. This design can prevent delamination during the etching of silicon vias, and there is no delamination at the electrical connection between the solder pads and the subsequent redistribution layer. The overall packaging structure is stable and the product performance is significantly improved. Attached Figure Description
[0021] Figure 1 This is an image of a semiconductor device after etching a through-silicon via (TSV).
[0022] Figure 2 This is a schematic diagram of the structure of a semiconductor element according to one embodiment of the present invention;
[0023] Figure 3 In Example 1 Figure 2 Enlarged diagram of some details;
[0024] Figure 4 yes Figure 3 A top view of the shallow trench isolation layer in the middle;
[0025] Figure 5 This is an image of the semiconductor device of Embodiment 1 of the present invention after etching a silicon via;
[0026] Figure 6 In Example 2 Figure 2 Enlarged diagram of some details;
[0027] Figure 7 This is an image of the semiconductor device after etching a silicon via in Embodiment 2 of the present invention;
[0028] Figure 8 This is a schematic diagram of the packaging structure of a semiconductor element according to an embodiment of the present invention;
[0029] Figure 9 This is a schematic flowchart of a packaging method for a semiconductor device packaging structure according to an embodiment of the present invention;
[0030] Figures 10-12 This is a schematic diagram of the packaging method of a semiconductor device packaging structure according to an embodiment of the present invention. Detailed Implementation
[0031] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.
[0032] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.
[0033] CMOS image sensors (CIS) can be divided into three structures: front-side illuminated (FSI), back-side illuminated (BSI), and stacked.
[0034] The substrate of a BSI photosensitive unit is not entirely a light-receiving area; a considerable area is a circuit board. If the circuit board could be removed, the light-receiving area would increase significantly. Therefore, the new design places the circuit board under the light-receiving area, forming a stacked structure. This design is called stacked.
[0035] Stacked CIS (CMOS Image Sensor) can significantly increase the light-receiving area of each unit. A larger area means more light reception, resulting in a stronger input signal. However, manufacturers prefer to use this technology to increase pixel count because even with smaller photosensitive units, the light-receiving area remains constant, meaning image quality doesn't decrease. More photosensitive units can be placed on the same sensor size, increasing pixel density and total pixel count. The first stacked image sensor achieved a total of 13 million pixels, with a significant improvement in image quality. Structurally, stacked CIS is also a type of back-illuminated sensor.
[0036] As mentioned in the background section, a stacked CIS includes a stack wafer, and shallow trench isolation (STI) technology is used in 3D stacked wafers. During the packaging stage, due to the STI design, delamination was observed at the STI locations after etching through-holes to expose the pads. (See reference...) Figure 1 As shown, a is a through-silicon via (TSV), b is a shallow trench isolation layer, c is the metal layer of the solder pad, and h is the delamination gap. This prevents the subsequently formed metal conductive leads (rewiring layers) from achieving a good electrical connection with the pads, thus reducing product performance.
[0037] To address the aforementioned technical problems, this invention creatively proposes a semiconductor element that avoids delamination during via etching by either not setting a shallow trench isolation layer in the area where the solder pads are located or designing the size of the shallow trench isolation layer in the area where the solder pads are located. This ensures that there is no delamination at the electrical connection between the solder pads and the subsequent redistribution layer, resulting in a stable overall packaging structure and significantly improved product performance.
[0038] Example 1
[0039] like Figure 2 and Figure 3 As shown, in Embodiment 1, the present invention provides a semiconductor element 100, including a substrate 10, a functional structure 20 formed in the substrate 10, and a bonding pad 30 connected to the functional structure 20.
[0040] The functional structure 20 includes a shallow trench isolation layer 21 with a mesh structure, a polysilicon layer 22 formed on one side of the shallow trench isolation layer 21, and an insulating layer 23 formed on one side of the polysilicon layer 22. Of course, the functional structure 20 also includes other layer structures that can realize the functions of the semiconductor element 100, such as pn junction diode layers, etc. Since these are not innovative points of this application, they will not be described in detail here. The distribution of these layer structures and their structural relationship with the shallow trench isolation layer 21, polysilicon layer 22, and insulating layer 23 in this invention can be referenced from existing layer structures within the semiconductor element 100 that can realize certain functions, such as the functional structures within a stack wafer used to fabricate a CMOS image sensor.
[0041] In this embodiment, the shallow trench isolation layer 21 extends to and is part of the solder pad 30, such as Figure 3 As shown. The mesh size of the shallow trench isolation layer 21 satisfies the following condition: the mesh width ranges from 2.29 μm to 2.49 μm. The polysilicon layer 22 also extends to and is part of the pad 30, and the polysilicon layer 22 is formed on the shallow trench isolation layer 21.
[0042] Specifically, the substrate 10 includes a first region A, which is the region where the pad 30 is located and the region that the pad 30 can vertically cover in the thickness direction of the semiconductor element 100. The shallow trench isolation layer 21 extends into the first region A, and the mesh size of the shallow trench isolation layer 21 located in the first region A satisfies the following conditions: the mesh width ranges from 2.29 μm to 2.49 μm, the mesh depth ranges from 0.2 μm to 0.4 μm, and the mesh spacing ranges from 2.76 μm to 2.96 μm.
[0043] In one exemplary embodiment, the polysilicon layer 22 includes a plurality of polysilicon units 221 arranged in an array, each polysilicon unit 221 being formed on the mesh gaps of the shallow trench isolation layer 21.
[0044] An insulating layer 23 is formed on a polysilicon layer 22. The insulating layer 23 can be made of silicon dioxide. A mask layer 24 can also be disposed between the insulating layer 23 and the polysilicon layer 22. The mask layer 24 can be made of silicon nitride.
[0045] The bonding pad 30 includes a metal layer 31, a dielectric layer 32, and a metal plug 33. The metal layer 31 includes multiple sub-metal layers 311 spaced apart, with a dielectric layer 32 disposed between adjacent sub-metal layers 311. A metal plug 33 is formed within the dielectric layer 32, and adjacent sub-metal layers 311 are electrically connected through the metal plug 33. Similarly, the polysilicon layer 22 and the metal layer 31 are electrically connected through the metal plug 33. The dielectric layer 32 can be made of a Low-k material.
[0046] In one exemplary implementation, such as Figure 4 As shown, the shallow trench isolation layer 21 extends to the bonding pad 30, and the mesh size of the shallow trench isolation layer 21 satisfies the following requirements: width of 2.39 μm, depth of 0.3 μm, and mesh spacing of 2.86 μm. In this semiconductor device 100 design, after the vias are formed by etching during the packaging process, no delamination occurs between the shallow trench isolation layer 21 and the metal layer 31 of the bonding pad 30. (Refer to...) Figure 5 As shown.
[0047] Compared with the prior art, the semiconductor device of the present invention has a shallow trench isolation layer with a width of 2.29μm to 2.49μm in the area where the solder pads are located. This design allows for the avoidance of delamination during the etching of through-silicon vias in the subsequent packaging process. Figure 5 As shown, there is no delamination at the electrical connection between the solder pads and the subsequent redistribution layer, the overall package structure is stable, and the product performance is significantly improved.
[0048] 2 were implemented
[0049] like Figure 2 and 6As shown, in Embodiment 2, the present invention provides a semiconductor element 100, including a substrate 10, a functional structure 20 formed in the substrate 10, and a bonding pad 30 connected to the functional structure 20.
[0050] The functional structure 20 includes a shallow trench isolation layer 21 with a mesh structure, a polysilicon layer 22 formed on one side of the shallow trench isolation layer 21, and an insulating layer 23 formed on one side of the polysilicon layer 22. Of course, the functional structure 20 also includes other layer structures that can realize the functions of the semiconductor device 100, such as pn junction diode layers, etc. Since these are not innovative points of this application, they will not be described in detail here. The distribution of these layer structures and their structural relationship with the shallow trench isolation layer 21, polysilicon layer 22, and insulating layer 23 in this invention can be referenced to the layer structures within existing functional structures within the semiconductor device 100 that can realize certain functions, such as the functional structures within a stack wafer used to fabricate a CMOS image sensor. The polysilicon layer 22 includes a plurality of polysilicon units 221 arranged in an array, each polysilicon unit 221 being formed on the mesh gaps of the shallow trench isolation layer 21.
[0051] In this embodiment, the shallow trench isolation layer 21 does not extend to the solder pad 30. Similarly, the polysilicon layer 22 does not extend to the solder pad 30. Figure 6 As shown. Specifically, the substrate 10 includes a first region A, which is the region where the bonding pad 30 is located and the region that the bonding pad 30 can vertically cover in the thickness direction of the semiconductor element 100. The shallow trench isolation layer 21 does not extend into the first region A, and the polysilicon layer 22 does not extend into the first region A.
[0052] An insulating layer 23 is formed on a polycrystalline silicon layer 22. The insulating layer 23 can be made of silicon dioxide and extends into the first region A.
[0053] The bonding pad 30 includes a metal layer 31, a dielectric layer 32, and a metal plug 33. The metal layer 31 includes multiple spaced sub-metal layers 311, with a dielectric layer 32 disposed between adjacent sub-metal layers 311. A metal plug 33 is formed within the dielectric layer 32, and adjacent sub-metal layers 311 are electrically connected through the metal plug 33. Within the first region A, the metal plug 33 also penetrates the insulating layer 23 and contacts the substrate 10. The dielectric layer 32 can be made of a Low-k material.
[0054] In this semiconductor device 100 design, during the packaging process, after the vias are formed by etching, there is no delamination between the redistribution layer formed by the vias and the metal layer 31 of the solder pad 30. (Refer to...) Figure 7 As shown.
[0055] Compared with the prior art, the semiconductor device of the present invention does not have a shallow trench isolation layer and a polysilicon layer in the area where the solder pads are located, making the structure simpler. This also allows for the avoidance of delamination during subsequent packaging processes, such as etching through-silicon vias. Figure 7 As shown, there is no delamination at the electrical connection between the solder pads and the subsequent redistribution layer, the overall package structure is stable, and the product performance is significantly improved.
[0056] like Figure 8 As shown, the present invention also provides a packaging structure for the above-mentioned semiconductor element, including: the semiconductor element 100 as described above, solder bumps 200, redistribution layer 300, passivation layer 400 and sealing layer 500 disposed on the surface of the semiconductor element 100.
[0057] The semiconductor element 100 includes a first surface 101 and a second surface 102 disposed opposite to each other. The functional structure 20 and the bonding pad 30 are formed on the first surface 101.
[0058] A through-hole 103 is formed on the second surface 102 of the semiconductor element 100 toward the first surface 101. The through-hole 103 exposes the solder pad 30.
[0059] A passivation layer 400 is formed on the sidewall of the via 103 and on the second surface 102 of the semiconductor element 100. The passivation layer 400 serves as an electrical insulating layer of the redistribution layer 300. In this embodiment, the passivation layer 400 is an inorganic dielectric material such as oxide or nitride, such as silicon oxide, silicon nitride, or silicon oxynitride, or a stack thereof. As an insulating layer, the passivation layer 400 has good stepped coverage and good coverage at the corners of the via, avoiding defects caused by weak corners of the via.
[0060] A redistribution layer 300 is formed on the inner wall of the via 103 and extends to the passivation layer 400 of the second surface 102 of the semiconductor element 100. Solder bumps 200 are disposed on the redistribution layer 300 of the second surface 102, and the redistribution layer 300 is electrically connected between the solder bumps 200 and the solder pads 30. The material of the redistribution layer 300 is a conductive material, which can be a metallic material, such as aluminum, copper, or gold.
[0061] The sealing layer 500 is disposed on the surface of the redistribution layer 300 and acts as an insulating protective layer for other layers during the solder bump 200 process. The sealing layer 500 can be, for example, a solder resist photosensitive ink.
[0062] Figure 9 This is a schematic flowchart of a packaging method for a semiconductor device packaging structure according to an embodiment of the present invention. Figures 10-12 This is a schematic diagram illustrating the steps of a packaging method for a semiconductor device packaging structure according to an embodiment of the present invention. The following is in conjunction with... Figures 9 to 12The packaging method of the semiconductor element packaging structure of the present invention will be described in detail.
[0063] Step s1: Provide a wafer having multiple semiconductor devices 100 arranged in an array, the cross-sectional structure of the semiconductor devices 100 being... Figure 2 As shown, dicing channels are provided between adjacent semiconductor elements 100 for subsequent wafer dicing to form independent packaging structures. Figure 7 As shown;
[0064] Step s2, a protective cover plate 120 is provided, and the protective cover plate 120 is pressed and mated with the first surface 101 of the semiconductor element 100, such as... Figure 10 As shown.
[0065] Step s3: Through-silicon via (TSV) process is used to form a through-hole 103 extending from the second surface 102 of the semiconductor device 100 to the bonding pad 30. Specifically, etching techniques such as reactive ion etching or inductively coupled plasma etching can be used to etch the semiconductor device 100 until the bonding pad 30 is exposed.
[0066] Step s4, a passivation layer 400 is formed on the sidewall of the via 103 and on the second surface 102 of the semiconductor element 100, such as Figure 11 As shown.
[0067] Step s5, forming a redistribution layer 300 covering the inner wall and bottom wall of the via 103 and the second surface 102 of the semiconductor element 100.
[0068] Step s6: Form a capping layer 500, and form an opening in the capping layer 500 to expose the redistribution layer 300. Then, form solder bumps 200 that are electrically connected to the redistribution layer 300 within the opening, such as... Figure 12 As shown.
[0069] Step s7: Peel off the protective cover 120 and perform a dicing process, dicing the wafer along the dicing grooves to cut the wafer into individual package structures, such as... Figure 8 As shown.
[0070] All aspects, embodiments, features, and examples of this invention are to be regarded as illustrative in all respects and are not intended to limit the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and uses will become apparent to those skilled in the art without departing from the spirit and scope of the invention as claimed.
[0071] The use of headings and sections in this application is not intended to limit the invention; each section can be applied to any aspect, embodiment or feature of the invention.
[0072] Throughout this application, wherever a composition is described as having, containing, or including specific components, or wherever a process is described as having, containing, or including specific process steps, it is contemplated that the compositions taught in this invention are also substantially composed of or comprised of the described components, and that the processes taught in this invention are also substantially composed of or comprised of the described process steps.
[0073] In this application, where an element or component is referred to as being included in and / or selected from the list of described elements or components, it should be understood that the element or component may be any of the described elements or components and may be freely selected from a group consisting of two or more of the described elements or components. Furthermore, it should be understood that the elements and / or features of the compositions, devices, or methods described herein may be combined in various ways, whether expressly stated or implied, without departing from the spirit and scope of the teachings of this invention.
[0074] Unless otherwise specifically stated, the use of the terms “comprising” or “having” should generally be understood as open-ended and non-restrictive.
[0075] Unless otherwise specifically stated, the use of the singular herein includes the plural (and vice versa). Furthermore, unless the context clearly indicates otherwise, the singular forms “a” and “said” include the plural forms. Additionally, where the term “about” precedes a quantity, the teachings of this invention also include the specific quantity itself, unless otherwise specifically stated.
[0076] It should be understood that the order of the steps or the order in which specific actions are performed is not particularly important, as long as the teachings of this invention remain operable. Furthermore, two or more steps or actions can be performed simultaneously.
[0077] It should be understood that the figures and descriptions of this invention have been simplified to illustrate elements relevant to a clear understanding of the invention, and other elements have been omitted for clarity. However, those skilled in the art will recognize that these and other elements may be desirable. However, since such elements are well-known in the art and do not contribute to a better understanding of the invention, a discussion of such elements is not provided herein. It should be understood that the figures are presented for illustrative purposes and are not intended as construction diagrams. Omitted details and modifications or alternative embodiments are within the scope of those skilled in the art.
[0078] It will be understood that, in certain aspects of the invention, a single component may be replaced by multiple components and multiple components may be replaced by a single component to provide an element or structure or to perform one or more given functions. This substitution is considered to be within the scope of the invention, except where such substitution would not be operational in practice of a particular embodiment of the invention.
[0079] Although the invention has been described with reference to illustrative embodiments, those skilled in the art will understand that various other changes, omissions, and / or additions can be made without departing from the spirit and scope of the invention, and that elements of the embodiments can be substituted with substantially equivalents. Furthermore, many modifications can be made without departing from the scope of the invention to adapt particular situations or materials to the teachings of the invention. Therefore, this invention is not intended to be limited to the specific embodiments disclosed for carrying out the invention, but rather is intended to encompass all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated otherwise, any use of the terms first, second, etc., does not indicate any order or importance, but is used to distinguish one element from another.
Claims
1. A semiconductor element, characterized in that, The device includes a substrate, a functional structure formed within the substrate, and a bonding pad connected to the functional structure. The bonding pad and the functional structure are disposed without overlapping in the thickness direction of the substrate. The functional structure includes a shallow trench isolation layer with a mesh structure. The shallow trench isolation layer extends to the bonding pad and is part of the bonding pad. The mesh of the shallow trench isolation layer satisfies the following condition: the mesh width ranges from 2.29 μm to 2.49 μm.
2. The semiconductor device as claimed in claim 1, characterized in that, The mesh size of the shallow trench isolation layer meets the following requirements: the mesh depth ranges from 0.2μm to 0.4μm, and the mesh spacing ranges from 2.76μm to 2.96μm.
3. The semiconductor device as claimed in claim 1, characterized in that, The functional structure further includes a polysilicon layer that extends to and is part of the pads, and the polysilicon layer is formed on the shallow trench isolation layer.
4. The semiconductor device as described in claim 3, characterized in that, The polysilicon layer includes a plurality of polysilicon units arranged in an array, each polysilicon unit being formed on the mesh gaps of the shallow trench isolation layer.
5. The semiconductor device as claimed in claim 3, characterized in that, The pad includes a metal layer, which comprises multiple sub-metal layers spaced apart, and adjacent sub-metal layers are electrically connected.
6. The semiconductor device as claimed in claim 5, characterized in that, A dielectric layer is disposed between adjacent sub-metal layers.
7. The semiconductor device as claimed in claim 6, characterized in that, A metal plug is formed within the dielectric layer, and an electrical connection is formed between adjacent sub-metal layers through the metal plug.
8. The semiconductor device as claimed in claim 1, characterized in that, The mesh size of the shallow trench isolation layer has the following characteristics: width of 2.39 μm, depth of 0.3 μm, and mesh spacing of 2.86 μm.
9. A packaging structure for a semiconductor device, characterized in that, include: The semiconductor device as described in any one of claims 1 to 8 includes a solder bump and a redistribution layer disposed on the surface of the semiconductor device; a via is formed in the semiconductor device, the via exposing the solder pad, and the redistribution layer is electrically connected between the solder bump and the solder pad through the via.
10. A packaging method for a semiconductor device packaging structure, characterized in that, include: Provide a wafer having a plurality of semiconductor elements arranged in an array as described in any one of claims 1 to 8; A through-hole is formed from the surface of the semiconductor element to the bonding pad; A passivation layer is formed on the sidewall of the via and on the surface of the semiconductor element; A redistribution layer is formed covering the sidewalls and bottom wall of the via and the surface of the semiconductor element; Solder bumps that are electrically connected to the redistribution layer are formed on the redistribution layer.