A semiconductor device having a high-K metal gate structure and a manufacturing method thereof

Abstract

The present invention provides a semiconductor device with a high-K metal gate structure and a manufacturing method thereof, including the following steps: providing a semiconductor layer including a gate dielectric layer, a bottom barrier layer, and a gate sidewall, the bottom barrier layer being located on the gate dielectric layer to enclose a receiving space with a top opening, and the bottom wall and sidewall of the receiving space forming a corner; forming a P-type work function metal sidewall at the corner; forming a P-type work function layer covering the P-type work function metal sidewall on the bottom wall and sidewall of the receiving space; sequentially forming an N-type work function layer, a top barrier layer, and a metal layer in the receiving space, the N-type work function layer covering the P-type work function layer and being spaced from the metal layer by the top barrier layer. This method can effectively improve the aluminum diffusion effect in the N-type work function layer, and improve the performance stability, product yield, and reliability evaluation of the device. The present invention also provides a semiconductor device with a high-K metal gate structure, and this device has good performance stability and reliability.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit manufacturing, and relates to a semiconductor device with a high-K metal gate structure and a manufacturing method thereof. Background Art

[0002] The main semiconductor device of integrated circuits, especially very large scale integrated circuits, is the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET for short). With the continuous development of integrated circuit manufacturing technology, the semiconductor device technology node is continuously reduced, and the geometric size of semiconductor devices is continuously reduced following Moore's law. When the size of semiconductor devices is reduced to a certain extent, various secondary effects caused by the physical limits of semiconductor devices emerge one after another, and it becomes increasingly difficult to reduce the characteristic size of semiconductor devices proportionally. Among them, in the field of semiconductor manufacturing, the most challenging is how to solve the problem of large leakage current in semiconductor devices. The large leakage current in semiconductor devices is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer.

[0003] With the development of semiconductor technology, in the gate structure of semiconductor devices with high process nodes, high-K materials are usually used to replace the traditional silicon dioxide material as the gate dielectric layer, and metal is used as the gate electrode, and a High-K Metal Gate (HKMG for short) structure is formed by superposition to avoid the Fermi level pinning effect and boron penetration effect between the high-K material and the traditional gate electrode material, thereby reducing the leakage current of semiconductor devices. In HKMG, a work function layer needs to be used. For N-type semiconductor devices, an N-type work function layer such as TiAl is used. The work function of the N-type work function layer is close to the conduction band of the semiconductor substrate such as a silicon substrate, which is beneficial to reducing the threshold voltage of N-type semiconductor devices; for P-type semiconductor devices, a P-type work function layer such as TiN is used. The work function of the P-type work function layer is close to the valence band of the semiconductor substrate such as a silicon substrate, which is beneficial to reducing the threshold voltage of P-type semiconductor devices, that is, the absolute value of the threshold voltage.

[0004] Please refer to Figure 1 , which shows a schematic cross-sectional structure diagram of a semiconductor device with a high-K metal gate structure in the prior art. During the formation of the existing P-type work function layer (titanium nitride layer), the deposition process behavior of titanium nitride will cause corners in the titanium nitride layer 1. If the subsequent layers deposited on this layer contain Al, in the subsequent production process, a high-temperature process environment will cause the occurrence of an aluminum diffusion effect, that is, the Al element in the other structural layers deposited on the titanium nitride layer will be like Figure 1The diffusion along the arrow at the corner as shown in the figure into the structural layer (such as the dielectric layer 2) under the titanium nitride layer 1 causes a serious drift in the effective work function of the dielectric layer, an abnormal increase in the threshold voltage of the PMOS device, a reduction in the control ability of the device, a serious decline in the electrical performance of the device, and even yield loss of the product and related reliability evaluation.

[0005] Therefore, how to provide a semiconductor device with a high-K metal gate structure and a manufacturing method thereof to improve the structure of the weak corner generated during the deposition of titanium nitride in the traditional P-type work function, thereby avoiding the possible aluminum diffusion effect to stabilize the performance of the P-type device, improve the product yield and related reliability evaluation has become an important technical problem urgently to be solved by those skilled in the art.

[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor device with a high-K metal gate structure and a manufacturing method thereof, which are used to solve the problem that in the prior art, after the formation of the P-type work function layer, the weak corner is formed. If Al is included in the layer deposited thereon and other layers, in the subsequent production process, the high-temperature process environment may cause the occurrence of the aluminum diffusion effect, thereby affecting the performance of the P-type device, and even causing yield loss of the product and related reliability evaluation.

[0008] To achieve the above purpose and other related purposes, the present invention provides a manufacturing method of a semiconductor device with a high-K metal gate structure, including the following steps:

[0009] Provide a semiconductor layer, the semiconductor layer includes a gate dielectric layer, a bottom barrier layer, and gate sidewalls. The bottom barrier layer is located on the gate dielectric layer, the gate sidewalls are located on both sides of the gate dielectric layer and the bottom barrier layer. The bottom barrier layer encloses a receiving space with an open top, and the bottom wall and side walls of the receiving space form a corner;

[0010] Form a P-type work function metal sidewall at the corner;

[0011] Form a P-type work function layer covering the P-type work function metal sidewall on the bottom wall and side walls of the receiving space;

[0012] Form an N-type work function layer, a top barrier layer, and a metal layer in the accommodation space in sequence. The N-type work function layer covers the P-type work function layer, and the top barrier layer is interposed between the N-type work function layer and the metal layer.

[0013] Optionally, the method for forming the P-type work function metal sidewall includes: depositing a P-type work function metal conformal layer in the accommodation space, and etching back the P-type work function metal conformal layer until a part of the sidewall and a part of the bottom wall of the accommodation space are exposed, and the remaining P-type work function metal conformal layer in the accommodation space constitutes the P-type work function metal sidewall.

[0014] Optionally, the gate dielectric layer includes a stacked interface layer and a high-K dielectric layer, and the high-K dielectric layer is located above the interface layer.

[0015] Optionally, the material of the interface layer includes at least one of SiO2 and SiON; the material of the high-K dielectric layer includes at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3.

[0016] Optionally, the bottom barrier layer includes a stacked first bottom barrier layer and a second bottom barrier layer, the second bottom barrier layer is located above the first bottom barrier layer, and the accommodation space is located within the second bottom barrier layer.

[0017] Optionally, the material of the first bottom barrier layer includes at least one of TiN and TaN, and the material of the second bottom barrier layer includes at least one of TiN and TaN.

[0018] Optionally, the material of the P-type work function layer includes at least one of TiN and TaN; the material of the N-type work function layer includes at least one of TiAl, TiAlC, TiAlN, and AlN; the material of the P-type work function metal sidewall includes at least one of TiN and TaN; the material of the metal layer includes at least one of Al, Cu, Ag, W, and Ni; the gate sidewall structure includes a single-layer or stacked structure, and the material of the gate sidewall includes at least one of SiO2, SiN, and SiON.

[0019] Optionally, the exposed surface of the P-type work function metal sidewall is a convex surface.

[0020] The present invention also provides a semiconductor device having a high-K metal gate structure, including:

[0021] A semiconductor layer, including a gate dielectric layer, a bottom barrier layer, and gate sidewalls. The bottom barrier layer is located on the gate dielectric layer. The gate sidewalls are located on both sides of the gate dielectric layer and the bottom barrier layer. The bottom barrier layer encloses a receiving space with an open top. The bottom wall and sidewalls of the receiving space form a corner.

[0022] A P-type work function metal sidewall is located at the corner.

[0023] A P-type work function layer is located on the bottom wall and sidewalls of the receiving space and covers the P-type work function metal sidewall.

[0024] An N-type work function layer is located within the receiving space and covers the P-type work function layer.

[0025] A top barrier layer is located within the receiving space and covers the N-type work function layer.

[0026] A metal layer is located within the receiving space and covers the top barrier layer.

[0027] Optionally, the surface of the P-type work function metal sidewall facing the P-type work function layer is a convex surface.

[0028] As described above, in the manufacturing method of the semiconductor device with a high-K metal gate structure of the present invention, by forming the P-type work function metal sidewall before forming the P-type work function layer, the structural morphology of the P-type work function layer is changed, compensating for the structural defect of the weak corner generated due to the deposition behavior of the P-type work function material during the formation process of the traditional P-type work function layer, effectively avoiding the aluminum diffusion effect that occurs in the subsequent N-type work function layer under subsequent high-temperature process conditions. Thus, while improving the performance stability and reliability of the device, the product yield is significantly improved. In the semiconductor device with a high-K metal gate structure of the present invention, due to the P-type work function metal sidewall structure provided in the structure, the aluminum diffusion effect occurring under high-temperature conditions is effectively avoided, and the device has excellent performance stability and use reliability. Description of the Drawings

[0029] Figure 1 It shows a schematic cross-sectional structure diagram of a semiconductor device with a high-K metal gate structure in the prior art.

[0030] Figure 2 It shows a flowchart of the steps of the manufacturing method of the semiconductor device with a high-K metal gate structure of the present invention.

[0031] Figure 3 It shows a schematic cross-sectional diagram of the structure obtained after performing step S1 in the manufacturing method of the semiconductor device with a high-K metal gate structure of the present invention.

[0032] Figure 4Schematic cross-sectional view of the structure obtained after performing step S2 in the semiconductor device with a high-K metal gate structure and its manufacturing method according to the present invention.

[0033] Figure 5 Schematic cross-sectional view of the structure obtained after performing step S3 in the semiconductor device with a high-K metal gate structure and its manufacturing method according to the present invention.

[0034] Figure 6 Schematic cross-sectional view of the structure obtained after performing step S4 in the manufacturing method of the semiconductor device with a high-K metal gate structure according to the present invention.

[0035] Description of component labels

[0036] 1 Titanium nitride layer

[0037] 2 Dielectric layer

[0038] 3 Gate dielectric layer

[0039] 31 Interface layer

[0040] 32 High-K dielectric layer

[0041] 4 Bottom barrier layer

[0042] 41 First bottom barrier layer

[0043] 42 Second bottom barrier layer

[0044] 5 Gate sidewall

[0045] 6 Receiving space

[0046] 7 Corner

[0047] 8 P-type work function metal sidewall

[0048] 9 P-type work function layer

[0049] 10 N-type work function layer

[0050] 11 Top barrier layer

[0051] 12 Metal layer

[0052] Steps S1 to S4 Detailed implementation manners

[0053] The following illustrates the implementation manners of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please refer to Figures 2 to 6 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0055] Embodiment 1

[0056] This embodiment provides a method for manufacturing a semiconductor device with a high-K metal gate structure. Please refer to Figure 2 , which is shown as a flowchart of the steps of this method, including steps S1 to S4.

[0057] First, please refer to Figure 3 , and perform step S1 to provide a semiconductor layer. The semiconductor layer includes a gate dielectric layer 3, a bottom barrier layer 4, and gate sidewalls 5. The bottom barrier layer 4 is located on the gate dielectric layer 3. The gate sidewalls 5 are located on both sides of the gate dielectric layer 3 and the bottom barrier layer 4. The bottom barrier layer 4 encloses a receiving space 6 with an open top. The bottom wall and side walls of the receiving space 6 form a corner 7.

[0058] As an example, the semiconductor layer further includes a substrate layer (not labeled in the figure). The gate dielectric layer 2 is located above the substrate layer. The material of the substrate layer includes at least one of Si, Ge, SiGe, SiC, and GaIn. The substrate layer can also be a Si substrate or a Ge substrate on insulator.

[0059] As an example, the method for forming the receiving space 6 includes the following steps: forming a polysilicon gate, the polysilicon gate including a polysilicon layer and gate sidewalls 5 on the side of the polysilicon layer; removing at least a part of the polysilicon layer to form a groove; sequentially forming the gate dielectric layer 3 and the bottom barrier layer 4 from bottom to top at the bottom of the groove; etching at least a part of the bottom barrier layer 4 to form the receiving space 6.

[0060] As an example, the gate dielectric layer 3 includes a stacked interface layer 31 and a high-K dielectric layer 32. The high-K dielectric layer 32 is located above the interface layer 31.

[0061] As an example, the material of the interface layer 31 includes at least one of SiO2 and SiON. The functions of the interface layer 31 include the following two aspects. The interface layer 31 can form a stacked structure with the subsequent high-K dielectric layer 32, and this stacked structure constitutes the gate dielectric layer 3. The interface layer 31 also provides a good interface foundation for the subsequent formation of the high-K dielectric layer 32 to improve the quality of the formation of the high-K dielectric layer 32, reduce the interface state density between the high-K dielectric layer 32 and the substrate layer, and avoid the adverse effects caused by the direct contact between the high-K dielectric layer 32 and the substrate layer. The thickness of the interface layer 31 needs to be reasonably set based on actual needs and meet the structural and performance requirements of the device. The interface layer 31 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or oxidation process. In this embodiment, it is preferably formed by thermal oxidation process to improve the interface performance between the interface layer 31 and the high-K dielectric layer 32.

[0062] As an example, the material of the high-K dielectric layer 32 includes HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2 or Al2O3. The high-K dielectric layer 32 can also use other high-K dielectric materials, and high-K dielectric materials refer to gate dielectric materials with a relative dielectric constant greater than that of silicon oxide. The high-K dielectric layer 32 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In addition, the thickness range of the high-K dielectric layer 32 is 5 to 15 angstroms.

[0063] As an example, the bottom barrier layer 4 includes a stacked first bottom barrier layer 41 and a second bottom barrier layer 42. The second bottom barrier layer 42 is located above the first bottom barrier layer 41, and the accommodation space 6 is located within the second bottom barrier layer 42.

[0064] As an example, the material of the first bottom barrier layer 41 includes at least one of TiN and TaN, and the material of the second bottom barrier layer 42 includes at least one of TiN and TaN. The material of the second bottom barrier layer 42 can be the same as or different from the material of the first bottom barrier layer 41. In this embodiment, it is preferably that the materials of the two are different. Among them, the material of the first bottom barrier layer 41 is TiN, and the material of the second bottom barrier layer 42 is TaN. The functions of the first bottom barrier layer 41 and the second bottom barrier layer 42 are that when the P-type work function layer 9 is formed in the opening subsequently, the metal ions in the P-type work function layer 9 may diffuse into the high-K dielectric layer 32 at high temperature, playing a protective role for the high-K dielectric layer 32 to keep the high-K dielectric layer 32 in good performance. The second bottom barrier layer 42 can also prevent metal ions from diffusing into the gate sidewall 5, ensuring that the work function value of the P-type work function layer 9 is not affected.

[0065] As an example, the gate sidewall 5 structure includes a single-layer or stacked structure, and the material of the gate sidewall 5 includes at least one of SiO2, SiN, and SiON. In this embodiment, the gate sidewall is a stacked structure.

[0066] Please refer to Figure 4 , and perform step S2 to form a P-type work function metal sidewall 8 at the corner 7. The function of the P-type work function metal sidewall is to prevent, when the subsequent P-type work function layer 9 is formed, the weakening at the corner 7 caused by the self-deposition characteristics of the material of the P-type work function layer 9, so that the easily diffused ions in the P-type work function layer diffuse into the high-K dielectric layer 32 under high-temperature conditions, resulting in damage to the device performance. Among them, the specifications of the P-type work function metal sidewall 8 are reasonably set based on the actual situation.

[0067] As an example, the exposed surface of the P-type work function metal sidewall 8 is a convex surface. In practical applications, the morphology of the P-type work function metal sidewall 8 is not limited to the foregoing morphology, and can be a convex morphology, a concave morphology, or a flat morphology. As long as the morphology of the P-type work function metal sidewall 8 can make up for the structural defects at the corner weak points generated when depositing the P-type work function layer in the prior art, so that the thickness of the P-type work function layer in the corner area is not less than the thickness of the P-type work function layer in the non-corner area, and the occurrence of the aluminum diffusion effect can be avoided. In this embodiment, the convex morphology is preferably used.

[0068] As an example, the method for forming the P-type work function metal sidewall 8 includes: depositing a P-type work function metal conformal layer (not marked in the figure) in the receiving space 6, and etching back the P-type work function metal conformal layer until a part of the sidewall and a part of the bottom wall of the receiving space 6 are exposed. The remaining P-type work function metal conformal layer in the receiving space 6 constitutes the P-type work function metal sidewall 8. The etching method includes anisotropic etching or other suitable etching methods.

[0069] Please refer to Figure 5 , and perform step S3 to form a P-type work function layer 9 covering the P-type work function metal sidewall 8 on the bottom wall and sidewall of the receiving space 6.

[0070] As an example, the method for forming the P-type work function layer 9 includes at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition; the material of the P-type work function layer 9 includes at least one of TiN and TaN. The P-type work function layer 9 is used to adjust the threshold voltage of the transistor. The thickness of the P-type work function layer 9 should be appropriate, meeting the requirements for the threshold voltage and not having an adverse effect on the threshold voltage. The material of the P-type work function layer 9 and the material of the P-type work function metal sidewall 8 can be the same or different. In this embodiment, it is preferably that the two materials are the same, both being TiN. When the two materials are the same, the interface between the P-type work function layer 9 and the P-type work function metal sidewall 8 is more tightly bonded, reducing the adverse effect on the device performance caused by the generation of interface defects. In addition, the thickness range of the P-type work function layer 9 is 10 - 20 angstroms.

[0071] Please refer to Figure 6 , perform step S4, and sequentially form an N-type work function layer 10, a top barrier layer 11, and a metal layer 12 in the accommodation space 6. The N-type work function layer 10 covers the P-type work function layer 9, and the N-type work function layer 10 and the metal layer 12 are separated by the top barrier layer 11.

[0072] As an example, the method for forming the N-type work function layer 10 includes at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition; the material of the N-type work function layer 10 includes at least one of TiAl, TiAlC, TiAlN, and AlN. In this embodiment, the material of the N-type work function layer 10 is preferably TiAl. In addition, the thickness range of the N-type work function layer 10 is 30 - 80 angstroms.

[0073] As an example, the material of the top barrier layer 11 includes at least one of TiN and TaN. The thickness range of the top barrier layer 11 is 15 - 40 angstroms, including but not limited to 20 angstroms, 25 angstroms, 30 angstroms, and 35 angstroms. The top barrier layer 11 can prevent the easily diffused ions in the metal layer 12 from diffusing into the N-type work function layer 10, reducing the work function value and causing the threshold voltage of the formed semiconductor device to drop. The top barrier layer 11 can also improve the formation quality of the subsequent metal layer 12 and the adhesion of the metal layer 12 in the opening. The thickness of the top barrier layer 11 should be appropriate. Too low a thickness will result in too poor a blocking effect of the top barrier layer 11, while too large a thickness will be unfavorable for the formation of the metal layer 12 and easily cause an increase in the resistance value of the high-K metal gate structure, thereby having an adverse effect on the electrical performance. In this embodiment, the material of the top barrier layer 11 is preferably TiN.

[0074] As an example, the material of the metal layer 12 includes at least one of Al, Cu, Ag, W, and Ni. In this embodiment, the material of the metal layer 12 is Al, and the metal layer 12 can reduce the resistance value of the high-K metal gate. The metal layer 12 can fill the remaining accommodation space 6, or can be not filled according to actual production needs to facilitate the formation of other subsequent structural layers.

[0075] As an example, the method for manufacturing a semiconductor device with a high-K metal gate structure further includes a chemical mechanical polishing step, which is performed after the formation of the metal layer 12 to make the tops of the layers deposited in the opening flush to improve the performance of the device.

[0076] In the method for manufacturing a semiconductor device with a high-K metal gate structure according to this embodiment, by forming the P-type work function metal sidewall before forming the P-type work function layer, the structural morphology of the P-type work function layer is changed, compensating for the structural defect of the corner weakness caused by the deposition behavior of the P-type work function material during the formation of the traditional P-type work function layer, effectively avoiding the aluminum diffusion effect that occurs in the subsequently formed N-type work function layer under subsequent high-temperature process conditions. Therefore, while improving the performance stability and reliability of the device, the product yield is significantly improved.

[0077] Embodiment 2

[0078] This embodiment provides a semiconductor device with a high-K metal gate structure, which can be manufactured by using the method for manufacturing a semiconductor device with a high-K metal gate structure described in Embodiment 1 or other suitable methods. Please refer to Figure 6 , which shows a cross-sectional schematic diagram of the semiconductor device with a high-K metal gate structure of this embodiment, including a semiconductor layer, a P-type work function metal sidewall 8, a P-type work function layer 9, an N-type work function layer 10, a top barrier layer 11, and a metal layer 12. Among them, the semiconductor layer includes a gate dielectric layer 3, a bottom barrier layer 4, and a gate sidewall 5. The bottom barrier layer 4 is located on the gate dielectric layer 3, and the gate sidewall 5 is located on both sides of the gate dielectric layer 3 and the bottom barrier layer 4. The bottom barrier layer 4 encloses an accommodation space 6 with an open top. The bottom wall and side walls of the accommodation space 6 form a corner 7; the P-type work function metal sidewall 8 is located at the corner 7; the P-type work function layer 9 is located on the bottom wall and side walls of the accommodation space 6 and covers the P-type work function metal sidewall 8; the N-type work function layer 10 is located in the accommodation space 6 and covers the P-type work function layer 9; the top barrier layer 11 is located in the accommodation space 6 and covers the N-type work function layer 10; the metal layer 12 is located in the accommodation space 6 and covers the top barrier layer 11.

[0079] As an example, the surface of the P-type work function metal sidewall 8 facing the P-type work function layer 9 is a convex surface. The setting of the P-type work function metal sidewall 8 can effectively prevent the easily diffusible ions (such as Al ions) in the N-type work function layer 10 on the P-type work function layer 9 from diffusing into the gate dielectric layer 3 through the weak point of the corner 7, thereby achieving the technical effect of stabilizing the performance of the device, the product yield and the subsequent reliability evaluation.

[0080] It should be noted that the relevant parameters and functions of each structure in this embodiment are consistent with those in the first embodiment, and no further explanation is given here.

[0081] The semiconductor device with a high-K metal gate structure of this embodiment effectively avoids the aluminum diffusion effect occurring under high temperature conditions due to the P-type work function metal sidewall structure provided in the structure, and has excellent device performance stability and reliability.

[0082] In summary, the method for manufacturing a semiconductor device with a high-K metal gate structure of the present invention changes the structural morphology of the P-type work function layer by first forming a P-type work function metal sidewall before forming the P-type work function layer, making up for the structural defects of weak corners caused by the deposition behavior of the P-type work function material in the traditional P-type work function layer formation process, and effectively avoiding the aluminum diffusion effect of the subsequently formed N-type work function layer under subsequent high-temperature process conditions, thereby significantly improving the product yield while improving the performance stability and reliability of the device. The semiconductor device with a high-K metal gate structure of the present invention effectively avoids the aluminum diffusion effect under high temperature conditions because the P-type work function metal sidewall structure is provided in the structure, and has excellent device performance stability and reliability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a semiconductor device with a high-K metal gate structure, characterized in that, Including the following steps: Providing a semiconductor layer including a gate dielectric layer, a bottom barrier layer, and gate sidewalls, the bottom barrier layer being located on the gate dielectric layer, the gate sidewalls being located on both sides of the gate dielectric layer and the bottom barrier layer, the bottom barrier layer enclosing a receiving space with a top opening, and the bottom wall and sidewalls of the receiving space forming corners; Forming a P-type work function metal sidewall at the corners; Forming a P-type work function layer covering the P-type work function metal sidewall on the bottom wall and sidewalls of the receiving space; Successively forming an N-type work function layer, a top barrier layer, and a metal layer in the receiving space, the N-type work function layer covering the P-type work function layer, and the N-type work function layer and the metal layer being spaced apart by the top barrier layer.

2. The manufacturing method of a semiconductor device having a high-K metal gate structure according to claim 1, characterized in that, The method for forming the P-type work function metal sidewall includes: depositing a P-type work function metal conformal layer in the receiving space and etching back the P-type work function metal conformal layer until a part of the sidewall and a part of the bottom wall of the receiving space are exposed, and the remaining P-type work function metal conformal layer in the receiving space constitutes the P-type work function metal sidewall.

3. The manufacturing method of the semiconductor device with a high-K metal gate structure according to claim 1, wherein: The gate dielectric layer includes a stacked interface layer and a high-k dielectric layer, and the high-k dielectric layer is located above the interface layer.

4. The manufacturing method of a semiconductor device having a high-K metal gate structure according to claim 3, characterized in that: The material of the interface layer includes at least one of SiO2 and SiON; the material of the high-k dielectric layer includes at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3.

5. The manufacturing method of the semiconductor device with a high-K metal gate structure according to claim 1, characterized in that: The bottom barrier layer includes a stacked first bottom barrier layer and a second bottom barrier layer, the second bottom barrier layer being located above the first bottom barrier layer, and the receiving space being located within the second bottom barrier layer.

6. The manufacturing method of a semiconductor device having a high-K metal gate structure according to claim 5, characterized in that: The material of the first bottom barrier layer includes at least one of TiN and TaN, and the material of the second bottom barrier layer includes at least one of TiN and TaN.

7. The manufacturing method of a semiconductor device with a high-K metal gate structure according to claim 1, characterized in that: The material of the P-type work function layer includes at least one of TiN and TaN; the material of the N-type work function layer includes at least one of TiAl, TiAlC, TiAlN, and AlN; the material of the P-type work function metal sidewall includes at least one of TiN and TaN; the material of the metal layer includes at least one of Al, Cu, Ag, W, and Ni; the gate sidewall structure includes a single-layer or stacked structure, and the material of the gate sidewall includes at least one of SiO2, SiN, and SiON.

8. The manufacturing method of a semiconductor device having a high-K metal gate structure according to claim 1, wherein: The exposed surface of the P-type work function metal sidewall is a convex surface.

9. A semiconductor device having a high-K metal gate structure, characterized in that, Including: A semiconductor layer including a gate dielectric layer, a bottom barrier layer, and gate sidewalls, the bottom barrier layer being located on the gate dielectric layer, the gate sidewalls being located on both sides of the gate dielectric layer and the bottom barrier layer, the bottom barrier layer enclosing a receiving space with a top opening, and the bottom wall and sidewalls of the receiving space forming corners; A P-type work function metal sidewall located at the corners; A P-type work function layer located on the bottom wall and sidewalls of the receiving space and covering the P-type work function metal sidewall; An N-type work function layer, located within the accommodation space and covering the P-type work function layer; A top barrier layer, located within the accommodation space and covering the N-type work function layer; A metal layer, located within the accommodation space and covering the top barrier layer.

10. A semiconductor device having a high-K metal gate structure according to claim 9, characterized in that: The surface of the P-type work function metal sidewall facing the P-type work function layer is a convex surface.

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