Level shifter

Abstract

A level shifter includes a prelevel shifter and a selector coupled to the prelevel shifter. The prelevel shifter shifts an input digital voltage to a first digital voltage and a second digital voltage. As the level of the input digital voltage changes, the levels of the first digital voltage and the second digital voltage change sequentially. The selector selects and outputs the first digital voltage, wherein the level of the first digital voltage changes earlier than the level of the second digital voltage.

Description

Technical Field

[0001] This invention relates to a driving technology, and more particularly to a level shifter that can quickly shift and output voltage levels without increasing quiescent current. Background Technology

[0002] Circuits with multiple functions can be integrated into a single integrated circuit. Circuits may use different power supply voltages, requiring interface circuits to change the voltage level of signals transmitted between circuits. Such interface circuits are called level shifters.

[0003] Figure 1 This is a schematic diagram of a level shifter in the prior art. Figure 2 This section presents waveforms of the input voltage, output node signal, and output voltage for a prior art level shifter. Please refer to... Figure 1 and Figure 2The level shifter 100 includes a first P-channel MOSFET 110, a second P-channel MOSFET 111, a third P-channel MOSFET 112, a fourth P-channel MOSFET 113, a first N-channel MOSFET 114, a second N-channel MOSFET 115, a fifth P-channel MOSFET 116, a sixth P-channel MOSFET 117, a third N-channel MOSFET 118, a fourth N-channel MOSFET 119, a first current source 120, a second current source 121, and two inverters 122. VH represents a high logic level H, and VL represents a low logic level L. Because the first P-channel MOSFET 110, the second P-channel MOSFET 111, the third P-channel MOSFET 112, and the fourth P-channel MOSFET 113 operate like a latch after being interconnected, their operation is slow. The first N-channel MOSFET 114 and the second N-channel MOSFET 115 receive input voltages IN and INB, respectively. Input voltages IN and INB are digital voltages with opposite phase. When the input voltage IN rises from a low logic level L' to a high logic level H', the voltage at node a is quickly pulled low. Therefore, the sixth P-channel MOSFET 117 turns on, pulling the voltage at node d to a high logic level H. Next, inverter 122 can quickly output a high logic level H as the output voltage OUT. When the input voltage IN drops from a high logic level H' to a low logic level L', the second P-channel MOSFET 111 and the third P-channel MOSFET 112 slowly pull the voltage at node a to a high voltage. Therefore, the voltage at node d is pulled to a low logic level L after a delay. Then, inverter 122 slowly outputs the output voltage OUT as a low logic level L. In other words, when the input voltage IN drops from a high logic level H' to a low logic level L', the output voltage OUT requires a relatively long propagation delay to change. The ability to pull the voltage at node a to a high voltage depends on the current magnitude of the second current source 121, because the drive current of the third P-channel MOSFET 112 is mirrored from the drive current of the fourth P-channel MOSFET 113.In order to quickly pull the voltage of node a to a high voltage, the current of the second current source 121 needs to be increased. However, the increased current of the second current source 121 will result in the generation of a high quiescent current. Summary of the Invention

[0004] This invention provides a level shifter that can quickly shift and output voltage levels without increasing quiescent current.

[0005] In one embodiment of the present invention, a level shifter is provided, comprising a prelevel shifter and a selector coupled to the prelevel shifter. The prelevel shifter shifts an input digital voltage to a first digital voltage and a second digital voltage. As the level of the input digital voltage changes, the levels of the first digital voltage and the second digital voltage change sequentially. The selector selects and outputs the first digital voltage, wherein the level of the first digital voltage changes earlier than the level of the second digital voltage.

[0006] In one embodiment of the invention, the level shifter further includes a buffer coupled to a selector.

[0007] In one embodiment of the present invention, the pre-level shifter includes an inverter, a first current source, a second current source, a first electronic switch, a second electronic switch, a first current mirror, a second current mirror, a first P-channel MOSFET, a second P-channel MOSFET, a first N-channel MOSFET, and a second N-channel MOSFET. The first and second current sources are coupled to a first voltage terminal. The first and second electronic switches are respectively coupled to the first and second current sources, wherein the second electronic switch is coupled to the inverter. The first and second current mirrors are coupled to a high voltage terminal. The first and second current mirrors are respectively coupled to the first and second electronic switches, wherein the first current mirror is coupled to the second current mirror. The first P-channel MOSFET is coupled to the high voltage terminal, the second electronic switch, the second current mirror, and a selector. The second P-channel MOSFET is coupled to the high voltage terminal, the first electronic switch, the first current mirror, and the selector. A first N-channel MOSFET is coupled to a second low-voltage terminal, a first P-channel MOSFET, a selector, and a second P-channel MOSFET. A second N-channel MOSFET is coupled to a second low-voltage terminal, a second P-channel MOSFET, a selector, the first N-channel MOSFET, and the first P-channel MOSFET.

[0008] In one embodiment of the present invention, the first current mirror includes two P-channel metal-oxide-semiconductor field-effect transistors, and the second current mirror includes two P-channel metal-oxide-semiconductor field-effect transistors.

[0009] In one embodiment of the present invention, both the first electronic switch and the second electronic switch are N-channel metal-oxide-semiconductor field-effect transistors.

[0010] In one embodiment of the present invention, the selector includes an inverter, a falling edge delay, and a multiplexer. The input of the inverter is coupled to a pre-level shifter, the falling edge delay is coupled to the output of the inverter, and the multiplexer is coupled to the falling edge delay, the output of the inverter, and the pre-level shifter.

[0011] In one embodiment of the present invention, the selector includes a rising-edge pulse generator, a falling-edge pulse generator, an SR latch, and a multiplexer. The rising-edge pulse generator is coupled to the output of the inverter, and the falling-edge pulse generator is coupled to a pre-level shifter. The SR latch is coupled to the rising-edge pulse generator and the falling-edge pulse generator, and the multiplexer is coupled to the SR latch, the output of the inverter, and the pre-level shifter.

[0012] In one embodiment of the present invention, the voltage of the first low-voltage terminal is lower than the voltage of the second low-voltage terminal.

[0013] Based on the above, the level shifter automatically selects a fast signal transmission path and quickly shifts and outputs a voltage level without increasing the quiescent current. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a level shifter in the prior art.

[0015] Figure 2 The waveforms of the input voltage, output node signal, and output voltage of a level shifter in the prior art are shown.

[0016] Figure 3 This is a schematic diagram of a level shifter according to the first embodiment of the present invention.

[0017] Figure 4 The waveforms of the input digital voltage, the first digital voltage, the second digital voltage, and the output digital voltage of the level shifter according to the first embodiment of the present invention are shown.

[0018] Figure 5 This is a schematic diagram of a level shifter according to a second embodiment of the present invention.

[0019] Figure 6 The waveforms of the input digital voltage, node signal, set voltage, and output digital voltage of the level shifter according to the second embodiment of the present invention are shown.

[0020] Figure 7 This is a schematic diagram of a level shifter according to a third embodiment of the present invention.

[0021] Figure 8 The waveforms of the input digital voltage of the level shifter, the node signal, the input voltage of the SR latch, the set voltage, and the output digital voltage are shown in the second embodiment of the present invention.

[0022] 100… level shifter

[0023] 110…First P-channel metal-oxide-semiconductor field-effect transistor

[0024] 111…Second P-channel metal-oxide-semiconductor field-effect transistor

[0025] 112…Third P-channel metal-oxide-semiconductor field-effect transistor

[0026] 113… Fourth P-channel metal-oxide-semiconductor field-effect transistor

[0027] 114…First N-channel metal-oxide-semiconductor field-effect transistor

[0028] 115…Second N-channel metal-oxide-semiconductor field-effect transistor

[0029] 116…Fifth P-channel metal-oxide-semiconductor field-effect transistor

[0030] 117…Sixth P-channel metal-oxide-semiconductor field-effect transistor

[0031] 118…Third N-channel metal-oxide-semiconductor field-effect transistor

[0032] 119… Fourth N-channel metal-oxide-semiconductor field-effect transistor

[0033] 120…First Current Source

[0034] 121…Second Current Source

[0035] 122…Inverter

[0036] 200… level shifter

[0037] 210…Pre-level shifter

[0038] 211…First Inverter

[0039] 212…First Current Source

[0040] 213…Second Current Source

[0041] 214…First Electronic Switch

[0042] 215…Second Electronic Switch

[0043] 216…First Current Mirror

[0044] 217…Second Current Mirror

[0045] 220…selector

[0046] 221…Second Inverter

[0047] 222… Falling Edge Delay

[0048] 223… Multiplexer

[0049] 224…Rising Edge Pulse Generator

[0050] 225… Falling Edge Pulse Generator

[0051] 226…SR latch

[0052] 230… buffer

[0053] VH, H, H', VGH... High logic level

[0054] VL, L, L', VGL... low logic level

[0055] IN, INB… Input voltage

[0056] a, d... nodes

[0057] OUT… Output voltage

[0058] U1, U2... Output terminals

[0059] I, IB… Input digital voltage

[0060] t0, t1, t2, t3, t4, t5… time points

[0061] O… Output digital voltage

[0062] MP1…First P-channel metal-oxide-semiconductor field-effect transistor

[0063] MP2…Second P-channel metal-oxide-semiconductor field-effect transistor

[0064] MN1…First N-channel metal-oxide-semiconductor field-effect transistor

[0065] MN2…Second N-channel metal-oxide-semiconductor field-effect transistor

[0066] Nodes A, B, C, D, E...

[0067] SEL…Set voltage Detailed Implementation

[0068] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0069] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0070] In the following description of "one embodiment" or "an embodiment," the reference refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0071] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element via other elements or connection means.

[0072] The disclosure is specifically described with reference to the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “described” include a description comprising “a or at least one” of the stated elements or components. Furthermore, as used in this disclosure, the singular article also includes a description of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this art, the content of this disclosure, and the specific content. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are merely illustrative and do not, of course, limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0073] The terms “substantially,” “around,” “about,” or “approximately” as used herein should generally mean within 20%, preferably within 10%, of a given value or range. Furthermore, quantities provided herein may be approximate, thus meaning that unless otherwise stated, the terms “about,” “approximately,” or “approximately” may be used. When a quantity, concentration, or other numerical value or parameter has a specified range, preferred range, or lists upper and lower ideal values, it should be considered as specifically disclosing all ranges consisting of pairs of numbers or ideal values ​​of any upper and lower limits, whether such ranges are separately disclosed. For example, if a range of length X cm to Y cm is disclosed, it should be considered as disclosing a length of H cm, where H can be any real number between X and Y.

[0074] The following description provides a level shifter. The level shifter automatically selects a fast signal transmission path and rapidly shifts and outputs a voltage level without increasing quiescent current. The level shifter described below can also be applied to other circuit architectures.

[0075] Figure 3 This is a schematic diagram of a level shifter according to the first embodiment of the present invention. Figure 4The image shows waveforms of the input digital voltage, first digital voltage, second digital voltage, and output digital voltage of the level shifter according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 3 and Figure 4 The first embodiment of the present invention is described below. In the first embodiment, the level shifter 200 includes a pre-level shifter 210 and a selector 220. The pre-level shifter 210 has an input terminal and two output terminals U1 and U2. The output terminals U1 and U2 of the pre-level shifter 210 are coupled to the selector 220.

[0076] The operation of the level shifter 200 in the first embodiment is described below. The pre-level shifter 210 receives an input digital voltage I and shifts it to a first digital voltage and a second digital voltage. Therefore, the two output terminals U1 and U2 of the pre-level shifter 210 output the first digital voltage and the second digital voltage, respectively. For example, the input digital voltage I has a range of 0-3 volts, and each of the first and second digital voltages has a range of 25-30 volts, but this invention does not limit these voltage ranges. Specifically, the low logic level L' and high logic level H' of the input digital voltage I are 0 volts and 3 volts, respectively. The low logic level L and high logic level H of each of the first and second digital voltages are 25 volts and 30 volts, respectively. During the time interval between time point t0 and time point t1, the input digital voltage I is at a low logic level L'. The output terminal U1 of the prelevel shifter 210 outputs a low logic level L as the first digital voltage, and the output terminal U2 of the prelevel shifter 210 outputs a high logic level H as the second digital voltage. Due to the limitations of the circuit characteristics of the prelevel shifter 210, the levels of the first and second digital voltages change sequentially as the level of the input digital voltage I changes. For example, when the level of the input digital voltage I rises from a low logic level L' to a high logic level H' at time point t1, the level of the first digital voltage rises from a low logic level L to a high logic level H at time point t1, and the level of the second digital voltage drops from a high logic level H to a low logic level L at time point t2. The selector 220 receives the first and second digital voltages and selects and outputs the first digital voltage. Since time point t1 is earlier than time point t2, the level of the first digital voltage changes earlier than the level of the second digital voltage. Therefore, selector 220 outputs a first digital voltage, which is used as the output digital voltage O between time point t1 and time point t3. That is, the output digital voltage O is a high logic level H between time point t1 and time point t3.

[0077] During the time interval between time points t2 and t3, the input digital voltage I is at a high logic level H'. The output of prelevel shifter 210, U1, outputs a high logic level H as the second digital voltage, and the output of prelevel shifter 210, U2, outputs a low logic level L as the first digital voltage. Due to the limitations of the circuit characteristics of prelevel shifter 210, the levels of the first and second digital voltages change sequentially as the level of the input digital voltage I changes. For example, when the level of the input digital voltage I drops from a high logic level H' to a low logic level L' at time point t3, the level of the first digital voltage rises from a low logic level L to a high logic level H at time point t3, and the level of the second digital voltage drops from a high logic level H to a low logic level L at time point t4. Selector 220 receives the first and second digital voltages and selects and outputs the first digital voltage without increasing the quiescent current. Since time point t3 is earlier than time point t4, the level of the first digital voltage changes earlier than the level of the second digital voltage. Therefore, since selector 220 can invert the first digital voltage, after time point t3, selector 220 outputs the inverted first digital voltage and uses this as the output digital voltage O. That is, after time point t3, the output digital voltage O is a low logic level L. Alternatively, selector 220 can directly output the first digital voltage and use this as the output digital voltage O, making the output digital voltage O a high logic level H after time point t3.

[0078] Figure 5 This is a schematic diagram of a level shifter according to a second embodiment of the present invention. Figure 6 The waveform diagram shows the input digital voltage, node signal, set voltage, and output digital voltage of the level shifter according to the second embodiment of the present invention. Please refer to [link / reference]. Figure 5 and Figure 6The second embodiment of the present invention is described below. The difference between the second embodiment and the first embodiment lies in the internal circuitry of the pre-level shifter 210 and the selector 220. In the second embodiment, the pre-level shifter 210 may include, but is not limited to, a first inverter 211, a first current source 212, a second current source 213, a first electronic switch 214, a second electronic switch 215, a first current mirror 216, a second current mirror 217, a first P-channel MOSFET MP1, a second P-channel MOSFET MP2, a first N-channel MOSFET MN1, and a second N-channel MOSFET MN2. The first electronic switch 214 and the second electronic switch 215 are N-channel MOSFETs, but the present invention is not limited thereto. The first current mirror 216 includes, but is not limited to, two P-channel MOSFETs. The second current mirror 217 includes, but is not limited to, two P-channel MOSFETs.

[0079] The first current source 212 and the second current source 213 are coupled to a first low-voltage terminal. This first low-voltage terminal can be grounded, but the invention is not limited thereto. The first electronic switch 214 and the second electronic switch 215 are respectively coupled to the first current source 212 and the second current source 213. The second electronic switch 215 is coupled to an inverter 211. The first current mirror 216 and the second current mirror 217 are coupled to a high-voltage terminal and are also coupled to the first electronic switch 214 and the second electronic switch 215, respectively. The voltage of the high-voltage terminal is denoted by VGH, which represents a high logic level H. The first current mirror 216 is coupled to the second current mirror 217. The levels of nodes A and B are difficult to change because the first current mirror 216 and the second current mirror 217, when interconnected, function like a latch. To easily change the levels of nodes A and B, the driving capability of the transistors in the first electronic switch 214 and the second electronic switch 215 must be higher than the driving capability of the transistors in the first current mirror 216 and the second current mirror 217. In other words, the channel length and channel width of the transistors of the first electronic switch 214 and the second electronic switch 215 must be greater than the channel length and channel width of the transistors of the first current mirror 216 and the second current mirror 217, respectively.

[0080] A first P-channel MOSFET MP1 is coupled to a high-voltage terminal, a second electronic switch 215, a second current mirror 217, and a selector 220. A second P-channel MOSFET MP2 is coupled to a high-voltage terminal, a first electronic switch 214, a first current mirror 216, and a selector 220. A first N-channel MOSFET MN1 is coupled to a second low-voltage terminal, the first P-channel MOSFET MP1, the selector 220, and the second P-channel MOSFET MP2. The voltage of the second low-voltage terminal is denoted by VGL, which represents a low logic level L. In some embodiments, the voltage of the first low-voltage terminal may be substantially lower than the voltage of the second low-voltage terminal. A second N-channel MOSFET MN2 is coupled to the second low-voltage terminal, the second P-channel MOSFET MP2, the selector 220, the first N-channel MOSFET MN1, and the first P-channel MOSFET MP1. Because the first N-channel MOSFET MN1 and the second N-channel MOSFET MN2 are interconnected, their function is similar to a latch, making it difficult to change the voltage levels at nodes C and D. To easily change the voltage levels at nodes C and D, the driving capability of the first P-channel MOSFET MP1 and the second P-channel MOSFET MP2 must be higher than that of the first N-channel MOSFET MN1 and the second N-channel MOSFET MN2. In other words, the channel length and channel width of the first P-channel MOSFET MP1 and the second P-channel MOSFET MP2 must be greater than those of the first N-channel MOSFET MN1 and the second N-channel MOSFET MN2. Node C is located between the first N-channel MOSFET MN1 and the first P-channel MOSFET MP1 and is considered another output terminal of the pre-level shifter 210.

[0081] In a second embodiment, selector 220 may include, but is not limited to, a second inverter 221, a falling-edge delay cell 222, and a multiplexer 223. The input of the second inverter 221 is coupled to node C of the pre-level shifter 210. The falling-edge delay cell 222 is coupled to the output of the second inverter 221. The output of the second inverter 221 is considered to be node E. The multiplexer 223 is coupled to the output of the falling-edge delay cell 222 and the second inverter 221, and node D of the pre-level shifter 210. To increase drive capability, level shifter 200 may further include a buffer 230, which is coupled to the multiplexer 223 of selector 220. Buffer 230 may be coupled to a high-voltage terminal and a second low-voltage terminal. Alternatively, buffer 230 may be coupled to an external power supply. In some embodiments of the invention, buffer 230 may further include inverters coupled in series, but the invention is not limited thereto.

[0082] The operation of the level shifter 200 in the second embodiment is described below. During the time interval between time point t0 and time point t1, the first electronic switch 214 and the first inverter 211 receive a low logic level L' as the input digital voltage I. Then, the input digital voltage I turns off the first electronic switch 214. The first inverter 211 inverts the input digital voltage I to generate a high logic level H' as the input digital voltage IB. The input digital voltage IB turns on the second electronic switch 215. Therefore, the current from the second current source 213 flows through the second electronic switch 215, pulling the voltage at node B to a low voltage. The voltage at node B turns on the first P-channel MOSFET MP1, pulling the voltage at node C to a high logic level H. The voltage at node C turns on the second N-channel MOSFET MN2, pulling the voltage at node D to a low logic level L. The voltages at nodes C and D are considered the second digital voltage and the first digital voltage, respectively. The second inverter 221 inverts the voltage at node C to generate a low logic level L at node E. Falling edge delay 222 receives the voltage of node E to generate a low logic level L, which is used as a set voltage SEL. Multiplexer 223 selects and outputs the voltage of node D based on the low logic level L used as the set voltage SEL. Finally, buffer 230 receives the voltage of node D and outputs a low logic level L as the output digital voltage O.

[0083] When the level of the input digital voltage I rises from low logic level L' to high logic level H' at time point t1, the input digital voltage IB drops from high logic level H' to low logic level L' at time point t1. The input digital voltage I turns on the first electronic switch 214. The input digital voltage IB turns off the second electronic switch 215. The current from the first current source 212 flows through the first electronic switch 214, pulling the voltage at node A to a low voltage. The voltage at node A turns on the second P-channel metal-oxide-semiconductor field-effect transistor MP2, pulling the voltage at node D to a high logic level H. The voltage at node D turns on the first N-channel metal-oxide-semiconductor field-effect transistor MN1, pulling the voltage at node C to a low logic level L. Because the driving capability of the first N-channel metal-oxide-semiconductor field-effect transistor MN1 is weak, after time point t1, the first N-channel metal-oxide-semiconductor field-effect transistor MN1 pulls the voltage at node C to a low logic level L at time point t2. Simultaneously, at time t2 after time t1, the second inverter 221 pulls the voltage of node E to a high logic level H. The falling edge delay 222 pulls the set voltage SEL to a high logic level H at time t2. During the period between time t1 and time t2, the multiplexer 223 selects and outputs the voltage of node D as the first digital voltage based on the low logic level L of the set voltage SEL. The buffer 230 receives the voltage of node D, outputs a low logic level L, and uses this as the output digital voltage O.

[0084] During the time interval between time points t2 and t3, the voltages of nodes C and D are treated as the first digital voltage and the second digital voltage, respectively. During the time interval between time points t2 and t3, multiplexer 223 selects and outputs the voltage of node E based on the high logic level H of the set voltage SEL. Buffer 230 receives the voltage of node E and outputs a low logic level H as the output digital voltage O.

[0085] When the level of the input digital voltage I drops from high logic level H' to low logic level L' at time t3, the input digital voltage IB rises from low logic level L' to high logic level H' at time t3. The input digital voltage I turns off the first electronic switch 214. The input digital voltage IB turns on the second electronic switch 215. The current from the second current source 213 flows through the second electronic switch 215, pulling the voltage at node B to a low voltage. The voltage at node B turns on the first P-channel metal-oxide-semiconductor field-effect transistor MP1, pulling the voltage at node C to a high logic level H. Simultaneously, at time t3, the second inverter 221 pulls the voltage at node E to a low logic level L. The voltage at node C turns on the second N-channel metal-oxide-semiconductor field-effect transistor MN2, pulling the voltage at node D to a low logic level L. Because the driving capability of the second N-channel MOSFET MN2 is relatively weak, the second N-channel MOSFET MN2 pulls the voltage of node D to a low logic level L at time t4, after time t3. The falling edge delay 222 pulls the set voltage SEL to a low logic level L at time t5, after time t4. During the period between time t3 and time t5, the multiplexer 223 selects and outputs the voltage of node E based on the high logic level H of the set voltage SEL. In other words, the level shifter 200 automatically selects a fast signal transmission path without increasing the quiescent current. The buffer 230 receives the voltage of node E and outputs a high logic level H as the output digital voltage O. After time t5, the multiplexer 223 selects and outputs the voltage of node D based on the low logic level L of the set voltage SEL. The buffer 230 receives the voltage of node D and outputs a low logic level L as the output digital voltage O.

[0086] Figure 7 This is a schematic diagram of a level shifter according to a third embodiment of the present invention. Figure 8 The waveforms of the input digital voltage of the level shifter, the node signal, the input voltage of the SR latch, the set voltage, and the output digital voltage are shown in the second embodiment of the present invention. Please refer to [link / reference]. Figure 7 and Figure 8The third embodiment of the present invention is described below. The difference between the third and second embodiments lies in the internal circuitry of the selector 220. In the third embodiment, the selector 220 may include, but is not limited to, a second inverter 221, a multiplexer 223, a rising-edge pulse generator 224, a falling-edge pulse generator 225, and an SR latch 226. The input of the second inverter 221 is coupled to node C of the pre-level shifter 210. The rising-edge pulse generator 224 is coupled to the output of the second inverter 221. The output of the second inverter 221 is considered to be node E. The falling-edge pulse generator 225 is coupled to node D of the pre-level shifter 210. The S and R inputs of the SR latch are respectively coupled to the rising-edge pulse generator 224 and the falling-edge pulse generator 225. Multiplexer 223 is coupled to the Q output of SR latch, the output of second inverter 221 and node D of pre-level shifter 210.

[0087] The operation of the level shifter 200 in the third embodiment is described below. The operation of the pre-level shifter 210 has been described previously and will not be repeated here. During the time period between time point t0 and time point t1, the first electronic switch 214 and the first inverter 211 receive a low logic level L' as the input digital voltage I. The voltages of nodes C and D are respectively regarded as the second digital voltage and the first digital voltage. The second inverter 221 inverts the voltage of node C to generate a low logic level L at node E. The rising edge pulse generator 224 receives the voltage of node E to generate a low logic level L, which is received by the S input terminal of the SR latch 226. The falling edge pulse generator 225 receives the voltage of node D to generate a low logic level L, which is received by the R input terminal of the SR latch 226. Therefore, based on the voltages of the S input terminal and the R input terminal, the Q output terminal of the SR latch 226 generates a low logic level L as the set voltage SEL. Multiplexer 223 receives the voltages of nodes D and E and a set voltage SEL. Based on the low logic level L of the set voltage SEL, multiplexer 223 selects and outputs the voltage of node D. Finally, buffer 230 receives the voltage of node D and outputs a low logic level L as the output digital voltage O.

[0088] When the level of the input digital voltage I rises from low logic level L' to high logic level H' at time t1, the level of the input digital voltage IB falls from high logic level H' to low logic level L' at time t1. At time t2, after time t1, the second inverter 221 pulls the voltage of node E to high logic level H. The rising-edge pulse generator 224 receives the voltage of node E to generate a positive pulse, which is received by the S input of the SR latch 226 at time t2. The falling-edge pulse generator 225 receives the voltage of node D to generate a low logic level L, which is received by the R input of the SR latch 226. Therefore, based on the voltages at the S and R inputs at time t2, the Q output of the SR latch 226 pulls the set voltage SEL to high logic level H. During the time interval between time point t1 and time point t2, based on the low logic level L of the set voltage SEL, multiplexer 223 selects and outputs the voltage of node D as the first digital voltage. Finally, buffer 230 receives the voltage of node D and outputs the low logic level L as the output digital voltage O.

[0089] During the time interval between time points t2 and t3, the voltages of nodes C and D are treated as the first digital voltage and the second digital voltage, respectively. During the time interval between time points t2 and t3, multiplexer 223 selects and outputs the voltage of node E based on the high logic level H of the set voltage SEL. Buffer 230 receives the voltage of node E and outputs the high logic level H as the output digital voltage O.

[0090] When the level of the input digital voltage I drops from high logic level H' to low logic level L' at time point t3, the level of the input digital voltage IB rises from low logic level L' to high logic level H' at time point t3. The second inverter 221 pulls the voltage of node E to low logic level L at time point t3. The rising-edge pulse generator 224 receives the voltage of node E to generate a low logic level L, which is received by the S input of the SR latch 226. The falling-edge pulse generator 225 receives the voltage of node D to generate a positive pulse, which is received by the R input of the SR latch 226 at time point t4. Therefore, based on the voltages at the S and R inputs at time point t4 after time point t3, the Q output of the SR latch 226 pulls the set voltage SEL to low logic level L. During the period between time points t3 and t4, the multiplexer 223 selects and outputs the voltage of node E based on the high logic level H of the set voltage SEL. In other words, level shifter 200 can automatically select a fast signal transmission path without increasing quiescent current. Finally, buffer 230 receives the voltage of node E and outputs a low logic level L as the output digital voltage O. After time point t4, based on the low logic level L as the set voltage SEL, multiplexer 223 selects and outputs the voltage of node D. Buffer 230 receives the voltage of node D and outputs a low logic level L as the output digital voltage O.

[0091] According to the above embodiment, the level shifter automatically selects a fast signal transmission path and quickly shifts and outputs a voltage level without increasing the quiescent current.

[0092] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A level shifter, characterized in that, include: A pre-level shifter for shifting an input digital voltage to a first digital voltage and a second digital voltage, wherein the levels of the first digital voltage and the second digital voltage change sequentially as the level of the input digital voltage changes; as well as A selector, including: An inverter whose input is used to receive the second digital voltage; A falling edge delay is coupled to the output of the inverter and used to output a set voltage; and A multiplexer is used to select either the first digital voltage or an output voltage of the inverter as the output voltage based on the logic level of the set voltage.

2. The level shifter as described in claim 1, characterized in that, It also includes a buffer that is coupled to the selector.

3. The level shifter as described in claim 1, characterized in that, The pre-level shifter includes: An inverter; A first current source and a second current source are coupled to a first low-voltage terminal; A first electronic switch and a second electronic switch are respectively coupled to the first current source and the second current source, wherein the second electronic switch is coupled to the inverter; A first current mirror and a second current mirror are coupled to a high voltage terminal. The first current mirror and the second current mirror are respectively coupled to the first electronic switch and the second electronic switch, wherein the first current mirror is coupled to the second current mirror. A first P-channel metal-oxide-semiconductor field-effect transistor is coupled to the high-voltage terminal, the second electronic switch, the second current mirror, and the selector; A second P-channel metal-oxide-semiconductor field-effect transistor is coupled to the high-voltage terminal, the first electronic switch, the first current mirror, and the selector; A first N-channel metal-oxide-semiconductor field-effect transistor, coupled to a second low-voltage terminal, the first P-channel metal-oxide-semiconductor field-effect transistor, the selector, and the second P-channel metal-oxide-semiconductor field-effect transistor; and A second N-channel metal-oxide-semiconductor field-effect transistor is coupled to the second low-voltage terminal, the second P-channel metal-oxide-semiconductor field-effect transistor, the selector, the first N-channel metal-oxide-semiconductor field-effect transistor, and the first P-channel metal-oxide-semiconductor field-effect transistor.

4. The level shifter as described in claim 3, characterized in that, The first current mirror includes two P-channel metal-oxide-semiconductor field-effect transistors, and the second current mirror includes two P-channel metal-oxide-semiconductor field-effect transistors.

5. The level shifter as described in claim 3, characterized in that, Both the first electronic switch and the second electronic switch are N-channel metal-oxide-semiconductor field-effect transistors.

6. The level shifter as described in claim 3, characterized in that, The voltage at the first low-voltage terminal is lower than the voltage at the second low-voltage terminal.

7. A level shifter, characterized in that, include: A pre-level shifter for shifting an input digital voltage to a first digital voltage and a second digital voltage, wherein the levels of the first digital voltage and the second digital voltage change sequentially as the level of the input digital voltage changes; as well as A selector, including: An inverter, the input of which is coupled to the pre-level shifter and used to receive the second digital voltage; A rising edge pulse generator is coupled to the output of the inverter; A falling edge pulse generator is coupled to the prelevel shifter and used to receive the first digital voltage; An SR latch, coupled to the rising edge pulse generator and the falling edge pulse generator, is used to output a set voltage; and A multiplexer is coupled to the Q output of the SR latch, the inverter, and the pre-level shifter, and is used to select either the first digital voltage or an output voltage of the inverter as the output voltage according to the logic level of the set voltage.

Images