High-speed high-dV / dt immunity level shift circuit based on dynamic pull-down current

Abstract

The invention relates to the technical field of integrated circuit level shifting, in particular to a low-power-consumption high-speed level shifting circuit based on dynamic pull-down current. The level shift circuit comprises a low-voltage domain and a high-voltage domain where a high-voltage floating power rail is located, the low-voltage domain is provided with a dynamic pull-down current generating circuit, and the high-voltage domain is provided with a level conversion circuit electrically connected with the high-voltage domain. When level jump occurs to a low-voltage input signal, the dynamic pull-down current generation circuit controllably generates a large transient pull-down current and injects the large transient pull-down current into a high-voltage domain, a high-voltage domain control node is triggered to turn over rapidly in a current comparison mode, and reliable level shift from the low-voltage signal to a high-voltage floating power rail signal is achieved. During the steady state of the input signal, the circuit maintains a smaller quiescent current, thereby significantly reducing power consumption. The scheme gives consideration to high-speed response and low static power consumption, and is suitable for high-voltage isolation, floating driving and mixed voltage system scenes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a high-speed, high dV / dt immunity level shifting circuit based on dynamic pull-down current. Background Technology

[0002] Level shifting circuits are a key circuit module in analog integrated circuits, widely used in half-bridge drivers and high-voltage BUCK converters. They are typically used as a transmission bridge between different voltage domains, transferring the potential of control logic from the low-voltage domain to the high-voltage domain.

[0003] For example, in a high-voltage Buck-type DC-DC converter, the overall circuit is divided into two operating regions: a high-voltage basin and a low-voltage basin. Figure 1 As shown. The high-voltage basin mainly includes level shifting circuits, high-side drive circuits, and bootstrap circuits, while the low-voltage basin mainly includes power management circuits, logic circuits, and various protection circuits. Unlike the low-voltage basin's power supply (usually a fixed voltage below 5V), the high-voltage basin is mainly powered by a floating power supply (VSSH-VDDH). This allows the high-side drive circuit in the high-voltage basin to control the power switch's on and off. The original drive signal controlling the high-side drive circuit comes from the logic control circuit in the low-voltage basin, requiring the conversion of the low-voltage basin's logic signal to the high-voltage basin's logic signal. The level shifting circuit converts the drive signal to ground into a drive signal to the high-side floating rail, thus enabling the power switch to be turned on and off. Therefore, the level shifting circuit can be considered the bridge connecting the low-voltage and high-voltage basins, and is an essential key module for gate drivers in analog integrated circuits.

[0004] However, the design of level shifting circuits currently faces two main challenges. One challenge is the need to balance and optimize transmission delay with low power consumption, where high transmission delay is particularly detrimental in high-speed signal scenarios. The other challenge is the dV / dt (the rate of change of voltage over time) generated by the rapid switching of the power transistor. Figure 1 The change in switching node voltage VSW of the middle Buck converter over time (referring to noise immunity issues). If the dV / dt noise suppression capability of the level shifting circuit is low, it will directly affect the reliability of signal transmission and cause incorrect conduction of the power transistor. Therefore, reliability must be considered in circuit design. Summary of the Invention

[0005] Existing level shifting circuits, when operating under high-voltage floating power rail conditions, generally rely on continuous bias current or static voltage threshold triggering mechanisms to complete the level conversion from low-voltage signals to the high-voltage domain. When the input signal experiences a level transition, this type of structure suffers from significant level shifting transmission delays due to the large parasitic capacitance of the high-voltage domain control node, resulting in a slow charging and discharging process. This makes it difficult to meet the application requirements of high-speed signal transmission. Furthermore, under conditions of rapid potential changes on the high-voltage floating power rail, the control node is susceptible to common-mode voltage variations, leading to false triggering or output instability.

[0006] Therefore, without introducing continuous static power consumption or relying on absolute voltage threshold judgment, how to provide sufficient driving capability at the moment of input signal transition to accelerate the switching of high voltage domain nodes, and ensure that the level shifting process remains stable and reliable in a high dV / dt noise environment, is a core technical problem that urgently needs to be solved in the existing technology.

[0007] To address the aforementioned technical problems, this invention proposes a level shifting circuit based on dynamic pull-down current, comprising a low-voltage domain and a high-voltage domain. The low-voltage domain includes a dynamic pull-down current generating circuit, and the high-voltage domain includes a level conversion circuit connected to the dynamic pull-down current generating circuit. Specifically, the dynamic pull-down current generating circuit generates a large dynamic pull-down current in a controlled manner when the input signal in the low-voltage domain experiences a level transition. This large dynamic pull-down current is injected into the level conversion circuit in the high-voltage domain, triggering a flip-flop in the high-voltage domain control node via current comparison, thereby completing the level shift from the low-voltage input signal to the high-voltage floating power rail signal. Because the large dynamic pull-down current can drive the level transition very quickly, the level shifting circuit can maintain low power consumption.

[0008] Furthermore, the dynamic pull-down current generating circuit includes a switching structure controlled by an input signal, a current mirror structure, and a high-voltage isolation structure. The switching structure controls the current mirror structure to conduct at the instant of input signal transition.

[0009] Furthermore, the dynamic pull-down current generating circuit also includes a voltage clamping structure connected to the high-voltage isolation structure for limiting the gate-source voltage of the high-voltage isolation structure.

[0010] Furthermore, the high-voltage domain is equipped with an edge detection circuit and a latching circuit. The edge detection circuit is used to detect the edge of the control signal after level conversion and has a filtering function to effectively suppress voltage fluctuations after shifting and output a pulse signal. The latching circuit is used to update the output state according to the pulse signal.

[0011] Furthermore, a transient compensation current path is provided at the key control node of the high-voltage domain to provide a transient charging and discharging path for the key control node when a rapid potential change occurs in the high-voltage floating power rail.

[0012] Compared with the prior art, the present invention has at least the following beneficial technical effects.

[0013] This invention generates a large dynamic pull-down current when the input signal transitions in the low-voltage domain, changing the high-voltage domain level transition process from voltage threshold triggering to current comparison triggering. When the input signal changes, the dynamic pull-down current can very quickly charge and discharge the parasitic capacitance of the high-voltage domain control node, thereby significantly shortening the level shift setup time and maintaining low power consumption.

[0014] Therefore, this invention achieves high-speed level shifting without significantly increasing static power consumption, effectively solving the core defects of existing level shifting circuits, such as large transmission delay and difficulty in balancing power consumption and speed.

[0015] The further introduction of a current mirror structure and a symmetrical level shifting method makes the level shifting process insensitive to device parameter fluctuations and power supply voltage changes, which helps to improve the stability of the circuit under different process angles and operating conditions, and improves the timing consistency of the rising and falling edges of the output signal.

[0016] By setting a voltage clamping structure to limit the gate-source voltage of the high-voltage isolation structure, the risk of abnormal voltage stress generated during dynamic pull-down current operation is effectively reduced, thereby improving the long-term reliability of the circuit and the safety of the devices.

[0017] By introducing an output structure that combines edge detection and latching in the high-voltage domain, the output state changes only when a valid signal edge is detected. This effectively shields the output from voltage noise when there are rapid potential changes in the high-voltage floating power rail, thus avoiding false triggering.

[0018] By setting a transient compensation current path at the critical control node, a fast charging and discharging path is provided for the parasitic capacitance of the critical node under high dV / dt noise conditions, further reducing the node potential shift and enhancing the circuit's anti-dv / dt interference capability.

[0019] In summary, this invention, through a level shifting mechanism based on dynamic pull-down current and edge detection, achieves low power consumption, high reliability, and excellent high dV / dt immunity performance while ensuring high-speed response, and has significant engineering application value.

[0020] (1) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows:

[0021] Adapting to the upgrading trend of the third-generation semiconductor industry and empowering the high-end power management market: With the widespread application of silicon carbide (SiC) and gallium nitride (GaN) power devices in new energy vehicles (800V high-voltage platforms), photovoltaic inverters, and high-density data center power supplies, the market has placed extremely high demands on the dV / dt immunity of driver chips (typically requiring >100V / ns). The technical solution of this invention achieves ultra-high dV / dt immunity, perfectly adapting to high-frequency, high-efficiency third-generation semiconductor application scenarios, and possesses extremely high market entry value and broad application prospects.

[0022] (2) Whether the technical solution of the present invention solves the technical problem that people have long wanted to solve but have never been able to solve successfully:

[0023] This invention solves the problem of "common-mode transient false triggering" under high-voltage floating power rails: In high-voltage Buck converters, drastic voltage jumps at the switching node (SW) generate displacement currents through parasitic capacitance, which has long been a persistent problem causing logic errors in the upper-side driver. While existing technologies have made improvements, they are difficult to eradicate completely and often require expensive isolation processes. This invention uses edge detection technology to convert the level signal into a noise-insensitive pulse edge signal, fundamentally distinguishing between "effective control signals" and "common-mode noise," thus solving the long-standing false triggering problem that has plagued the industry.

[0024] This solution overcomes the challenge of process drift caused by parasitic parameters: Traditional level shifting circuits are extremely sensitive to process fluctuations and temperature, resulting in large threshold drift and unstable yield during mass production. This solution uses current comparison principles instead of voltage comparison, reducing dependence on absolute device parameters and solving the manufacturing challenge of maintaining high consistency and high reliability across different process angles and temperatures.

[0025] (3) Whether the technical solution of the present invention overcomes technical bias:

[0026] This invention overcomes the technical prejudice that "high interference immunity must come at the cost of transmission speed": It is widely believed in the field that filtering out high dV / dt noise requires adding large filter capacitors or applying long dead times in the circuit, which inevitably leads to increased signal transmission delay (typically >20ns). This invention, through dynamic current acceleration and edge extraction techniques, achieves ultra-high interference immunity while controlling the delay to within 2ns, breaking the inherent perception that interference immunity and high speed are mutually exclusive.

[0027] Attached image caption

[0028] Figure 1 Circuit diagrams of Buck converters provided by existing technology;

[0029] Figure 2A high-speed, high-dV / dt immunity level shifting circuit based on dynamic pull-down current;

[0030] Figure 3 Output stage circuit structure diagram;

[0031] Figure 4 The output signal waveform of this invention;

[0032] Figure 5 Simulation results of the anti-dV / dt noise function of this invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] This invention proposes a high-speed, high-dV / dt immunity level shifter circuit based on dynamic pull-down current, achieving low propagation delay and high dV / dt immunity without significantly increasing power consumption. Furthermore, this invention is a special type of general-purpose level shifter circuit, suitable for half-bridge drivers and high-speed, high-reliability DC-DC converters.

[0035] like Figure 2 As shown, the level shifting circuit based on dynamic pull-down current of the present invention includes a low-voltage domain and a high-voltage domain connected to a floating high-voltage power rail, and the two are electrically isolated and coupled to signals through an isolation structure.

[0036] The low-voltage domain includes a dynamic pull-down current generation module and an input buffer module. The dynamic pull-down current generation module consists of input switching transistors M1 and M2, current mirror branches M3, M4, M5, and M6, high-voltage isolation transistors MHV1 and MHV2, and resistors R1 and R2. It is used to transiently generate large pull-down currents I1 and I2 when the input signal Vin changes, and injects them into the corresponding nodes in the high-voltage domain through isolation devices. The input buffer module shapes and delays Vin to ensure that the pull-down current only occurs at the edge of the signal.

[0037] The high-voltage domain includes a level-shifting core, an edge-detection buffer chain, and an RS latch. The level-shifting core consists of cross-coupled transistors M10-M15 and pull-up / pull-down branches M7, M8, M9, M11, M12, M13, and M16, forming a bistable structure. Diodes D1 and D2 limit reverse current and stabilize node potentials. Nodes A, B, C, and D serve as control nodes in the high-voltage domain, triggering state flipping through dynamic current injection. The edge-detection section consists of a delay chain of multi-stage inverters INV1-INV6, used in conjunction with NAND gates Nand1 and Nand3 to achieve pulse shaping. The RS flip-flop, composed of Nand2 and Nand4, latches the final output state, with the output being Vout.

[0038] This invention is used to reliably convert low-voltage digital control signals into logic signals in the high-voltage floating power rail domain. It is applicable to high-voltage drives, isolation interfaces, power management chips, motor drives, power device gate control, and mixed-voltage SoCs, and is especially suitable for high-voltage, large-capacitance loads or applications with strict requirements for static power consumption.

[0039] This circuit can be used in applications requiring low-voltage logic to safely control high-voltage circuits, such as bridge arm drivers, high-side switches, photovoltaic inverters, motor drives, and battery management systems.

[0040] When the low-voltage input Vin experiences a level transition, the switching transistor in the low-voltage domain turns on, causing the current mirror branch to momentarily conduct and amplify the current. This current is then injected into node A or B in the high-voltage domain via the high-voltage isolation transistor, forming a large transient dynamic pull-down current I1 or I2. This current is compared with the steady-state bias current in the high-voltage domain, disrupting the original balance of the cross-coupling structure and causing the bistable node in the high-voltage domain to flip, thus completing a level shift.

[0041] Once Vin enters steady state, the dynamic branch shuts down, and the circuit maintains only a very small static bias current, thus significantly reducing static power consumption. Edge detection and RS latching ensure that triggering only occurs on valid transitions and prevent glitches and metastability propagation, improving output stability.

[0042] Therefore, compared with traditional voltage swing driven level shifters, the present invention has the following technical advantages:

[0043] 1) The dynamic current triggering method significantly improves the node switching speed and shortens the propagation delay;

[0044] 2) Maintains extremely low quiescent current during steady state, significantly reducing power consumption;

[0045] 3) Avoid stress and reliability issues caused by direct high-voltage, large-amplitude charging and discharging;

[0046] 4) It is less sensitive to floating power rails, power jitter, and process changes, and has stronger robustness;

[0047] 5) The structure is suitable for integrated implementation, with small area and high reliability.

[0048] Therefore, this invention achieves high-speed, high-reliability level shifting while effectively balancing low power consumption and high stability, and has good engineering application value.

[0049] In a preferred embodiment of the present invention, a dynamic current generation circuit module generates a pull-down current, and a level conversion circuit module converts the input signal of the low-voltage rail to the control signal of the high-voltage floating power rail. An edge detection circuit module quickly detects the converted high-voltage floating power rail control signal and filters the voltage noise to effectively suppress voltage fluctuations, and outputs a pulse signal to the RS latch at the edge. The RS latch restores the original input signal on the high-voltage floating power rail and also shields the dV / dt noise, so that the output of the level shifting circuit remains constant.

[0050] The high-speed, high dV / dt immunity level shifting circuit proposed in this invention is composed of a low-voltage domain: a dynamic current generation module; and a high-voltage domain: a level conversion module, an edge detection module, and an RS latch module. Voltage isolation and signal transmission between the low-voltage domain and the high-voltage floating power rail are achieved through high-voltage devices.

[0051] In the low-voltage domain, the dynamic pull-down current generation circuit consists of switching transistors M1 and M2, current mirror pairs M3–M4 and M5–M6, high-voltage transistors MHV1 and MHV2, resistors R1 and R2, diode connectors MCL1 and MCL2, and an inverter. The input signal VIN, after being inverterized, drives M1 and M2 respectively, causing the current mirrors to be activated at specific times, thereby generating a dynamic pull-down current I1 or I2 in the corresponding branch. MCL1 and MCL2 are connected in a diode configuration to clamp and limit the gate-source voltage of MHV1 and MHV2, suppressing abnormal voltage stress and preventing potential device failures.

[0052] In the high-voltage domain, the level conversion circuit consists of cross-coupled current mirror structures, including PMOS transistors M7–M12 and NMOS transistors M13–M16, which are connected to the dynamic pull-down current nodes generated in the low-voltage domain. This converts the low-voltage rail input signal into control signals VC and VD under the high-voltage floating power rail. Diodes D1 and D2 act as clamping elements. The edge detection module consists of multi-stage inverters INV1–INV3 and INV4–INV6, buffers Buffer1 and Buffer2, and NAND gates. It rapidly detects the transition edges of signals VC and VD, generating narrow pulse signals S and R when a valid edge is detected. The RS latch module, composed of NAND1–NAND4, reconstructs a stable output signal VOUT within the high-voltage domain.

[0053] During normal circuit operation, the level of the low-voltage input signal VIN first controls the switching transistors M1 or M2 to turn on, causing the corresponding current mirror branch to instantaneously establish a dynamic pull-down current I1 or I2. This current is injected into the high-voltage level conversion circuit through the high-voltage transistors MHV1 or MHV2, creating a rapid discharge effect on the cross-coupled nodes, thereby triggering the toggling of the high-voltage control signal VC or VD. Since the dynamic current exists only during the valid period of the input signal, power consumption is effectively reduced.

[0054] After level conversion, the high-voltage domain signals VC and VD are sent to the edge detection module. The multi-stage inverter and buffer structure are only sensitive to the rising or falling edge of the signal, outputting a narrow pulse signal S or R when the edge arrives, while remaining unresponsive during steady state, thereby avoiding the continuous transmission of high dV / dt common-mode noise.

[0055] After receiving the S and R narrow pulse signals, the RS latch changes its latching state only when the effective edge arrives, thus reconstructing the original low-voltage input signal. Because the RS latch is insensitive to input changes after its state stabilizes, dv / dt noise in the high-voltage domain cannot cause false triggering, ensuring that the output VOUT remains constant and reliable even under strong common-mode interference.

[0056] In the high-voltage domain, a symmetrical current mirror structure is observed in the circuit. Parallel branches (M9-M16) are used for current comparison and to balance the rise and fall edge delays. M17-M20 form two dynamic current branches, generating transient current only when VSSH changes, helping to stabilize the voltages at nodes A and B. Furthermore, D1 and D2 connect VSSH to points A and B respectively, acting as clamps to reduce the impact of dV / dt noise on the potentials at points A and B. Simultaneously, the output circuit consists of an edge detection circuit that detects the voltage signals at nodes C and D, generates narrow pulse signals, and then latches the output using an RS latch. The output circuit structure is as follows: Figure 3 As shown.

[0057] This invention achieves a level shifting function that balances high-speed response and high dV / dt immunity through the coordinated operation of dynamic pull-down current triggering, level shifting, edge detection and RS latching, making it suitable for reliable signal transmission scenarios under high-voltage floating power rail conditions.

[0058] The specific working principle of the circuit of this invention is as follows: When VIN is high, M1 turns on, and node 1 is immediately pulled low to ground. At this time, the gate-source voltage difference VGS between M3 and M4 increases from approximately Vth to VDDL, where Vth represents the threshold voltage of the NMOS transistor, causing M3 and M4 to conduct. A large dynamic current I1 flows through MHV1, causing the parasitic capacitance at node A to discharge, generating a sufficiently large voltage drop, causing M7 to conduct. When the voltage at node A is less than the turn-on voltage of the PMOS transistor M7, the current mirror formed by M7 and M9 mirrors the large current in the branch where node A is located to the branch where node C is located. Since the current of M13 is very small at this time, the potential of node C is quickly pulled up. After the edge detection circuit captures the rise in the potential at point C, it generates a voltage pulse, sets the RS flip-flop, outputs a high level on the floating power rail, and changes the logic of the output signal from 0 to 1. Simultaneously, the current in the branch containing node A is mirrored to the branch containing node D through M7, M10, M15, and M16. Since the current in M12 is very small at this time, the potential of node D is quickly pulled low. Although the rate of decrease of VD is slower than the rate of increase of VA, the decrease in VD is not detected by the edge detection circuit; it merely prepares for the next reset. Therefore, when the input signal VIN changes from low to high, the rate of change of the potential of node D has no effect on the circuit.

[0059] When VIN is low, M2 turns on, and node 11 is immediately pulled low to ground. At this time, the gate-source voltage difference VGS between M5 and M6 increases from approximately Vth to VDDL, where Vth represents the threshold voltage of the NMOS. M5 and M6 then conduct, generating a large dynamic current I2 flowing through MHV2. This discharges the parasitic capacitance at node B, creating a sufficiently large voltage drop that causes M8 to turn on. This current is then mirrored through a current mirror, turning on M12. The current mirror then mirrors the large current in the branch containing point B to the branch containing point D. Since the current in M16 is very small at this time, the potential of node D will be pulled high. After the edge detection circuit detects the rise in the potential of point D, it generates a voltage pulse, resetting the RS flip-flop and outputting a low level on the floating power rail. The logic of the output signal changes from 1 to 0. Simultaneously, the current in the branch containing point B is also mirrored through M8, M11, M13, and M14 to the branch containing node C. Since the current in M9 is very small at this time, the potential of node C is quickly pulled low. Although the rate of decrease of VC is slower than the rate of increase of VB, the decrease of VC is not detected by the edge detection circuit; it merely prepares for the next setting. Therefore, when the input signal VIN changes from high to low, the rate of change of the potential at node C has no effect on the circuit. The waveform of the circuit output signal is as follows: Figure 4 As shown.

[0060] The working principle of the level shifter proposed in this invention is to shield dV / dt noise using a dV / dt noise shielding circuit composed of INV1-INV6 and NAND1-NAND4. When rapid changes in VSSH generate dV / dt noise, the voltages at nodes C and D will rise or fall synchronously. If the dV / dt noise is high, the voltage changes at nodes C and D may trigger the logic gates of the edge detection circuit. Positive dV / dt noise will generate under-adjustment voltages at nodes C and D, and negative dV / dt noise will generate over-adjustment voltages at nodes C and D. These generated voltage noises are filtered after passing through the edge detection circuit, so no error signals are generated at the S and R terminals. The state of the RS latch is not changed. Therefore, the proposed level shifter can shield dV / dt noise so that it does not interfere with the output VOUT, thereby keeping VOUT constant.

[0061] Furthermore, the level shifting circuit designed in this invention adds two dynamic current compensation branches. By adding transient compensation PMOS transistors PM17-PM20 to the branches where high-voltage transistors MHV1 and MHV2 are located, transient current is only generated when VSSH changes. For example, at nodes A and B, during the rapid rise of the floating power rail, since nodes A and B are connected to high-voltage NMOS transistors MHV1 and MHV2 respectively, there is a certain charging time. During the charging time, the voltages of nodes A and B will be simultaneously low relative to the floating high-voltage power rail VDDH for a moment. At this time, the added dynamic compensation circuit will quickly charge the parasitic capacitances CA and CB, providing a transient current path that reacts quickly to changes in voltage VSSH, helping to stabilize the voltages of nodes A and B, and further reducing the common-mode noise current flowing into M13 and M16. This fast response helps to maintain the voltage within a safe and operable range, preventing excessive deviations that may lead to logic errors. Simulation results for dV / dt noise immunity are as follows: Figure 5 As shown.

[0062] The transmission delay principle of the circuit of this invention: The delay from the rising edge of the input VIN to the rising edge of the output VOUT is denoted as Tdr. Tdr is mainly composed of four parts, namely Tdr1, Tdr2, Tdr3 and Tdr4.

[0063] Tdr1 is the propagation delay from input VIN to node A, and its magnitude is mainly related to the switching speed and current drive capability of the MOSFET. The instantaneous voltage drop of VA shortens the propagation delay Tdr1 of the level shift circuit to less than 1 ns. Tdr1 can be expressed by Equation 1 as:

[0064] t_dr1≈(c_p (VDDH-VSSH-VT)) / I_P =(c_p (5-VT)) / I_P (1)

[0065] Cp is the capacitance between the gate and source of the PMOS transistor PM9, and VTH is the turn-on voltage of the PMOS transistor PM9.

[0066] The current M7 is mirrored by M9. Because the current in M13 is small, and the current in M9 is much larger than that in M13, the potential of node C rises rapidly to VDDH. Tdr2 is the propagation delay from node A to node C, determined by the delay of the current comparator.

[0067] The edge detection circuit can identify the rising edge signal of node C. When VC goes high, a short pulse signal is generated at node S under the action of the delay chain composed of INV1-INV3, buffer1, and NAND1. Tdr3 is the delay of the edge detection circuit.

[0068] A narrow pulse signal VS is generated to trigger the switching voltage of NAND2. At this time, VOUT transitions from low to high and remains at VDDH until a short pulse appears at node R. The delay between VS and VOUT is described by Tdr4, which is the delay of NAND2.

[0069] The time delay from the falling edge of the input VIN terminal to the falling edge of the output VOUT terminal is denoted as Tdf. Tdf consists of four parts: Tdf1, Tdf2, Tdf3, and Tdf4. The analysis of Tdf is similar to that of Tdr, except that the enable signal of M2 has an additional inverter delay compared to M1. The magnitude of Tdf is approximately equal to that of Tdr, about 1 nanosecond, demonstrating that the level shifting circuit of this invention has excellent propagation delay and symmetry.

[0070] 5. Advantages and positive effects

[0071] (1) The dynamic current generation circuit mentioned in this invention cleverly designs the positions of switching transistors M1 and M2 to control the generation of currents I1 and I2. Positioning switching transistors M1 and M2 at the bottom of the current trace ensures that the gate voltages of M3 and M4, and M5 and M6 are always high, facilitating a rapid increase in the gate-source voltage and significantly reducing the propagation delay of the level shifting circuit. In steady state, the minimum values ​​of the voltages at nodes A and B are intentionally designed to be closer to (VSSH + Vth), rather than VSSH or (VSSH-0.7) in the traditional method, which helps reduce the circuit's propagation delay. The advantage of this structure is that it can reduce propagation delay while keeping power consumption within an acceptable range.

[0072] (2). The method for implementing level shifting proposed in this invention is based on the current comparison principle. Compared with traditional level shifting circuits, the advantage of this structure is that it cleverly uses a current mirror structure to make the rising and falling edge delays of the output level symmetrical, so that the transmission delay is basically the same, and improves the circuit's resistance to dV / dt.

[0073] (3) The output stage circuit proposed in this invention employs an edge detection circuit and an RS latch. This structure can detect the rising edge position of the input signal and generate a pulse signal at the rising edge of the input signal, while also filtering the generated voltage noise signal. Therefore, the anti-dV / dt characteristics of the novel level shift circuit mainly rely on the reliable output of the current comparison and the filtering effect of the edge detection circuit.

[0074] Example 1: Implementation of Basic Level Shift Based on Dynamic Pull-Down Current Triggering

[0075] This embodiment provides a level shifting circuit based on dynamic pull-down current, the structure of which is as follows: Figure 2As shown, it comprises two parts: a low-voltage domain and a high-voltage domain. The low-voltage domain is equipped with a dynamic pull-down current generation circuit, which consists of a switching transistor controlled by the input signal, a current mirror structure, and a high-voltage isolation device. The high-voltage domain is equipped with a level conversion circuit electrically connected to the dynamic pull-down current generation circuit. After the low-voltage input signal is processed by the dynamic pull-down current generation circuit, it is injected into the high-voltage domain in the form of a large dynamic pull-down current to quickly drive the control node in the high-voltage domain level conversion circuit to undergo level switching.

[0076] In this embodiment, when the low-voltage input signal undergoes a level transition, a large dynamic pull-down current is generated, which causes a very rapid charging and discharging effect on the parasitic capacitance of the high-voltage domain node, thereby triggering the level transition. Since the large dynamic pull-down current can drive the level transition very quickly, the continuous current consumption during the level transition process can be avoided, thus achieving a balance between low power consumption and high-speed response.

[0077] Example 2: Symmetrical Level Conversion Structure Based on Current Comparison

[0078] This embodiment provides a symmetrical level conversion circuit, which is positioned below a high-voltage floating power rail and connected to a dynamic pull-down current generation circuit in the low-voltage domain. The level conversion circuit employs a symmetrical current mirror structure to establish current comparison relationships between different control nodes, thereby achieving level reconstruction of the low-voltage input signal in the high-voltage domain.

[0079] In this embodiment, by using symmetrically arranged current mirror branches, the rising and falling edges triggered by the dynamic pull-down current are kept consistent in terms of propagation path and driving capability. This makes the rising edge delay and falling edge delay of the output signal basically the same, improving the timing symmetry of the level shift circuit and helping to improve the stability of the circuit under high-speed operation.

[0080] Example 3: High dV / dt immunity output structure based on edge detection technology

[0081] Based on any one of the embodiments in Example 1 to Example 2, this embodiment includes an edge detection circuit and a latching circuit in the high-voltage domain. The edge detection circuit is used to detect the edge of the control signal after the high-voltage domain conversion and has a filtering function to effectively suppress voltage fluctuations after shifting and output a narrow pulse signal; the latching circuit is used to update the output state according to the narrow pulse signal.

[0082] In this embodiment, when a rapid potential change occurs in the high-voltage floating power rail, causing a common-mode voltage disturbance, the voltage of the control node may change synchronously. However, since the edge detection circuit has a filtering function and is only sensitive to effective edges, the common-mode disturbance will not form an effective pulse at the output of the edge detection circuit, and the state of the latch circuit remains unchanged, thereby achieving effective shielding against voltage noise.

[0083] Example 4: High-voltage domain node stability structure with transient compensation capability

[0084] This embodiment provides a node transient compensation structure for improving dV / dt resistance. This structure is located at a critical control node in the high-voltage domain and connected to the high-voltage floating power rail. The node transient compensation structure only conducts during rapid potential changes in the high-voltage floating power rail, providing a transient current path for the critical control node.

[0085] In this embodiment, when the high-voltage floating power rail changes rapidly, the transient compensation structure rapidly charges and discharges the parasitic capacitance of the key control node, thereby reducing the instantaneous offset of the node potential relative to the floating power rail, reducing the amplitude of common-mode noise current flowing into the level conversion circuit, and further improving the anti-interference performance of the level shift circuit in a high dv / dt environment.

[0086] like Figure 4 The figure shows the complete timing simulation waveforms from the low-voltage input signal VIN to the key nodes C and D in the high-voltage domain, then to the edge detection signals S and R, and finally the output signal VOUT. As can be seen from the figure, nodes C and D can quickly complete the level transition when the input signal flips, and the edge detection circuit only generates a narrow pulse signal S or R when a valid rising edge occurs at node C or D. The RS latch completes the output state flip after receiving this narrow pulse and maintains a stable output for the rest of the time. Therefore, the level shifting circuit of this invention can accurately reconstruct the logic state of the low-voltage input signal, and the output signal VOUT remains stable throughout the entire operation, without erroneous flipping due to slow changes or minor disturbances in the nodes within the high-voltage domain.

[0087] like Figure 5 As shown in the figure, simulation results of resistance to dV / dt noise under the condition of rapid changes in the high-voltage floating power rail VSSH are presented. It can be seen from the figure that when VSSH changes rapidly with a large amplitude, the voltages of nodes C, D, and edge-detection-related nodes will all generate certain synchronous disturbances. However, these disturbances do not form effective control pulses at the S and R terminals, the output state of the RS latch remains unchanged, and the output signal VOUT does not exhibit false triggering or abnormal toggling. These results demonstrate that the present invention, through the synergistic effect of edge detection and latching structure, makes the output state sensitive only to valid logic edges, thereby effectively shielding interference caused by high dV / dt common-mode noise.

[0088] comprehensive Figures 4-5The simulation results show that the level shifting circuit based on dynamic pull-down current proposed in this invention can not only achieve fast and reliable level switching when the input signal flips, but also maintain the stability and correctness of the output signal under the harsh working conditions of rapid potential changes in the high-voltage floating power rail, fully demonstrating its technical effects such as high speed, low power consumption and high dV / dt anti-interference capability.

[0089] like Figure 4 The figure shows the complete timing simulation waveforms from the low-voltage input signal VIN to the key nodes C and D in the high-voltage domain, then to the edge detection signals S and R, and finally the output signal VOUT. As can be seen from the figure, nodes C and D can quickly complete the level transition when the input signal flips, and the edge detection circuit only generates a narrow pulse signal S or R when a valid rising edge occurs at node C or D. The RS latch completes the output state flip after receiving this narrow pulse and maintains a stable output for the rest of the time. Therefore, the level shifting circuit of this invention can accurately reconstruct the logic state of the low-voltage input signal, and the output signal VOUT remains stable throughout the entire operation, without erroneous flipping due to slow changes or minor disturbances in the nodes within the high-voltage domain.

[0090] like Figure 5 As shown in the figure, simulation results of anti-dV / dt noise under the condition of rapid changes in the high-voltage floating power rail VSSH are presented. It can be seen from the figure that when VSSH changes rapidly with a large amplitude, the voltages of nodes C, D, and edge-detection-related nodes will all generate certain synchronous disturbances. However, these disturbances do not form effective control pulses at the S and R terminals, the output state of the RS latch remains unchanged, and the output signal VOUT does not exhibit abnormal flipping. These results demonstrate that the present invention, through the synergistic effect of edge detection and latching structure, makes the output state sensitive only to valid logic edges, thereby effectively shielding interference caused by high dV / dt noise.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A level shifting circuit based on dynamic pull-down current triggering, characterized in that, This includes a low-voltage domain and a high-voltage domain containing the high-voltage floating power rail. Electrical isolation and signal coupling are achieved between the low-voltage domain and the high-voltage domain through an isolation structure. The low-voltage domain includes a dynamic pull-down current generation circuit, which generates a dynamic pull-down current only when a low-voltage input signal undergoes a level transition. The high-voltage domain includes a level shifting circuit, which comprises at least one set of control nodes with bistable characteristics. The dynamic pull-down current generation circuit injects the dynamic pull-down current into the control node when a low-voltage input signal transitions, causing a transient current imbalance on the control node, thereby triggering a state flip of the control node to complete the level shift. Furthermore, during the period when the low-voltage input signal is in a steady state, the dynamic pull-down current generating circuit does not output the dynamic pull-down current, so that the level shifting circuit is in a low static power consumption state.

2. The level shifting circuit as described in claim 1, characterized in that, The dynamic pull-down current generating circuit includes a switching transistor controlled by a low-voltage input signal, a current mirror structure, and a high-voltage isolation device connected to the current mirror structure. The switching transistor is used to control the current mirror structure to conduct only during the transition of the low-voltage input signal.

3. The level shifting circuit as described in claim 2, characterized in that, The dimensions of each branch of the current mirror structure are set to a fixed ratio, so that the dynamic pull-down current output when the switching transistor is turned on is greater than the steady-state bias current, thereby shortening the charging and discharging time of the control node.

4. The level shifting circuit as described in claim 2, characterized in that, The dynamic pull-down current generating circuit also includes a voltage clamping structure connected to the high-voltage isolation device to limit the gate-source voltage of the high-voltage isolation device to prevent overvoltage stress.

5. An output circuit for improving the anti-interference capability of a level shifting circuit under high voltage change rate conditions, characterized in that, This includes edge detection circuitry and latching circuitry installed under the high-voltage floating power rail. The edge detection circuit outputs a pulse signal only when the high-voltage domain control signal undergoes a valid level edge change, and does not output a pulse signal when the control signal is in a steady state. The latching circuit changes its output state according to the pulse signal and keeps its output state unchanged when there is no pulse signal, thereby suppressing the influence of common-mode noise caused by high voltage change rate on the output signal.

6. The output circuit as described in claim 5, characterized in that, The edge detection circuit includes at least one delay link composed of multi-level inverting units and logic units, so that the pulse signal is generated only on the rising or falling edge of the control signal.

7. The output circuit as described in claim 5, characterized in that, The latching circuit is a cross-feedback structure, which only flips its state under the action of the pulse signal and maintains its original output state during the potential change of the high-voltage floating power rail.

8. A node transient compensation circuit for suppressing node disturbances caused by high voltage change rate, characterized in that, It is located at a critical control node in the high-voltage domain and includes a transient current path that conducts only when there is a rapid potential change in the high-voltage floating power rail. The transient current path is used to provide a fast charging and discharging path for the parasitic capacitance of the critical control node, so as to suppress the disturbance of the common-mode noise current to the potential of the critical control node.

9. The node transient compensation circuit as described in claim 8, characterized in that, The transient current path is automatically shut off when the high-voltage floating power rail potential is stable, thereby avoiding any impact on static power consumption.

10. The node transient compensation circuit as described in claim 8, characterized in that, The node transient compensation circuits are respectively set at multiple symmetrical control nodes corresponding to the level conversion circuit to reduce the overall impact of common-mode noise on the level conversion circuit.

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