A high-speed level conversion circuit

Abstract

This invention discloses a high-speed level conversion circuit, relating to the field of integrated circuit technology, to solve the problem that traditional level conversion circuits fail to convert when the difference between the input voltage and the conversion voltage is too large. It includes: a level conversion sub-circuit disposed between a high-voltage power supply and ground, a first pull-up circuit, and a second pull-up circuit; the level conversion sub-circuit includes at least a cross-coupled first node and a second node; the first input terminal of the first pull-up circuit is connected to the input terminal of the level conversion sub-circuit, the second input terminal of the first pull-up circuit is connected to the first node, and the output terminal of the first pull-up circuit is connected to the second node; the first input terminal of the second pull-up circuit is connected to the output terminal of the level conversion sub-circuit, the second input terminal of the second pull-up circuit is connected to the second node, and the output terminal of the second pull-up circuit is connected to the first node. This invention provides a high-speed level conversion circuit for achieving level conversion with a larger switching voltage difference.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-speed level conversion circuit. Background Technology

[0002] In fields such as high-voltage power drives, motor control, switching power supplies, and automotive electronics, control circuits typically operate in the low-voltage logic domain, while drive circuits such as power switches need to operate in the high-voltage domain. To achieve reliable transmission between low-voltage control signals and high-voltage drive signals, level conversion circuits are an indispensable and crucial module.

[0003] However, in traditional level-shifting circuits, when the input signal undergoes a transition, the inherent voltage difference between the internal nodes and the high-voltage power supply prevents the pull-up components from being completely turned off instantaneously. This results in both the pull-down and pull-up paths being active simultaneously at the moment of level transition, leading to intense level competition. When the difference between the input voltage and the transition voltage is too large, the level-shifting function of the entire circuit will fail, severely affecting the circuit's operational stability and output reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed level conversion circuit to solve the problem that traditional level conversion circuits will fail to convert when the difference between the input voltage and the conversion voltage is too large.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A high-speed level conversion circuit includes a level conversion sub-circuit disposed between a high-voltage power supply and ground, a first pull-up circuit, and a second pull-up circuit. The level conversion sub-circuit includes at least a cross-coupled first node and a second node; The first input terminal of the first pull-up circuit is connected to the input terminal of the level conversion sub-circuit, the second input terminal of the first pull-up circuit is connected to the first node, and the output terminal of the first pull-up circuit is connected to the second node; the first input terminal of the second pull-up circuit is connected to the output terminal of the level conversion sub-circuit, the second input terminal of the second pull-up circuit is connected to the second node, and the output terminal of the second pull-up circuit is connected to the first node. The level conversion sub-circuit is used to realize the level conversion between low level and high level; the first pull-up circuit is used to pull up the voltage of the second node to high level when the input signal of the level conversion sub-circuit flips from low level to high level; the second pull-up circuit is used to pull up the voltage of the first node to high level when the input signal of the level conversion sub-circuit flips from high level to low level.

[0006] Optionally, the first pull-up circuit includes a first NAND gate and a first PMOS transistor. The first input terminal of the first NAND gate is connected to the input terminal of the level conversion sub-circuit, the second input terminal of the first NAND gate is connected to the first node, the output terminal of the first NAND gate is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the second node.

[0007] Optionally, the second pull-up circuit includes a second NAND gate and a second PMOS transistor; the first input terminal of the second NAND gate is connected to the output terminal of the level conversion sub-circuit, the second input terminal of the second NAND gate is connected to the second node, the output terminal of the second NAND gate is connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the first node.

[0008] Optionally, the level conversion sub-circuit includes at least a first inverter, a second inverter, a third PMOS transistor, and a fourth PMOS transistor. The first inverter, the second inverter, the third PMOS transistor, and the fourth PMOS transistor are cross-coupled to form a first node and a second node. The first node and the second node are complementary differential nodes. The first node and the second node are used to provide complementary level states during level conversion and achieve fast switching and state latching through cross-coupling.

[0009] Optionally, the output terminal of the first inverter is connected to the gate of the fourth PMOS transistor, the input terminal of the first inverter is connected to the first input terminal of the first NAND gate, the input terminal of the second inverter is connected to the gate of the third PMOS transistor, the output terminal of the second inverter is connected to the first input terminal of the second NAND gate, the first node is located on the line connecting the output terminal of the first inverter and the gate of the fourth PMOS transistor, and the second node is located on the line connecting the input terminal of the second inverter and the gate of the third PMOS transistor.

[0010] Optionally, the first inverter includes a fifth PMOS transistor and a first NMOS transistor; the second inverter includes a sixth PMOS transistor and a second NMOS transistor; the gate of the fifth PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the fourth PMOS transistor, the source of the fifth PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the first NMOS transistor is connected to ground; the gate of the sixth PMOS transistor is connected to the gate of the second NMOS transistor and the first input terminal of the second NAND gate, the drain of the sixth PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the third PMOS transistor, the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the second NMOS transistor is connected to ground.

[0011] Optionally, the level conversion sub-circuit further includes a NOT gate, the output of which is connected to the output of the second inverter, and the input of which is connected to the input of the first inverter.

[0012] Optionally, when the input signal of the level conversion sub-circuit flips from low level to high level, the first NAND gate generates a first logic level signal. The first logic level signal is used to drive the first PMOS transistor to turn on. The drain current output by the first PMOS transistor is used to suppress the pull-up capability of the sixth PMOS transistor, thereby reducing the current competition between the sixth PMOS transistor and the second NMOS transistor, and pulling the voltage of the second node to a high level.

[0013] Optionally, when the input signal of the level conversion sub-circuit flips from high level to low level, the second NAND gate generates a second logic level signal. The second logic level signal is used to drive the second PMOS transistor to turn on. The drain current output by the second PMOS transistor is used to suppress the pull-up capability of the fifth PMOS transistor, thereby reducing the current competition between the fifth PMOS transistor and the first NMOS transistor, and pulling the voltage of the first node to a high level.

[0014] Optionally, when the voltage of the second node is pulled up to a high level, the conduction capability of the third PMOS transistor decreases, the first node is pulled down to a low level, and the first NAND gate generates a third logic level signal, which is used to turn off the first PMOS transistor. When the voltage of the first node is pulled up to a high level, the conduction capability of the fourth PMOS transistor decreases, and the voltage of the second node is pulled down to a low level. The second NAND gate generates a fourth logic level signal, which is used to turn off the second PMOS transistor.

[0015] Compared with the prior art, the present invention provides a high-speed level conversion circuit, including a level conversion sub-circuit, a first pull-up circuit, and a second pull-up circuit disposed between a high-voltage power supply and ground; the level conversion sub-circuit includes at least a first node and a second node that are cross-coupled; the first input terminal of the first pull-up circuit is connected to the input terminal of the level conversion sub-circuit, the second input terminal of the first pull-up circuit is connected to the first node, and the output terminal of the first pull-up circuit is connected to the second node. The first input terminal of the second pull-up circuit is connected to the output terminal of the level conversion sub-circuit. The second input terminal of the second pull-up circuit is connected to the second node, and the output terminal of the second pull-up circuit is connected to the first node. The level conversion sub-circuit is used to realize the level conversion between low and high levels. The first pull-up circuit is used to pull up the voltage of the second node to a high level when the input signal of the level conversion sub-circuit flips from low to high. At this time, the voltage of the first node is pulled down to a low level, and the first pull-up circuit automatically closes without affecting the recovery of the first and second nodes to their pre-flip state. The second pull-up circuit is used to pull up the voltage of the first node to a high level when the input signal of the level conversion sub-circuit flips from high to low. At this time, the voltage of the second node is pulled down to a low level, and the second pull-up circuit automatically closes without affecting the recovery of the first and second nodes to their pre-flip state. The high-speed level conversion circuit of the present invention has no additional power consumption loss in the static state. The first pull-up circuit and the second pull-up circuit are activated when the input signal of the level conversion sub-circuit is flipped and are cut off after the flip is completed, so that the input signal automatically returns to the initial state after the flip is completed. Therefore, no matter how large the voltage difference is, it will not affect the circuit flipping, and level conversion with larger flipping voltage differences can be achieved. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 The circuit diagram provided by this invention is a high-speed level conversion circuit.

[0017] Figure label: 1-Level conversion sub-circuit, 2-First pull-up circuit, 3-Second pull-up circuit, P1-First PMOS transistor, P2-Second PMOS transistor, P3-Third PMOS transistor, P4-Fourth PMOS transistor, P5-Fifth PMOS transistor, P6-Sixth PMOS transistor, N1-First NMOS transistor, N2-Second NMOS transistor, ND1-First NAND gate, ND2-Second NAND gate, A-First node, B-Second node, X1-NOT gate. Detailed Implementation

[0018] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0021] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] In the prior art, when the difference between the input voltage and the conversion voltage is too large, the pull-down capability of the pull-down path of the traditional level conversion circuit is not as good as the pull-up capability of the pull-up path, which will lead to output conversion failure and cannot meet the requirements of integrated circuits with larger voltage difference conversion needs.

[0024] To address the aforementioned problems, this invention provides a high-speed level conversion circuit, which will be described below with reference to the accompanying drawings.

[0025] Please see Figure 1The present invention provides a high-speed level conversion circuit including a level conversion sub-circuit 1, a first pull-up circuit 2, and a second pull-up circuit 3 disposed between the high-voltage power supply and ground; Level conversion sub-circuit 1 includes at least a first node A and a second node B that are cross-coupled; The first input terminal of the first pull-up circuit 2 is connected to the input terminal of the level conversion sub-circuit 1, the second input terminal of the first pull-up circuit 2 is connected to the first node A, and the output terminal of the first pull-up circuit 2 is connected to the second node B; the first input terminal of the second pull-up circuit 3 is connected to the input terminal of the level conversion sub-circuit 1, the second input terminal of the second pull-up circuit 3 is connected to the second node B, and the output terminal of the second pull-up circuit 3 is connected to the first node A. The level conversion sub-circuit 1 is used to realize the level conversion between low level and high level; the first pull-up circuit 2 is used to pull up the voltage of the second node B to a high level when the input signal of the level conversion sub-circuit 1 flips from low level to high level; the second pull-up circuit 3 is used to pull up the voltage of the first node A to a high level when the input signal of the level conversion sub-circuit 1 flips from high level to low level.

[0026] Figure 1 The first pull-up circuit in the aforementioned high-speed level conversion circuit pulls the voltage of the second node to a high level when the input signal of the level conversion sub-circuit flips from low to high. At this time, the voltage of the first node is pulled down to low, and the first pull-up circuit automatically shuts off, without affecting the recovery of the first and second nodes to their pre-flip states. The second pull-up circuit pulls the voltage of the first node to a high level when the input signal of the level conversion sub-circuit flips from high to low. At this time, the voltage of the second node is pulled down to low, and the second pull-up circuit automatically shuts off, without affecting the recovery of the first and second nodes to their pre-flip states. This circuit has no additional power consumption loss in the idle state, and the first and second pull-up circuits start when the input signal of the level conversion sub-circuit flips and shut down after the flip, so that the input signal automatically returns to its initial state after the flip. Therefore, no matter how large the voltage difference is, it will not affect the circuit flipping, and level conversion with larger flipping voltage differences can be achieved.

[0027] As an alternative approach, the level conversion sub-circuit 1 in the above structure includes a first inverter, a second inverter, a third PMOS transistor P3, a fourth PMOS transistor P4, and a NOT gate X1. The first inverter, the second inverter, the third PMOS transistor P3, and the fourth PMOS transistor P4 are cross-coupled to form a first node A and a second node B. The first node A and the second node B are complementary differential nodes. The first node A and the second node B are used to provide complementary level states during level conversion and achieve fast switching and state latching through cross-coupling.

[0028] Specifically, the output of the first inverter is connected to the gate of the fourth PMOS transistor P4, the input of the second inverter is connected to the gate of the third PMOS transistor P3, and the source of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4 and the high-voltage power supply VDDH. Node A is located on the line connecting the output of the first inverter and the gate of the fourth PMOS transistor P4, and node B is located on the line connecting the input of the second inverter and the gate of the third PMOS transistor P3. The output of NOT gate X1 is connected to the output of the second inverter, and the input of NOT gate X1 is connected to the input of the first inverter.

[0029] As an alternative, the first inverter may include a fifth PMOS transistor P5 and a first NMOS transistor N1; the second inverter may include a sixth PMOS transistor P6 and a second NMOS transistor N2; the gate of the fifth PMOS transistor P5 is connected to the gate of the first NMOS transistor N1, the drain of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1 and the gate of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5 is connected to the drain of the third PMOS transistor P3, and the source of the first NMOS transistor N1 is connected to ground (GND); the gate of the sixth PMOS transistor P6 is connected to the gate of the second NMOS transistor N2, the drain of the sixth PMOS transistor P6 is connected to the drain of the second NMOS transistor N2 and the gate of the third PMOS transistor P3, the source of the sixth PMOS transistor P6 is connected to the drain of the fourth PMOS transistor P4, and the source of the second NMOS transistor N2 is connected to ground (GND).

[0030] In practical applications, if the level conversion circuit only includes the aforementioned level conversion sub-circuit 1, when the input signal IN is low, the voltage at the first node is VDDH, and the voltage at the second node B is 0. When the input signal IN changes from low to VDD, the first NMOS transistor turns on, causing the voltage at the first node A to drop, and the fourth PMOS transistor gradually turns on. At this time, the output terminal INB changes to low, the sixth PMOS transistor P6 turns on, and the voltage at the second node B gradually rises, eventually causing the voltage at the first node A to change to 0, and the voltage at the second node B to change to VDDH. However, during the conversion process, because the voltage at the input terminal IN is VDD and the voltage at point C is VDDH, the fifth PMOS transistor P5 cannot be turned off, and there is a current competition between the fifth PMOS transistor P5 and the first NMOS transistor N1. Therefore, if the difference between the input voltage and the conversion voltage is too large, the pull-down capability of the first NMOS transistor N1 may be less than the pull-up capability of the fifth PMOS transistor P5, leading to output conversion failure.

[0031] To solve the above problems, the present invention connects a second pull-up circuit 3 to the first node A of the level conversion sub-circuit 1, and symmetrically connects a first pull-up circuit 2 to the second node B. A detailed description follows.

[0032] Specifically, the aforementioned first pull-up circuit 2 includes a first NAND gate ND1 and a first PMOS transistor P1. The first input terminal of the first NAND gate ND1 is connected to the input terminal of the level conversion sub-circuit, i.e., connected to the input terminal of the first NAND gate ND1. The second input terminal of the first NAND gate ND1 is connected to the first node A, i.e., connected to the output terminal of the first inverter. The output terminal of the first NAND gate ND1 is connected to the gate of the first PMOS transistor P1. The drain of the first PMOS transistor P1 is connected to the second node B, i.e., connected to the input terminal of the second inverter. The source of the first PMOS transistor P1 is connected to the low-voltage power supply VDDL. It can be understood that the first input terminal of the first NAND gate ND1 is the first input terminal of the first pull-up circuit 2, the second input terminal of the first NAND gate ND1 is the second input terminal of the first pull-up circuit 2, and the drain of the first PMOS transistor P1 is the output terminal of the first pull-up circuit 2.

[0033] In practical applications, when the input signal of the level conversion sub-circuit 1 flips from low to high, the first NAND gate ND1 generates a first logic level signal. This first logic level signal drives the first PMOS transistor P1 to conduct. The drain current output by the first PMOS transistor P1 is used to suppress the pull-up capability of the sixth PMOS transistor P6, thus reducing the current competition between the sixth PMOS transistor P6 and the second NMOS transistor N2. The voltage of the second node B is quickly pulled up to a high level. When the voltage of the second node B is pulled up to a high level, the conduction capability of the third PMOS transistor P3 decreases, and the first node A is pulled down to a low level. The first NAND gate ND1 generates a third logic level signal, which is used to turn off the first PMOS transistor P1. Compared to the case where the level conversion circuit only includes level conversion sub-circuit 1, the pull-up of the fifth PMOS transistor P5 and the first NMOS transistor N1 are in conflict, and it takes a period of time to pull down the voltage of the first node A. This invention can quickly pull up the second node B to a high level through the first pull-up circuit, so that the pull-up of the fifth PMOS transistor becomes weaker, and the first node A will become 0 faster, thereby accelerating the voltage switching speed of level conversion.

[0034] Specifically, the aforementioned second pull-up circuit 3 includes a second NAND gate ND2 and a second PMOS transistor P2. The first input terminal of the second NAND gate ND2 is connected to the output terminal of the level conversion sub-circuit 1, i.e., connected to the output terminal of the second inverter. The second input terminal of the second NAND gate ND2 is connected to the second node B, i.e., connected to the input terminal of the second inverter. The output terminal of the second NAND gate ND2 is connected to the gate of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the first node A, i.e., connected to the output terminal of the first inverter. The source of the second PMOS transistor P2 is connected to the low-voltage power supply VDDL. It can be understood that the first input terminal of the second NAND gate ND2 is the first input terminal of the second pull-up circuit 3, the second input terminal of the second NAND gate ND2 is the second input terminal of the second pull-up circuit 3, and the drain of the second PMOS transistor P2 is the output terminal of the second pull-up circuit 3.

[0035] In practical applications, when the input signal of the level conversion sub-circuit flips from high to low, the second NAND gate generates a second logic level signal. This second logic level signal is used to drive the second PMOS transistor to conduct. The drain current output by the second PMOS transistor is used to suppress the pull-up capability of the fifth PMOS transistor, thus weakening the current competition between the fifth PMOS transistor and the first NMOS transistor, and pulling the voltage of the first node to a high level. When the voltage of the first node is pulled to a high level, the conduction capability of the fourth PMOS transistor decreases, the voltage of the second node is pulled down to a low level, and the second NAND gate generates a fourth logic level signal, which is used to turn off the second PMOS transistor. Compared to the situation where the level conversion circuit only includes level conversion sub-circuit 1, where the pull-up of the sixth PMOS transistor P6 and the second NMOS transistor N2 is antagonistic and requires a period of time to pull the voltage of point B down, this invention can quickly pull the second node A to a high level through the second pull-up circuit, making the pull-up of the sixth PMOS transistor P6 weaker, and the second node B will become 0 faster, thereby accelerating the voltage flip speed of the level conversion.

[0036] In practical implementation: Assuming the initial state is IN=0, INB=VDDL, A=VDDH, B=0, ND1 and ND2 output VDDL, P1 and P2 are off. After IN transitions from 0 to VDDL, due to the competition between N1 and P5, point A remains high, so N1 outputs 0, P1 conducts. Since INB is 0, there is no competition between P1 and N2, so point B is quickly pulled to VDDL, weakening the conduction capability of P3. Point A is then pulled down to 0 more rapidly. When A becomes 0, ND1 outputs VDDL, and P1 returns to the off state. During this process, P2 remains off. If IN transitions from VDDL to 0, P2 conducts to help point B quickly drop to 0, while P1 remains off. It can be seen that this invention has no additional power loss in the static state, starts during the transition process, and automatically returns to the initial state after the transition ends. This invention not only accelerates the voltage transition speed of level conversion but also helps support larger transition voltage differences.

[0037] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0038] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-speed level conversion circuit, characterized in that, It includes a level conversion sub-circuit, a first pull-up circuit, and a second pull-up circuit, which are set between the high-voltage power supply and ground. The level conversion sub-circuit includes at least a cross-coupled first node and a second node; The first input terminal of the first pull-up circuit is connected to the input terminal of the level conversion sub-circuit, the second input terminal of the first pull-up circuit is connected to the first node, and the output terminal of the first pull-up circuit is connected to the second node; the first input terminal of the second pull-up circuit is connected to the output terminal of the level conversion sub-circuit, the second input terminal of the second pull-up circuit is connected to the second node, and the output terminal of the second pull-up circuit is connected to the first node. The level conversion sub-circuit is used to realize the level conversion between low level and high level; the first pull-up circuit is used to pull up the voltage of the second node to high level when the input signal of the level conversion sub-circuit flips from low level to high level; the second pull-up circuit is used to pull up the voltage of the first node to high level when the input signal of the level conversion sub-circuit flips from high level to low level.

2. The high-speed level conversion circuit according to claim 1, characterized in that, The first pull-up circuit includes a first NAND gate and a first PMOS transistor. The first input terminal of the first NAND gate is connected to the input terminal of the level conversion sub-circuit, the second input terminal of the first NAND gate is connected to the first node, the output terminal of the first NAND gate is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the second node.

3. The high-speed level conversion circuit according to claim 1, characterized in that, The second pull-up circuit includes a second NAND gate and a second PMOS transistor; the first input terminal of the second NAND gate is connected to the output terminal of the level conversion sub-circuit, the second input terminal of the second NAND gate is connected to the second node, the output terminal of the second NAND gate is connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the first node.

4. The high-speed level conversion circuit according to claim 1, characterized in that, The level conversion sub-circuit includes at least a first inverter, a second inverter, a third PMOS transistor, and a fourth PMOS transistor. The first inverter, the second inverter, the third PMOS transistor, and the fourth PMOS transistor are cross-coupled to form a first node and a second node. The first node and the second node are complementary differential nodes. The first node and the second node are used to provide complementary level states during level transitions and achieve fast toggling and state latching through cross-coupling.

5. The high-speed level conversion circuit according to claim 4, characterized in that, The output terminal of the first inverter is connected to the gate of the fourth PMOS transistor, the input terminal of the first inverter is connected to the first input terminal of the first NAND gate, the input terminal of the second inverter is connected to the gate of the third PMOS transistor, the output terminal of the second inverter is connected to the first input terminal of the second NAND gate, the first node is located on the line connecting the output terminal of the first inverter and the gate of the fourth PMOS transistor, and the second node is located on the line connecting the input terminal of the second inverter and the gate of the third PMOS transistor.

6. The high-speed level conversion circuit according to claim 5, characterized in that, The first inverter includes a fifth PMOS transistor and a first NMOS transistor; the second inverter includes a sixth PMOS transistor and a second NMOS transistor; the gate of the fifth PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the fourth PMOS transistor, the source of the fifth PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the first NMOS transistor is connected to ground; the gate of the sixth PMOS transistor is connected to the gate of the second NMOS transistor and the first input terminal of the second NAND gate, the drain of the sixth PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the third PMOS transistor, the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the second NMOS transistor is connected to ground.

7. The high-speed level conversion circuit according to claim 4, characterized in that, The level conversion sub-circuit also includes a NOT gate, the output of which is connected to the output of the second inverter, and the input of which is connected to the input of the first inverter.

8. The high-speed level conversion circuit according to claim 1, characterized in that, When the input signal of the level conversion sub-circuit flips from low level to high level, the first NAND gate generates a first logic level signal. The first logic level signal is used to drive the first PMOS transistor to turn on. The drain current output by the first PMOS transistor is used to suppress the pull-up capability of the sixth PMOS transistor, thereby reducing the current competition between the sixth PMOS transistor and the second NMOS transistor, and pulling the voltage of the second node to a high level.

9. The high-speed level conversion circuit according to claim 1, characterized in that, When the input signal of the level conversion sub-circuit flips from high level to low level, the second NAND gate generates a second logic level signal. The second logic level signal is used to drive the second PMOS transistor to turn on. The drain current output by the second PMOS transistor is used to suppress the pull-up capability of the fifth PMOS transistor, thereby reducing the current competition between the fifth PMOS transistor and the first NMOS transistor, and pulling the voltage of the first node to a high level.

10. The high-speed level conversion circuit according to claim 1, characterized in that, When the voltage of the second node is pulled up to a high level, the conduction capability of the third PMOS transistor decreases, the first node is pulled down to a low level, and the first NAND gate generates a third logic level signal, which is used to turn off the first PMOS transistor. When the voltage of the first node is pulled up to a high level, the conduction capability of the fourth PMOS transistor decreases, and the voltage of the second node is pulled down to a low level. The second NAND gate generates a fourth logic level signal, which is used to turn off the second PMOS transistor.

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