Multi-port chip testing method and apparatus

Abstract

The present disclosure relates to a multi-port chip testing method and device, the device comprising a host, a switch assembly, a level conversion assembly, a port switching assembly, the host being configured to: establish a connection relationship between each input port and each output port in the port switching assembly; establish an analog test path or a digital test path according to the type of a test signal, wherein if the type of the test signal is an analog signal, an analog test path is established through the switch assembly and each input port of the port switching assembly; if the type of the test signal is a digital signal, a digital test path is established through the switch assembly, the level conversion assembly and each input port of the port switching assembly; send the test signal to the test chip for testing, and receive a result signal returned by the test chip. The present disclosure can realize switching of any port in different voltage environments, improve the testing efficiency of the chip, and avoid possible signal conflict problems.

Description

Technical Field

[0001] This disclosure relates to the field of testing technology, and in particular to a method and apparatus for testing multi-port chips. Background Technology

[0002] Typically, after a chip is manufactured, it is tested to ensure its performance. Currently, when the number of chip pins is large, the relevant technology cannot achieve switching between any port under different voltage conditions, resulting in low testing efficiency and potential signal conflicts. Summary of the Invention

[0003] According to one aspect of this disclosure, a multi-port chip testing apparatus is provided. The apparatus includes a host, a switching component, a level conversion component, and a port switching component. The host is connected to the switching component and the level conversion component. Both the switching component and the level conversion component are connected to respective input ports of the port switching component. Each port of the test chip is correspondingly connected to each output port of the port switching component.

[0004] The host is used for:

[0005] Establish the connection relationship between each input port and each output port in the port switching component;

[0006] An analog test path or a digital test path is established according to the type of the test signal. If the type of the test signal is an analog signal, an analog test path is established through the switching component and each input port of the port switching component. If the type of the test signal is a digital signal, a digital test path is established through the switching component and the level conversion component and each input port of the port switching component.

[0007] The test signal is sent to the test chip for testing, and the result signal returned by the test chip is received.

[0008] In one possible implementation, establishing the connection relationship between each input port and each output port in the port switching component includes:

[0009] The input port number and output port number are determined based on the received port switching command;

[0010] Establish the connection relationship between each input port number and each output port number in the port switching component.

[0011] In one possible implementation, the switching assembly includes multiple switches, which include any one of relays, reed switches, silicon controlled rectifiers, switching diodes, switching transistors, electronic bidirectional switches, and optocouplers. The level conversion assembly includes multiple level converters, which include unidirectional level converters or bidirectional level converters.

[0012] In one possible implementation, if each switch in the switching assembly is a relay, the switching assembly further includes a relay driving circuit adapted to each relay, wherein the relay includes a first host analog signal input terminal, a second host analog signal input terminal, a first channel input terminal, a first channel output terminal, a second channel input terminal, a second channel output terminal, and a driving signal receiving terminal, wherein...

[0013] The drive signal receiving terminal is used to receive the drive signal output by the relay drive circuit, wherein,

[0014] If the drive signal is high, the first channel input terminal and the first channel output terminal of the relay are respectively connected to the first host analog signal input terminal and the second host analog signal input terminal to establish the analog test path;

[0015] If the drive signal is low, the first channel access terminal and the first channel output terminal of the relay are connected to the second channel access terminal and the second channel output terminal, respectively, to establish the digital test path.

[0016] In one possible implementation, the relay driving circuit includes a first driving resistor, a second driving resistor, a third driving resistor, a first driving capacitor, and a first driving transistor, wherein,

[0017] The first end of the first driving resistor is used to receive the control signal from the host, and the second end of the first driving resistor is connected to the first end of the second driving resistor, the first end of the first driving capacitor, and the gate of the first driving transistor.

[0018] The drain of the first driving transistor is connected to the driving signal receiving terminal, and the source of the first driving transistor is connected to the first terminal of the third driving resistor.

[0019] The second end of the second driving resistor, the second end of the first driving capacitor, and the second end of the third driving resistor are grounded.

[0020] In one possible implementation, the host is also used to perform at least one of the following steps:

[0021] During the testing of the test chip, the connection relationship between each input port and each output port is switched according to the port switching command;

[0022] To end the test of the test chip, disconnect the connection between each input port and each output port in the port switching component; disconnect the analog test path or digital test path, and set the level conversion component to the output state.

[0023] In one possible implementation, if the level converter is a unidirectional level converter, then the host is used to switch the input / output state of the level converter; or

[0024] If the level converter is a bidirectional level converter, the level converter will automatically switch between input and output states.

[0025] In one possible implementation, the port switching component includes multiple analog switch array circuits, each analog switch array circuit including N input ports and M output ports, wherein each input port of each analog switch array circuit is connected to the other, and the host is used to establish a connection between any input port and at least one output port, where N and M are both integers greater than 0.

[0026] According to one aspect of this disclosure, a multi-port chip testing method is provided. The method is applied to the host unit of a multi-port chip testing apparatus. The apparatus includes the host unit, a switching component, a level conversion component, and a port switching component. The host unit is connected to the switching component and the level conversion component. Both the switching component and the level conversion component are connected to various input ports of the port switching component. Various ports of the test chip are correspondingly connected to various output ports of the port switching component. The method includes:

[0027] Establish the connection relationship between each input port and each output port in the port switching component;

[0028] An analog test path or a digital test path is established according to the type of the test signal. If the type of the test signal is an analog signal, an analog test path is established through the switching component and each input port of the port switching component. If the type of the test signal is a digital signal, a digital test path is established through the switching component and the level conversion component and each input port of the port switching component.

[0029] The test signal is sent to the test chip for testing, and the result signal returned by the test chip is received.

[0030] In one possible implementation, the method further includes:

[0031] During the testing of the test chip, the connection relationship between each input port and each output port is switched according to the port switching command; and / or

[0032] To end the test of the test chip, disconnect the connection between each input port and each output port in the port switching component; disconnect the analog test path or digital test path, and set the level conversion component to the output state.

[0033] According to one aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0034] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0035] The multi-port chip testing device proposed in this disclosure includes a host, a switching component, a level conversion component, and a port switching component. The host is connected to the switching component and the level conversion component. The host establishes the connection relationship between each input port and each output port in the port switching component. According to the analog or digital type of the test signal, a corresponding analog test path or digital test path is established. The test signal is sent to the test chip for testing, and the result signal returned by the test chip is received. It can realize the switching of any port under different voltage environments, improve the chip testing efficiency, and avoid possible signal conflict problems.

[0036] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0038] Figure 1 A block diagram of a multi-port chip testing apparatus according to an embodiment of the present disclosure is shown.

[0039] Figure 2 A flowchart illustrating the operation of host 10 according to an embodiment of this disclosure is shown.

[0040] Figure 3 A schematic diagram of a switch assembly according to an embodiment of the present disclosure is shown. Detailed Implementation

[0041] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0042] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0044] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0045] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0046] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0047] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0048] Please see Figure 1 , Figure 1 A block diagram of a multi-port chip testing apparatus according to an embodiment of the present disclosure is shown.

[0049] Please see Figure 2 , Figure 2 A flowchart illustrating the operation of host 10 according to an embodiment of this disclosure is shown.

[0050] like Figure 1 As shown, the device includes a host 10, a switching assembly 20, a level conversion assembly 30, and a port switching assembly 40. The host 10 is connected to the switching assembly 20 and the level conversion assembly 30. The switching assembly 20 and the level conversion assembly 30 are both connected to the respective input ports of the port switching assembly 40. The respective ports of the test chip 50 are correspondingly connected to the respective output ports of the port switching assembly 40.

[0051] like Figure 2 As shown, the host 10 is used for:

[0052] Step S11: Establish the connection relationship between each input port and each output port in the port switching component 40;

[0053] Step S12: Establish an analog test path or a digital test path according to the type of the test signal. If the type of the test signal is an analog signal, an analog test path is established through the switch component 20 and each input port of the port switching component 40. If the type of the test signal is a digital signal, a digital test path is established through the switch component 20 and the level conversion component 30 and each input port of the port switching component 40.

[0054] Step S13: Send the test signal to the test chip 50 for testing, and receive the result signal returned by the test chip 50.

[0055] The multi-port chip testing device proposed in this embodiment includes a host 10, a switching component 20, a level conversion component 30, and a port switching component 40. The host 10 is connected to the switching component 20 and the level conversion component 30. The host 10 establishes the connection relationship between each input port and each output port in the port switching component 40. According to the analog or digital type of the test signal, a corresponding analog test path or digital test path is established, the test signal is sent to the test chip 50 for testing, and the result signal returned by the test chip 50 is received. It can realize the switching of any port under different voltage environments, improve the chip testing efficiency, and avoid possible signal conflict problems.

[0056] The present disclosure does not limit the specific implementation of the host 10, the switch component 20, the level conversion component 30, and the port switching component 40. Those skilled in the art can choose a suitable method to implement them according to the actual situation and needs, as long as the corresponding functions can be achieved.

[0057] For example, the host 10 may include a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.

[0058] In some possible implementations, the method can be implemented by a processing component invoking computer-readable instructions stored in memory. In one example, the processing component includes, but is not limited to, a standalone processor, discrete components, or a combination of processors and discrete components. The processor may include a controller in an electronic device capable of executing instructions, and may be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions may be executed by hardware circuitry such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.

[0059] For example, the switching assembly 20 may include multiple switches, including any one or more of relays, reed switches, thyristors, switching diodes, switching transistors, electronic bidirectional switches, optocouplers, etc. The level conversion assembly 30 may include multiple level converters, which may include unidirectional level converters or bidirectional level converters. The level converters perform digital voltage conversion for different voltage chips to adapt to different chip voltage logic. Among them, the bidirectional level converter has an automatic bidirectional switching function, which reduces the occupation of the corresponding control lines and host 10 ports, effectively reduces the circuit board size, and reduces processing costs.

[0060] For example, the port switching component 40 may include multiple analog switch array circuits, each of which may include N input ports and M output ports. The input ports of each analog switch array circuit are connected to each other. The host 10 is used to establish a connection between any input port and at least one output port. N and M are both integers greater than 0. In this way, the embodiments of this disclosure can achieve port expansion, enabling efficient testing of the pin test chip 50. For example, assuming the port switching component 40 includes K analog switch array circuits, where K is greater than 1, then by connecting the input ports of the K analog switch array circuits, an N-to-K×M port expansion can be achieved. Alternatively, the input terminals of the analog switch array circuits can be arranged in parallel, thereby achieving an L×N-to-K×M port expansion, where L≤K. Through these methods, the embodiments of this disclosure can solve the port testing combination problem for multi-port large chips.

[0061] The embodiments disclosed herein do not limit the specific implementation of each step executed by the host 10. Those skilled in the art can choose an appropriate method to implement it according to the actual situation and needs.

[0062] In one possible implementation, step S11, establishing the connection relationship between each input port and each output port in the port switching component 40, may include:

[0063] The input port number and output port number are determined based on the received port switching command;

[0064] Establish the connection relationship between each input port number and each output port number in the port switching component 40.

[0065] For example, the host 10 can receive port switching instructions input from other devices (such as keyboards, touch screens, etc.) to determine each input port number and each output port number according to the received port switching instructions, and establish the connection relationship between the corresponding ports of each input port number and each output port number in the port switching component 40. For example, the user can send a protocol command for port switching instructions through the USB port of the host 10 or other communication methods. The protocol command includes the input port number and the output port number. After receiving the switching instruction, the host 10 automatically determines and sends the corresponding analog matrix switch recognizable port switching waveform to perform port conversion.

[0066] This disclosure does not limit the specific implementation method for determining the type of the test signal. Those skilled in the art can choose an appropriate method to implement it according to time constraints and needs.

[0067] For example, the host 10 can use a computer or other communication methods to determine whether the test signal contains the input / output requirements of analog signals such as analog-to-digital converter (ADC) or digital-to-analog converter (DAC). If so, it switches to the analog test path (direct connection method such as relay). If not, it closes the analog test path and switches to the digital test path to meet the test requirements of the 50-level test chip.

[0068] The present disclosure does not limit the specific implementation of the switching component 20 and the level conversion component 30. For different types of switching components 20 and level conversion components 30, those skilled in the art can select appropriate control methods to establish test paths according to the different devices. The following is an exemplary description.

[0069] Please see Figure 3 , Figure 3 A schematic diagram of a switch assembly according to an embodiment of the present disclosure is shown.

[0070] In one possible implementation, if each switch in the switching assembly 20 is a relay, the switching assembly 20 may further include a relay drive circuit adapted to each relay, wherein, for example... Figure 3 As shown, the relay includes a first host analog signal input terminal PA0, a second host analog signal input terminal PA1, a first channel input terminal Y0, a first channel output terminal Y1, a second channel input terminal Y0_11, a second channel output terminal Y1_11, and a drive signal receiving terminal (8). The power supply voltage VCC5-1 is connected to the voltage input terminal (1) through resistor R105.

[0071] The drive signal receiving terminal is used to receive the drive signal output by the relay drive circuit, wherein,

[0072] If the drive signal is high, the first channel input terminal Y0 and the first channel output terminal Y1 of the relay are connected to the first host analog signal input terminal PA0 and the second host analog signal input terminal PA1, respectively, to establish the analog test path;

[0073] If the drive signal is low, the first channel access terminal Y0 and the first channel output terminal Y1 of the relay are connected to the second channel access terminal Y0_11 and the second channel output terminal Y1_11, respectively, to establish the digital test path.

[0074] The relay used in the switching assembly 20 of this embodiment can be a single-pole double-throw signal. The initial state of the relay in the switching assembly 20 can be a normally closed state, that is, the first channel access terminal Y0 and the first channel output terminal Y1 of the relay are respectively connected to the second channel access terminal Y0_11 and the second channel output terminal Y1_11 (digital test path). If the drive signal turns high, the first channel access terminal Y0 and the first channel output terminal Y1 of the relay are respectively connected to the first host analog signal access terminal PA0 and the second host analog signal access terminal PA1 to establish the analog test path.

[0075] In one possible implementation, such as Figure 3 As shown, the relay driving circuit may include a first driving resistor R106, a second driving resistor R107, a third driving resistor R108, a first driving capacitor C63, and a first driving transistor Q9, wherein...

[0076] The first terminal of the first driving resistor R106 is used to receive the control signal PH0 transmitted from the host 10. The second terminal of the first driving resistor R106 is connected to the first terminal of the second driving resistor R107, the first terminal of the first driving capacitor C63, and the gate of the first driving transistor Q9.

[0077] The drain of the first driving transistor Q9 is connected to the driving signal receiving terminal, and the source of the first driving transistor Q9 is connected to the first terminal of the third driving resistor R108.

[0078] The second terminal of the second driving resistor R107, the second terminal of the first driving capacitor C63, and the second terminal of the third driving resistor R108 are grounded.

[0079] For example, the host 10 can establish digital and analog test paths by controlling the level of the control signal PH0.

[0080] In one example, such as Figure 3 As shown, the first channel access terminal Y0 and the first channel output terminal Y1 are the COM common terminals of the two communication channels, channel 0 and channel 1, respectively. The first host analog signal access terminal PA0 is the access terminal of channel 0 of the host 10 analog signal port, which is connected to the normally open NO terminal of the relay channel 0. The second host analog signal access terminal PA1 is the access terminal of channel 1 of the host 10 analog signal port, which is connected to the normally open NO terminal of the relay channel 1. The second channel access terminal Y0_11 is the access terminal of the B port of the level converter channel 0. The second channel output terminal Y1_11 is the access terminal of the B port of the level converter channel 1. The relay drive circuit consists of the first driving resistor R106, the second driving resistor R107, the third driving resistor R108, the first driving capacitor C63, and the first driving transistor Q9. PH0 is the control signal port of the host 10. When the control signal PH0 is high, the transistor Q9 conducts, thereby driving the relay K9 to work. The first channel input terminal Y0 and the first channel output terminal Y1 of the relay are shorted to the first host analog signal input terminal PA0 and the second host analog signal input terminal PA1, respectively, and the entire circuit switches to analog signal path testing. When PH0 is low, the relay does not work, and the first channel input terminal Y0 and the first channel output terminal Y1 are always shorted to the second channel input terminal Y0_11 and the second channel output terminal Y1_11, respectively, maintaining the B-terminal connection state of the voltage level shift converter, thereby connecting the entire digital signal test path.

[0081] In one possible implementation, the host 10 can also be used to perform at least one of the following steps:

[0082] During the testing of the test chip 50, the connection relationship between each input port and each output port is switched according to the port switching command;

[0083] To end the test of the test chip 50, disconnect the connection between each input port and each output port in the port switching component 40; disconnect the analog test path or digital test path, and set the level conversion component 30 to the output state.

[0084] For example, once the analog or digital test path is established, the host 10 can test the test chip 50 and receive the signal returned by the test chip 50. During subsequent signal transmission (after the digital / analog signal is executed, the subsequent execution steps and conditions of the operation process continue to be executed), the host 10 can identify whether the test port of the test chip 50 is the same as the previously opened port. If they are the same, the port opening command is not executed and a prompt message is output to the display interface; if they are different, the port switching command is executed, and after the switching is completed, a successful execution command is sent back to the computer or other communication platform.

[0085] For example, to terminate the test of the test chip 50, the host 10 can send a close port connection command to the port switching component 40, and then restore the normally open and normally closed state of the relay port in the switching component 20. If the level conversion component 30 is a unidirectional level shifter, the host 10 adjusts the direction control terminal of the level conversion component 30 to the output state. When an input / output operation is required, the host 10 controls the direction of the conversion chip. The host 10 disconnects the connection between each input port and each output port in the port switching component 40, terminates the connection of the corresponding port, and can clear the port label in memory, clear the error message, error flag, and related operation prompts (such as analog signal flag, digital signal flag, test channel flag, test direction flag, etc.) for subsequent opening of the port. The output state indicates that the test signal is sent from the host 10 to the test chip 50 as a test waveform signal or communication signal. The input state indicates that the test signal is sent from the test chip 50 to the host 10 for measurement and judgment. For example, the error message could be that the same port of the test chip 50 cannot be connected to multiple ports accessed by the host 10 at the same time, as simultaneous access will cause signal interference and loss, providing unreliable measurement information.

[0086] In one possible implementation, if the level converter is a unidirectional level converter, then the host 10 is used to switch the input / output state of the level converter; or

[0087] If the level converter is a bidirectional level converter, the level converter will automatically switch between input and output states.

[0088] The embodiments of this disclosure do not limit the specific implementation of unidirectional level converters and bidirectional level converters, nor do they limit the method of automatically switching the input / output state of bidirectional level converters. Those skilled in the art can refer to relevant technologies for implementation.

[0089] In addition to solving the switching problems between one-to-many ports and many-to-many ports, the embodiments disclosed herein also solve the communication and data acquisition problems of the two systems under different voltage test environments, and can also solve the problem of extended application of digital signal waveforms and analog signal waveforms.

[0090] According to one aspect of this disclosure, a multi-port chip testing method is provided. The method is applied to a host 10 of a multi-port chip testing apparatus. The apparatus includes the host 10, a switching component 20, a level conversion component 30, and a port switching component 40. The host 10 is connected to the switching component 20 and the level conversion component 30. Both the switching component 20 and the level conversion component 30 are connected to respective input ports of the port switching component 40. Each port of the test chip 50 is correspondingly connected to each output port of the port switching component 40. Figure 2 As shown, the method includes:

[0091] Step S11: Establish the connection relationship between each input port and each output port in the port switching component 40;

[0092] Step S12: Establish an analog test path or a digital test path according to the type of the test signal. If the type of the test signal is an analog signal, an analog test path is established through the switch component 20 and each input port of the port switching component 40. If the type of the test signal is a digital signal, a digital test path is established through the switch component 20 and the level conversion component 30 and each input port of the port switching component 40.

[0093] Step S13: Send the test signal to the test chip 50 for testing, and receive the result signal returned by the test chip 50.

[0094] In this embodiment, the host 10 establishes the connection relationship between each input port and each output port in the port switching component 40; according to the analog or digital type of the test signal, a corresponding analog test path or digital test path is established, the test signal is sent to the test chip 50 for testing, and the result signal returned by the test chip 50 is received. This can realize the switching of any port under different voltage environments, improve the chip's testing efficiency, and avoid possible signal conflict problems.

[0095] For example, the host 10 may include a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.

[0096] In some possible implementations, the method can be implemented by a processing component invoking computer-readable instructions stored in memory. In one example, the processing component includes, but is not limited to, a standalone processor, discrete components, or a combination of processors and discrete components. The processor may include a controller in an electronic device capable of executing instructions, and may be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions may be executed by hardware circuitry such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.

[0097] In one possible implementation, establishing the connection relationship between each input port and each output port in the port switching component 40 includes:

[0098] The input port number and output port number are determined based on the received port switching command;

[0099] Establish the connection relationship between each input port number and each output port number in the port switching component 40.

[0100] In one possible implementation, the switching assembly 20 includes a plurality of switches, the switches including any one of relays, reed switches, silicon controlled rectifiers, switching diodes, switching transistors, electronic bidirectional switches, and optocouplers; the level conversion assembly 30 includes a plurality of level converters, the level converters including unidirectional level converters or bidirectional level converters.

[0101] In one possible implementation, if each switch in the switching assembly 20 is a relay, the switching assembly 20 further includes a relay drive circuit adapted to each relay, wherein the relay includes a first host analog signal input terminal PA0, a second host analog signal input terminal PA1, a first channel input terminal Y0, a first channel output terminal Y1, a second channel input terminal Y0_11, a second channel output terminal Y1_11, and a drive signal receiving terminal, wherein...

[0102] The drive signal receiving terminal is used to receive the drive signal output by the relay drive circuit, wherein,

[0103] If the drive signal is high, the first channel input terminal Y0 and the first channel output terminal Y1 of the relay are connected to the first host analog signal input terminal PA0 and the second host analog signal input terminal PA1, respectively, to establish the analog test path;

[0104] If the drive signal is low, the first channel access terminal Y0 and the first channel output terminal Y1 of the relay are connected to the second channel access terminal Y0_11 and the second channel output terminal Y1_11, respectively, to establish the digital test path.

[0105] In one possible implementation, the relay drive circuit includes a first drive resistor R106, a second drive resistor R107, a third drive resistor R108, a first drive capacitor C63, and a first drive transistor Q9, wherein...

[0106] The first terminal of the first driving resistor R106 is used to receive the control signal transmitted from the host 10, and the second terminal of the first driving resistor R106 is connected to the first terminal of the second driving resistor R107, the first terminal of the first driving capacitor C63, and the gate of the first driving transistor.

[0107] The drain of the first driving transistor Q9 is connected to the driving signal receiving terminal, and the source of the first driving transistor Q9 is connected to the first terminal of the third driving resistor R108.

[0108] The second terminal of the second driving resistor R107, the second terminal of the first driving capacitor C63, and the second terminal of the third driving resistor R108 are grounded.

[0109] In one possible implementation, the method further includes at least one of the following steps:

[0110] During the testing of the test chip 50, the connection relationship between each input port and each output port is switched according to the port switching command;

[0111] To end the test of the test chip 50, disconnect the connection between each input port and each output port in the port switching component 40; disconnect the analog test path or digital test path, and set the level conversion component 30 to the output state.

[0112] In one possible implementation, if the level converter is a unidirectional level converter, then the host 10 is used to switch the input / output state of the level converter; or

[0113] If the level converter is a bidirectional level converter, the level converter will automatically switch between input and output states.

[0114] In one possible implementation, the port switching component 40 includes multiple analog switch array circuits, each analog switch array circuit including N input ports and M output ports, wherein each input port of each analog switch array circuit is connected to the other, and the host 10 is used to establish a connection between any input port and at least one output port, where N and M are both integers greater than 0.

[0115] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0116] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A multi-port chip testing device, characterized in that, The device includes a host, a switching assembly, a level conversion assembly, and a port switching assembly. The host is connected to the switching assembly and the level conversion assembly. The switching assembly and the level conversion assembly are both connected to the respective input ports of the port switching assembly. The respective ports of the test chip are connected to the respective output ports of the port switching assembly. The host is used for: Establishing the connection relationship between each input port and each output port in the port switching component includes: determining each input port number and each output port number according to the received port switching instruction; and establishing the connection relationship between the corresponding ports of each input port number and each output port number in the port switching component. An analog test path or a digital test path is established according to the type of the test signal. If the type of the test signal is an analog signal, an analog test path is established through the switching component and each input port of the port switching component. If the type of the test signal is a digital signal, a digital test path is established through the switching component and the level conversion component and each input port of the port switching component. The test signal is sent to the test chip for testing, and the result signal returned by the test chip is received.

2. The apparatus according to claim 1, characterized in that, The switching assembly includes multiple switches, which include any one of relays, reed switches, silicon controlled rectifiers, switching diodes, switching transistors, electronic bidirectional switches, and optocouplers. The level conversion assembly includes multiple level converters, which include unidirectional level converters or bidirectional level converters.

3. The apparatus according to any one of claims 1 to 2, characterized in that, If each switch in the switching assembly is a relay, the switching assembly further includes a relay driving circuit adapted to each relay, wherein the relay includes a first host analog signal input terminal, a second host analog signal input terminal, a first channel input terminal, a first channel output terminal, a second channel input terminal, a second channel output terminal, and a driving signal receiving terminal, wherein... The drive signal receiving terminal is used to receive the drive signal output by the relay drive circuit, wherein, If the drive signal is high, the first channel input terminal and the first channel output terminal of the relay are respectively connected to the first host analog signal input terminal and the second host analog signal input terminal to establish the analog test path; If the drive signal is low, the first channel access terminal and the first channel output terminal of the relay are connected to the second channel access terminal and the second channel output terminal, respectively, to establish the digital test path.

4. The apparatus according to claim 3, characterized in that, The relay driving circuit includes a first driving resistor, a second driving resistor, a third driving resistor, a first driving capacitor, and a first driving transistor, wherein, The first end of the first driving resistor is used to receive the control signal from the host, and the second end of the first driving resistor is connected to the first end of the second driving resistor, the first end of the first driving capacitor, and the gate of the first driving transistor. The drain of the first driving transistor is connected to the driving signal receiving terminal, and the source of the first driving transistor is connected to the first terminal of the third driving resistor. The second end of the second driving resistor, the second end of the first driving capacitor, and the second end of the third driving resistor are grounded.

5. The apparatus according to claim 3, characterized in that, The host is also used to perform at least one of the following steps: During the testing of the test chip, the connection relationship between each input port and each output port is switched according to the port switching command; To end the test of the test chip, disconnect the connection between each input port and each output port in the port switching component; disconnect the analog test path or digital test path, and set the level conversion component to the output state.

6. The apparatus according to claim 2, characterized in that, If the level converter is a unidirectional level converter, then the host is used to switch the input / output state of the level converter; or If the level converter is a bidirectional level converter, the level converter will automatically switch between input and output states.

7. The apparatus according to claim 1, characterized in that, The port switching component includes multiple analog switch array circuits, each of which includes N input ports and M output ports. The input ports of each analog switch array circuit are connected to each other. The host is used to establish a connection between any input port and at least one output port. N and M are both integers greater than 0.

8. A multi-port chip testing method, characterized in that, The method is applied to the host of a multi-port chip testing device. The device includes the host, a switching component, a level conversion component, and a port switching component. The host is connected to the switching component and the level conversion component. The switching component and the level conversion component are both connected to each input port of the port switching component. Each port of the test chip is correspondingly connected to each output port of the port switching component. The method includes: Establishing the connection relationship between each input port and each output port in the port switching component includes: determining each input port number and each output port number according to the received port switching instruction; and establishing the connection relationship between the corresponding ports of each input port number and each output port number in the port switching component. An analog test path or a digital test path is established according to the type of the test signal. If the type of the test signal is an analog signal, an analog test path is established through the switching component and each input port of the port switching component. If the type of the test signal is a digital signal, a digital test path is established through the switching component and the level conversion component and each input port of the port switching component. The test signal is sent to the test chip for testing, and the result signal returned by the test chip is received.

9. The method according to claim 8, characterized in that, The method further includes: During the testing of the test chip, the connection relationship between each input port and each output port is switched according to the port switching command; and / or To end the test of the test chip, disconnect the connection between each input port and each output port in the port switching component; disconnect the analog test path or digital test path, and set the level conversion component to the output state.

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