Method and system for enhancing the running speed and security of SHA256 algorithm

Abstract

The application provides a method and system for enhancing the operation speed and security of SHA256 algorithm, and the method is applied to an SHA256 encryption circuit; the process of logical operation of any message in the logical operation of the message block in sequence is specifically that a count control unit is used to count and determine the number of cyclic compression processing times of any message block; when the cyclic compression processing of any message block is performed for the first 16 times, the corresponding data in the message block is transmitted to the cyclic compression module by the message preprocessing module to perform cyclic compression and output the cyclic compression result. The application has the beneficial effects that the linear structure of the traditional SHA algorithm is changed into a fork tree structure by changing the data flow direction; the operation speed of the algorithm is improved by reducing the path of the data flow; the count control of the message expansion and cyclic compression is placed in the upper module, and the operation speed of the algorithm is improved by reducing the used registers and occupied memory.

Description

Technical Field

[0001] This invention relates to the technical field of cryptography applied in the security field, and in particular to methods and systems for enhancing the running speed and security of the SHA256 algorithm. Background Technology

[0002] SHA256 is a sub-algorithm of SHA-2. SHA-2, short for Secure Hash Algorithm 2, is a cryptographic hash function algorithm standard developed by the U.S. National Security Agency. It belongs to the SHA algorithm family and is the successor to SHA-1. SHA-2 can be further divided into six different algorithm standards, including: SHA-224, SHA-256, SHA-384, SHA-512, SHA-512 / 224, and SHA-512 / 256. These variants share a consistent basic algorithm structure, with only minor differences in the length of the generated digest and the number of iterations.

[0003] The SHA256 algorithm has a wide range of applications, and it's used in many areas of security. Because of its widespread use, numerous attack methods have emerged. SHA256 applications are relatively low-level and fundamental, often requiring extensive repetition. Each smallest unit of computation requires at least 48 expansion calculations and 64 rounds of compression. Therefore, even small modifications can significantly speed up the entire computation process. However, the logical functions and formulas involved in the computation are difficult to modify, and the resulting efficiency gains are hard to observe. Therefore, current speed-up efforts for the SHA256 algorithm must focus on structural improvements. Even a small increase in computational speed in each operation can have a significant impact. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the aforementioned existing problems, the present invention is proposed.

[0006] Therefore, the technical problems solved by this invention are: first, to solve the problem of increasing the running speed of the SHA256 algorithm; and second, to solve the security problem.

[0007] To solve the above technical problems, the present invention provides the following technical solution: a method for enhancing the running speed of the SHA256 algorithm, the method being applied to a SHA256 encryption circuit; comprising the following steps: initial data is grouped into message blocks in a message preprocessing module; logical operations are sequentially performed on several message blocks to generate 256-bit hash values; the process of sequentially performing logical operations on any message in several message blocks specifically involves using a counting control unit to count and determine the number of cyclic compression processes for any message block and determine the data flow direction; during the first sixteen cyclic compression processes on any message block, the corresponding data within the message block is transmitted from the message preprocessing module to the cyclic compression module for cyclic compression and the cyclic compression result is output; during the first seventeen to sixty-fourth cyclic compression processes on any message block, the message block is transmitted to the message expansion module for message expansion, and then the message expansion result is transmitted to the cyclic compression module for cyclic compression and the cyclic compression result is output; during the sixteenth cyclic compression process on any message block, the message block is transmitted to the message expansion module for message expansion simultaneously with the cyclic compression and before the seventeenth cyclic compression.

[0008] Preferably, the method further includes an improvement step for the counting control unit: setting the counting control unit within the message preprocessing module; unifying the use of the same set of counting registers in the counting control unit for the message expansion module and the cyclic compression module; deleting the eight sets of registers for hash values ​​in the original SHA256 algorithm and modifying the data transmission path to replace this storage behavior; and connecting the message expansion module and the cyclic compression module to the message preprocessing module.

[0009] Preferably, the counting control unit determines the data flow direction by the following steps: in a single message block, during the first fifteen counts, the message preprocessing module transmits data only to the cyclic compression module; during the sixteenth count, the message preprocessing module transmits data to both the message expansion module and the cyclic compression module; and during the seventeenth to sixty-fourth counts, the message preprocessing module transmits data only to the message expansion module.

[0010] Preferably, the counting control unit's counting judgment includes the following steps: starting the count from 0, i.e., the first time is when the count is 0; if the count is less than or equal to 15, then 16 groups of 32-bit data are input to the cyclic compression module for multiple steps of cyclic compression processing; if the count is greater than or equal to 15, then the data block is processed by message expansion to form 48 groups of 32-bit data, and then the data is transmitted to the cyclic compression module for cyclic compression processing.

[0011] Preferably, the message expansion process of the message expansion module includes the following expansion steps: expanding the 16 groups of 32-bit data into 48 groups of 32-bit data; in the logical operation process, performing logical operations on multiple groups of 32-bit data in each operation and finally outputting a group of 32-bit byte functions; then performing cyclic compression processing on the 48 groups of 32-bit data respectively, and storing the results in 8 groups of 32-bit registers; the cyclic compression module obtains a group of 32-bit data from the message expansion module each time and performs operations on the group of data.

[0012] Preferably, performing logical operations on message blocks sequentially further includes the following steps: the last set of data output after each message block has completed all processing is involved in the cyclic compression operation of the first sixteen processing steps in the processing of the next message block; when there is only one message block, the last set of data output after it has completed all processing is output as the final 256-bit hash value composed of 8 sets of 32-bit data.

[0013] Preferably, the actual operation process of inputting variable-length initial data includes the following steps: S1: Preprocess the initial data to obtain several 16 groups of 32-bit message blocks; S2: Count and judge any 16 groups of 32-bit message blocks, and perform corresponding cyclic compression or cyclic compression and message expansion processing according to the judgment result; perform 64 processing cycles to obtain the final 8 groups of 32-bit data and store them in 8 groups of 32-bit registers; S3: If step S1 only generates a single message block, execute step S4; if step S1 generates multiple message blocks, participate the 8 groups of 32-bit data obtained in S2 in the cyclic compression operation of step S2 and continue to repeat step S2 until all message blocks are processed; S4: Output the stored value of the 8 groups of 32-bit registers, that is, the encrypted 256-bit hash value.

[0014] Preferably, the message preprocessing of the initial data includes the following steps: dividing the initial data of variable length into blocks and adding padding bits to each data block until the data length satisfies the remainder of 448 after modulo 512, and putting the excess data into the next data block; adding 64 bits of length information to the processed data blocks to form several groups of 16 groups of 32-bit message blocks.

[0015] This invention also provides a system for enhancing the running speed of the SHA256 algorithm, comprising a message preprocessing module, a message expansion module, and a cyclic compression module. The message expansion module and the cyclic compression module are both connected to the message preprocessing module. Each module includes a data input unit and a data output unit. The message preprocessing module includes a data processing unit, and both the message expansion module and the cyclic compression module include logic operation units. The data output unit of the message preprocessing module further includes a counting control unit, which is used to count and determine the number of cyclic compression cycles for message blocks and control the data flow based on the determination result. The message preprocessing module is used to preprocess the input initial data and to transmit the processed data to the message expansion module and the cyclic compression module. The message expansion module receives the data transmitted by the message preprocessing module and performs message expansion. The cyclic compression module receives the data transmitted by the message preprocessing module and performs cyclic compression.

[0016] The present invention also provides a method for enhancing the security of the SHA256 algorithm, including the method for enhancing the running speed of the SHA256 algorithm as described above, which sets a custom balance improvement between security and running speed during message preprocessing, including improvements that do not affect speed and power consumption at all, improvements that do not affect speed but increase power consumption, and improvements that affect both speed and power consumption.

[0017] The beneficial effects of this invention are as follows: by changing the data flow direction, the linear structure of the traditional SHA algorithm is changed to a branch tree structure; the running speed of the algorithm is improved by reducing the number of paths the data flows through; the counting control of message expansion and cyclic compression is placed in the upper-level module; the running speed of the algorithm is improved by reducing the number of registers used and the memory occupied; register resources are reallocated, reducing the number of registers used only for data storage; and the running speed of the algorithm is improved by reducing the number of registers used and the memory occupied. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0019] Figure 1 This is a schematic diagram illustrating the principle and flow of the SHA256 algorithm in the prior art described in this invention;

[0020] Figure 2 This is a schematic diagram illustrating the principle and structure of the traditional SHA256 algorithm of this invention;

[0021] Figure 3 The principle structure of the improved SHA256 algorithm in this invention;

[0022] Figure 4 This is a schematic diagram of the variable-length initial data encryption process described in this invention;

[0023] Figure 5 This is a schematic diagram of the circuit structure of the SHA256 algorithm described in this invention. Detailed Implementation

[0024] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0025] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0026] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0027] This invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of this invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0028] Furthermore, in the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] Example 1

[0031] This embodiment improves the SHA256 algorithm to enhance its computational speed and security in practical applications, referring to... Figure 1 As illustrated, the existing SHA256 algorithm mainly includes message preprocessing, message expansion, and cyclic compression. The first step is message preprocessing, which consists of two steps: appending padding bits and appending length. For all messages, the first bit is padded to 1, and then all bits are padded to 0 until the length satisfies the remainder of 448 when modulo 512. The excess is placed in the next message block. Then, 64 bits of length information are appended to make it a series of 512-bit message blocks.

[0032] Secondly, there is message expansion. Each 512-bit message block consists of 16 groups of 32-bit 4-byte data. After the following logical operations, it is expanded into 64 groups. In the logical operations, each function controls the 32-bit bytes and outputs 32-bit bytes.

[0033] Finally, there is cyclic compression. The 64 groups of 4-byte data after message expansion are compressed starting from the first group. Each loop operation operates on a 32-bit group and outputs 32 bits for the next operation. This process uses 8 initial 32-bit hash values ​​and 64 32-bit hash constants. Ultimately, each message block receives 8 32-bit hash values ​​from the operation. If there are multiple message blocks, the hash value of the previous message block is used as the initial hash value for the next 64 loop operations until a final 256-bit hash value is obtained.

[0034] The SHA256 algorithm has a wide range of applications, and it's used in many areas of security. Because of its widespread use, numerous attack methods have emerged. SHA256 applications are relatively low-level and fundamental, often requiring extensive repetition. Each smallest unit of computation requires at least 48 expansion calculations and 64 rounds of compression. Therefore, even small modifications can significantly speed up the entire computation process. However, the logical functions and formulas involved in the computation are difficult to modify, and the resulting efficiency gains are hard to observe. Therefore, current speed-up efforts for the SHA256 algorithm must focus on structural improvements. Even a small increase in computational speed in each operation can have a significant impact.

[0035] This embodiment addresses the SHA256 algorithm described above. In the integration of the SHA256 algorithm IP written in Chisel, it was found that some statements in the IP do not affect the actual calculation but occupy memory reclaimed by the GC. These statements have the following characteristics: they are only used for data caching, and each statement alone will not cause an error. Even several statements used together will not cause an error as long as the number of statements does not exceed a certain limit. Only when a certain number of statements are used or all of them are used will an error occur when the Chisel syntax is compiled into a Verilog file: GC overhead limit exceeded, i.e., GC memory overflow.

[0036] These statements are located in the loop compression section of the algorithm structure. They serve to temporarily store the hash values ​​from the previous 64 loop compression processes so that they can be used as the new initial hash values ​​in the next message block operation. In fact, the registers during operation also store these results and use them directly in the next operation. Therefore, deleting these statements will not affect the operation process at all.

[0037] This flaw arises because the relationship between the message expansion and compression modules is completely linear; all data must first pass through the message expansion module and then the compression module. Considering that the data storage effect is merely a storage method, and that error correction mechanisms are not necessary in all algorithms, removing this part is feasible. During the cyclic compression operation, most traditional SHA256 algorithms, while lacking this storage mechanism, still follow a linear data flow consistent with the IP address. Although this algorithm has wide applications, it can be omitted for applications that do not require this feature or where accuracy is not particularly stringent.

[0038] Furthermore, in the IP integration of this embodiment, the initial data is not processed in the message expansion section, and the compression module does not interfere with the message expansion module during operation. Therefore, having all data pass through the message expansion module is essentially unnecessary, just like redundant statements. Additionally, the more paths data traverses, the more time it takes. For example, transferring data from one register to another takes one clock cycle, and transferring data from one module to another requires inter-register operations and handshake signal control. Therefore, reducing data paths and improving the algorithm structure can increase the algorithm's running speed.

[0039] To address the aforementioned shortcomings, this embodiment demonstrates a feasible approach to improve the algorithm's running speed by modifying its linear structure into a branch tree structure and optimizing its internal logic. The specific improvements consist of two parts: First, the message expansion module is separated. Message blocks that have undergone message preprocessing can bypass this module and be directly passed from preprocessing to the compression module, reducing the path taken by these messages and decreasing at least one clock cycle and the handshake time between modules. Previously, data flowed linearly between the three modules; after the improvement, the first sixteen loops can be directly compressed after preprocessing, while the remaining forty-eight loops undergo actual computation by the message expansion module before reaching the compression part. Second, after the structural improvement, the counting registers that were originally present in both modules can be moved to the higher-level module. This changes the separate counting control of the two modules to joint control by the higher-level module. This optimization also reduces the number of duplicate counting registers and contributes to a slight speed improvement (previously, the counting registers of the two modules were...). After optimization, the counting part only requires one counting part, thus reducing one set of counting registers. Originally, the counting parts of the two modules were basically the same, and they were also consistent in the timing checks during normal operation (hence the term "repetitive"). Furthermore, the part of the message extension module that determines the data path based on the count is also moved to the next higher-level module. That is, in the first fifteen counts, the data is directly sent to the compression module. It is particularly important to note that in the sixteenth compression cycle, the data needs to be sent to both the compression module (for the sixteenth compression) and the message extension module (for the generation of the seventeenth set of data) simultaneously. Only in the seventeenth compression cycle does the data path completely change to the same data path as the traditional algorithm. Because the data path changes from linear to branched, it exhibits a branching phenomenon, while there are still intersections at the branches. Therefore, this embodiment refers to it as a branch tree structure.

[0040] Therefore, referring to Figure 2-3 This illustration shows the principle structure of the algorithm in this embodiment and the difference from traditional algorithms. The purpose of this embodiment is to solve the security problem and increase the running speed of the SHA256 algorithm. It proposes a method to enhance security and running speed by improving the algorithm structure. Specifically, it includes the following steps:

[0041] S1: Initial data is grouped and output in the message preprocessing module;

[0042] S2: The linear structure of the traditional algorithm is changed to a branch tree structure, and the initial data is divided into two parts after preprocessing;

[0043] S3: After grouping, the two parts of data are counted and judged in the message preprocessing module using the counting control unit to determine the data flow direction;

[0044] S4: A portion of the data flows into the message expansion module but is not expanded. The data goes directly from the message preprocessing module to the cyclic compression module. At this time, the message expansion module is temporarily not working and does not include the sixteenth cyclic compression.

[0045] S5: Another part of the data flows into the message expansion module to expand the 512-bit message block, and then the seventeenth cyclic compression is performed. The message expansion module needs to start expanding at the same time during the sixteenth compression to generate the seventeenth group of data. Connect the previous data to perform a complete sixty-four cyclic compression operation to generate a 256-bit hash value.

[0046] S6: Apply the improved SHA256 algorithm to the algorithm circuit structure.

[0047] In step S2, for the improvement of the separate counting operation of the message expansion module and the loop compression module in some syntax, the counting register part that originally existed in both modules can be placed in the upper-level module. That is, the message expansion module and the loop compression module use the same set of counting registers in the counting control unit.

[0048] It should be noted that traditional algorithms use eight registers to store the hash values ​​obtained in each of the 64 iterations. However, these registers only change in the last iteration of each message block. In this embodiment, by changing the linear structure of the traditional algorithm to a branch tree structure, and because the branch tree structure is used and the data enters the next iteration after the same operation, it is possible to optimize (meaning to optimize away from the eight registers used in the traditional algorithm for hash values, modifying the calculation formula to replace this storage step). This demonstrates the feasibility of the optimization. The registers only serve as data storage and transfer points and do not participate in the actual calculation. The optimized operation... The calculation result remains consistent with the result before optimization. After modifying the data flow, the original linear structure becomes a branch tree structure (some registers are deleted, moved, or modified). At the same time, the last group of A63B63C63D63E63F63G63H63 is replaced by calculation. The above is the modified data path. Calculation replacement means calling the previous calculation formula to achieve the same effect. The calculation process is also consistent with the previous traditional calculation. For algorithms with different implementation syntax, i.e., algorithm IPs with other syntax, as long as the registers stored in this embodiment are available and there are no other cooperating modules, optimization can be performed.

[0049] Simultaneously, in this step, both the message expansion module and the cyclic compression module are connected to the preprocessing module, placing the counting control of message expansion and cyclic compression in the upper-level module, that is, performing counting statistics and controlling the data flow in the preprocessing module.

[0050] More specifically, the counting determination in step S2 includes the following steps:

[0051] Counting starts from 0, meaning the first time is when the count reaches 0;

[0052] If the count is less than or equal to 15, then 16 groups of 32-bit data are input into the compression module and subjected to multiple steps of cyclic compression processing with 8 groups of 32-bit registers updated each time.

[0053] If the count is greater than or equal to 15, the data block is expanded to form 48 groups of 32-bit data, and then the data is transmitted to the compression module for cyclic compression.

[0054] Reference Figure 4 The illustration shows the encryption process of variable-length initial data in this embodiment. It starts counting from 0 for the first time. Based on the above counting determination, this embodiment also includes a step to enhance the security of the initial data.

[0055] SS1: Perform message preprocessing on the initial data, which consists of two steps: appending padding bits and appending length. For all messages, first pad the first bit to 1, then pad with 0, until the length satisfies the remainder of 448 when modulo 512. Any excess is placed in the next message block. Then, append 64 bits of length information (the binary representation of the actual message length value) to form several groups of 512 bits (16 groups of 32 bits) of data.

[0056] SS2.1: Counts 16 groups of 32-bit message blocks (starting from 0, i.e., the first count is 0). If the count is less than or equal to 15, these 16 groups of data are input to the compression module for multi-step cyclic compression processing with the 8 groups of 32-bit registers updated in each compression cycle. If the count is greater than or equal to 15, the data blocks undergo message expansion processing to form 48 groups of 32-bit data, which are then transmitted to the compression module for cyclic compression processing. The specific steps of message expansion are as follows: the 16 groups of 32-bit data are expanded into 48 groups (the traditional algorithm expands to 64 groups, but after structural improvement, 48 groups are actually used) of 32-bit data through certain logical operations. During the logical operation, each function in each operation operates on 32-bit bytes of data, combining multiple functions using multiple groups of data and finally outputting a single 32-bit byte function. Then, the 48 groups of 32-bit data are cyclically compressed, and the result is stored in 8 groups of 32-bit registers before entering the next cyclic compression processing module.

[0057] SS2.2: The core of the cyclic compression processing module consists of eight 32-bit registers and multiple operational logic formulas. In the first loop of the first 512-bit message block, the register data consists of eight initial hash values, obtained from the first 32 decimal places of the square root of the first eight prime numbers (1, 2, 3, 5, 7, 11, 13, 17). Subsequent compression operations involve taking one set of transmitted data (64 sets in total, including 16 sets directly from the preprocessing module and 48 sets from the message expansion module) and one set of hash constants (64 sets in total, obtained from the first 32 decimal places of the cube root of the first 64 prime numbers) and performing four logical operations with the eight registers, including XOR and circular right shift.

[0058] SS3: Finally, for each message block, i.e. every 64 cycles of compression, we get the last 8 groups of 32-bit data. If it is a single message block, we skip S4 and directly output these data as the final 256-bit hash value. If it is multiple message blocks, we use it as the initial hash value of the next message block and continue to repeat the processing steps SS2.1 and SS2.2 until all message blocks are processed.

[0059] SS4: Outputs the stored values ​​of 8 groups of 32-bit registers, which are the encrypted 256-bit hash values.

[0060] It should be noted that in a single message block in this embodiment, during the first fifteen loops, the preprocessing module of the counting control section only transmits data to the loop compression module; during the sixteenth loop, the preprocessing module transmits data to both the message expansion module and the loop compression module; and during the seventeenth to sixty-fourth loops, the preprocessing module only transmits data to the message expansion module. This part is data splitting processing, which can be understood as follows: before processing, it is the input data of the algorithm; after processing, it is divided into two paths. The first sixteen counts are not transmitted to both modules simultaneously, but are directly transmitted to the loop compression module; the last forty-eight counts transmit data to the message expansion module.

[0061] All data output from the message expansion module is transmitted to the cyclic compression module. The cyclic compression module's data input unit receives a set of 32-bit data each time and performs calculations on each set. Simultaneously, the last set of data in each message block's calculation process is updated with a new initial hash value in the next message block. When there is only one message block, it is output as a 256-bit hash value consisting of eight sets of 32-bit data. Temporally, this part belongs to the last forty-eight loops during counting; spatially, it represents the path of data from the message expansion module to the cyclic compression module after splitting, i.e., the part that flows through the message expansion module, compared to the different processing steps of the previous sixteen paths.

[0062] Example 2

[0063] The difference between this embodiment and the above embodiments is that, while enhancing the running speed of the SHA256 algorithm in Embodiment 1, a more detailed description of the operation for improving security is provided. There is no specific pattern; it only describes the specific features of three different methods for improving security. At the same time, different methods can be customized to achieve the purpose of improving security.

[0064] The definition of balancing safety and operating speed improvements includes improvements that have no impact on speed and power consumption, improvements that do not affect speed but increase power consumption, and improvements that affect speed and increase power consumption, as detailed below:

[0065] Improvements that do not affect speed or power consumption at all:

[0066] In the processing of long messages, the storage location of the effective information is reversed. That is, the processing of long information such as 00000000…00101000 is changed to 0001 0100…00000000. The advantage is that in actual operation, the processing of this information can still produce an irreversible 256-bit hash value. Moreover, compared with the result without improvement, it avoids simple collisions in traditional algorithms and can also prevent attacks in complex collisions.

[0067] Improvements that do not affect speed but increase power consumption:

[0068] The operation of padding with 1s and 0s is reversed during data preprocessing. That is, the processing of 10101000…00000000 (initial data is 1010) is changed to 10101111…11111111. The advantage is that the processing of this information can still produce an irreversible 256-bit hash value in actual operation. Moreover, compared with the result without improvement, it avoids simple collisions in traditional algorithms and can also prevent attacks in complex collisions. The disadvantage is that 1 and 0 represent on and off states in the circuit. The original 0 is more than 1, that is, there are more off circuit structures than on circuit structures, while the latter is the opposite, with more on circuit structures than off circuit structures.

[0069] Improvements that impact speed and increase power consumption:

[0070] When filling message blocks, a special string is added at a specific position. This position can be at the beginning, the end, or even a calculated position (such as the nth position after the valid information). For example, the processing of 1010100000000000…00000000 (initial data is 1010) is changed to 11011011 10101000…00000000 (the special string is 11011011). Similarly, the special string is added at the end. The advantage is that the processing of this information still produces an irreversible 256-bit hash value in actual computation. Compared to the unimproved result, it avoids simple collisions in traditional algorithms and also prevents attacks in complex collisions, making it more secure than the previous two improvements. The disadvantage is that it reduces the amount of data involved in the computation. For some data with a critical length, an additional message block is added, resulting in an additional 64 loops, which affects the running speed and power consumption.

[0071] The above process is an improvement on the initial data in the preprocessing module, and is referred to again. Figure 2-3 The diagram illustrates the general structure of this embodiment and the difference from traditional algorithms. The following is a detailed explanation of how structural optimizations improve the algorithm's running speed.

[0072] The traditional linear structure of the algorithm is changed to a branch tree structure. This means that after the aforementioned custom improvement, the data does not all flow to the message expansion module. Instead, it flows in two parts. The first part refers to the first sixteen compression loops, where the message expansion module does not substantially modify the data, but the data still passes through this point. In the improved branch tree structure, the data goes directly from the preprocessing module to the cyclic compression module, and the message expansion module can temporarily stop working during this time (excluding the sixteenth loop). The second part refers to the last forty-eight loops, where the expansion module needs to expand the 512-bit message block before the seventeenth cyclic compression can begin. To avoid the compression module starting to request expanded data before the expansion module has completed expanding the current data set, the expansion module needs to begin expanding during the sixteenth compression to generate the seventeenth data set. This, combined with the previous data, completes sixty-four cyclic compression operations to generate a 256-bit hash value.

[0073] In this embodiment, the linear structure of the traditional SHA algorithm is changed to a branch tree structure by altering the data flow direction; the algorithm's running speed is improved by reducing the number of paths the data flows through; the counting control for message expansion and cyclic compression is placed in a higher-level module; the algorithm's running speed is improved by reducing the number of registers used and the amount of memory occupied; register resources are reallocated, reducing the number of registers used solely for data storage; and the algorithm's running speed is improved by reducing the number of registers used and the amount of memory occupied.

[0074] Therefore, the key improvements in this embodiment are: 1. Changing the data flow direction, replacing the linear structure of the traditional SHA algorithm with a branch tree structure; improving the algorithm's running speed by reducing the number of paths the data flows through; 2. Placing the counting control for message expansion and loop compression in the upper-level module; improving the algorithm's running speed by reducing the number of registers used and the amount of memory occupied; 3. Reallocating register resources, reducing the number of registers used solely for data storage; improving the algorithm's running speed by reducing the number of registers used and the amount of memory occupied.

[0075] From the perspective of improving running speed, improvements to the algorithm structure are not limited to the language used to describe the algorithm. Different languages ​​describe different implementations of the algorithm. However, after optimizing the linear structure into a branch tree structure, the basic structure can theoretically simplify the part of the message extension module where data is not actually processed but only transmitted. This can reduce at least one clock cycle for data transmission in the first sixteen loops. Furthermore, if there is a handshake protocol, it can reduce one handshake signal, thereby improving the running speed of the algorithm. In addition, the separate connection and control between two modules is optimized into a common connection between three modules and merged into the same counting control logic.

[0076] Example 3

[0077] Based on the method for enhancing the running speed of the SHA256 algorithm proposed in the above embodiments, this embodiment proposes a system for implementing the method. The above method is implemented based on the system proposed in this embodiment. Figure 5 The diagram illustrates the circuit structure block diagram of this system. Specifically, the system proposed in this embodiment includes...

[0078] The system includes a message preprocessing module, a message expansion module, and a loop compression module. Each module includes a data input unit and a data output unit. The preprocessing module includes a data processing unit, and both the message expansion module and the loop compression module include a logic operation unit. The data output unit of the preprocessing module includes a counting control unit.

[0079] Specifically, the message expansion module and the loop compression module are both connected to the message preprocessing module. Each module includes a data input unit and a data output unit. The message preprocessing module includes a data processing unit, and both the message expansion module and the loop compression module include a logic operation unit.

[0080] The data output unit of the message preprocessing module also includes a counting control unit, which is used for counting judgment of message cyclic compression and to control the data flow based on the judgment result; the message preprocessing module is used to preprocess the input initial data and to transmit the processed data to the message expansion module and the cyclic compression module; the message expansion module is used to receive the data transmitted by the message preprocessing module for message expansion; the cyclic compression module is used to receive the data transmitted by the message preprocessing module for cyclic compression.

[0081] It should be noted that the improved SHA256 algorithm structure includes a message preprocessing module, a message expansion module, and a cyclic compression module. Each module consists of a data input unit, a data processing unit (logic operation unit), and a data output unit, as shown in the figure. Within a single message block, in the first fifteen loops, the message preprocessing module only transmits data to the cyclic compression module. In the sixteenth loop, the message preprocessing module transmits data to both the message expansion module and the cyclic compression module (to ensure clock accuracy and logical continuity). From the seventeenth to the sixty-fourth loop, the message preprocessing module only transmits data to the message expansion module. All data output from the message expansion module is transmitted to the cyclic compression module. The data input unit of the cyclic compression module receives a set of 32-bit data each time and performs operations on this set of data. Figure 5 This only shows the overall effect. The initial value is updated in each message block and does not represent the specific calculation process. At the same time, the last set of data in the calculation process of each message block is updated to a new hash initial value in the next message block. When there is only one message block, it is output as the most positive 256-bit hash value (composed of 8 sets of 32-bit data).

[0082] Example 4

[0083] In this embodiment, the improved SHA256 algorithm is described in practical applications, such as storing user passwords in databases, preventing file tampering, digital signatures, constructing pseudo-random number generators, and deduplication in high-speed data transfers. These applications significantly improve the processing speed of these applications. Specifically,

[0084] 1. Store user passwords in the database: Output the user's password to the database using a one-way hash function. The hash value is compared each time the user logs in. Due to the irreversible nature of one-way hash functions, even if the database is stolen, the user's information cannot be obtained.

[0085] 2. Preventing File Tampering: Most websites providing download services currently offer the SHA256 value of the files. This is because one-way hash functions have anti-tampering properties. If the SHA256 value of the downloaded file does not match the value provided by the website, the file may have been modified, possibly containing viruses or being pirated.

[0086] 3. Digital signatures are the digital implementation of actions like signing and stamping in the real world. The processing of digital signatures is very time-consuming; therefore, the entire message content is generally not directly signed using a digital signature. Instead, a hash value for the message is first calculated using a one-way hash function (SHA256), and then this hash value is encrypted using a private key to obtain the digital signature.

[0087] 4. Constructing a pseudo-random number generator: The random numbers used in cryptography need to possess the property that "it is practically impossible to predict future random number sequences based on past random number sequences." To ensure unpredictability, a pseudo-random number generator can be constructed using the one-way nature of the one-way hash function (SHA256).

[0088] 5. Instant Deduplication: When a user uploads a file, the one-way hash value of the file is first calculated. This value is then searched in the database. If a duplicate value exists, it means that the same file already exists, so there's no need to upload it again; it can be shared directly. This significantly reduces server load, drastically reduces storage space, and achieves deduplication.

[0089] Furthermore, the actual effects of the method described in this application will be explained.

[0090] Regarding the security improvements, traditional algorithms largely utilize the one-way irreversibility of the SHA256 algorithm in practical applications to achieve a function similar to a "digital fingerprint." Because this algorithm is simple to implement, has good one-wayness, and is widely used, its actual user base is large, and attack methods targeting it are well-established; there are even databases specifically designed to attack traditional SHA256 algorithms. The solution in this application does not affect the algorithm's logical function or one-way irreversibility. Therefore, there was some debate regarding security during internal discussions: if the security improvement is due to the addition of different processing methods, then attackers only need to add these processing methods synchronously, which is essentially the same as attacking traditional solutions, only increasing the difficulty and collision rate. The method in this application can effectively improve security, and the specific implementation scheme does not need to be fully disclosed to attackers, thus it also has certain value.

[0091] For the acceleration aspects of the improved algorithm and the practical application of traditional algorithms, it is necessary to understand them in conjunction with the circuit structure: for the circuit implementing this algorithm, adding registers in data transmission increases transmission time. The acceleration effect of the optimization method in this application varies depending on different implementation methods and scenarios. Theoretically, reducing the number of registers in the counting section and part of the data path improves the speed by at least 1 / 32 (for fuzzy path calculation) in terms of data flow improvement alone, thus having certain value.

[0092] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can be implemented using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein such a storage medium causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0093] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0094] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described herein, the invention also includes the computer itself. A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the converted data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on a display.

[0095] As used herein, the terms “component,” “module,” “system,” etc., are intended to refer to a computer-related entity, which may be hardware, firmware, a combination of hardware and software, software, or running software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a running thread, a program, and / or a computer. As an example, an application running on a computing device and the computing device itself can both be components. One or more components may reside in a running process and / or thread, and components may be located in a single computer and / or distributed among two or more computers. Furthermore, these components are capable of execution from various computer-readable media having various data structures thereon. These components may communicate locally and / or remotely via signals, such as based on one or more data packets (e.g., data from a component that interacts with a local system, another component in a distributed system, and / or signals that interact with other systems via a network such as the Internet).

[0096] It should also be understood that the present invention is described through embodiments, and the embodiments are only clear and complete descriptions of the technical solutions proposed in the claims of the present invention, that is, explanations of the claims. Therefore, when judging whether the technical solutions recorded in the specification of the present invention are sufficiently disclosed, the purpose and core essence of the solutions defined by the claims should be fully considered. There are necessarily other technical problems in the specification that are unrelated to the core technical problem solved by this embodiment. The corresponding technical features and technical solutions are not included in the essence of this embodiment and are non-essential technical features. Therefore, the implicit disclosure can be referred to. Those skilled in the art can fully implement them by combining existing technology and common knowledge. Therefore, there is no need to describe them in detail.

[0097] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for enhancing the running speed of SHA256 algorithm, the method being applied to an SHA256 encryption circuit. The method comprises the following steps, initial data is grouped and formed into a message block in a message preprocessing module; a logical operation is sequentially performed on the message block to generate a 256-bit hash value; characterized in that the logical operation process of any message block in the sequential logical operation of a plurality of message blocks is specifically, a count control unit is used to count and determine the number of cyclic compression processes of any message block and determine the data flow direction; when the first sixteen cyclic compression processes of any message block are performed, the corresponding data in the message block is transmitted from the message preprocessing module to the cyclic compression module for cyclic compression and output of the cyclic compression result; when the seventeenth to sixty-fourth cyclic compression processes of any message block are performed, the message preprocessing module transmits the message block to the message expansion module for message expansion, and then transmits the message expansion result to the cyclic compression module for cyclic compression and output of the cyclic compression result; when the sixteenth cyclic compression process of any message block is performed, the message preprocessing module performs cyclic compression while transmitting the message block to the message expansion module for message expansion before the seventeenth cyclic compression to generate the seventeenth set of data, and connects the previous data for complete sixty-fourth cyclic compression operation to generate a 256-bit hash value.

2. The method for enhancing the running speed of SHA256 algorithm according to claim 1, wherein: Further comprising an improvement step of the count control unit, the count control unit is arranged in the message preprocessing module; the message expansion module and the cyclic compression module use the same set of count register in the count control unit; eight sets of registers of hash values in the original SHA256 algorithm are deleted, and the data transmission path is modified to replace the storage behavior of this step; the message expansion module and the cyclic compression module are connected with the message preprocessing module at the same time.

3. The method for enhancing the running speed of SHA256 algorithm as claimed in claim 1, wherein: The count control unit determines the data flow direction, comprising the following steps, in a single message block, the count control unit counts the first fifteen times, and in this stage, the message preprocessing module only transmits data to the cyclic compression module; in the sixteenth counting stage of the count control unit, the message preprocessing module simultaneously transmits data to the message expansion module and the cyclic compression module; in the seventeenth to sixty-fourth counting stage of the count control unit, the message preprocessing module only transmits data to the message expansion module.

4. The method for enhancing the running speed of SHA256 algorithm of claim 1, wherein: The count control unit count judgment comprises the following steps, counting starts from 0, that is, the first time when the count is 0; if the count is less than or equal to 15, 16 sets of 32-bit data are input to the cyclic compression module for multiple-step cyclic compression processing; if the count is greater than or equal to 15, the data block is processed by message expansion to form 48 sets of 32-bit data, and then the data is transmitted to the cyclic compression module for cyclic compression processing.

5. The method for enhancing the running speed of SHA256 algorithm according to claim 4, wherein: The message expansion process of the message expansion module comprises the following expansion steps, the 16 sets of 32-bit data are expanded into 48 sets of 32-bit data, and in the logical operation process, a plurality of sets of 32-bit data are logically operated in each operation and finally output a set of 32-bit byte functions; Then 48 groups of 32-bit data are cyclically compressed respectively, and the results are stored in 8 groups of 32-bit registers; The cyclic compression module obtains one group of 32-bit data from the message expansion module each time, and performs operation on the group of data.

6. The method for enhancing the running speed of SHA256 algorithm as claimed in claim 4, wherein: The logical operation on the message blocks in turn further includes the following steps, The last group of data output after each message block completes the whole processing participates in the cyclic compression operation of the first sixteen times of processing in the processing of the next message block; When there is only one message block, the last group of data output after the whole processing of the message block is completed is output as the final 256-bit hash value composed of 8 groups of 32-bit data.

7. The method for enhancing the running speed of SHA256 algorithm as claimed in claim 6, wherein: The actual running process of inputting the initial data of indefinite length includes the following steps, S1: performing message preprocessing on the initial data to obtain a plurality of 16 groups of 32-bit message blocks; S2: performing counting judgment on any 16 groups of 32-bit message blocks, and performing corresponding cyclic compression or cyclic compression and message expansion processing according to the judgment result; performing 64 times of processing to obtain the last 8 groups of 32-bit data and store the 8 groups of 32-bit data in 8 groups of 32-bit registers; S3: if step S1 only generates a single message block, step S4 is executed, if step S1 generates a plurality of message blocks, the 8 groups of 32-bit data obtained in step S2 participate in the cyclic compression operation of step S2 and continue to repeat step S2 until all the message blocks are processed; S4: outputting the storage value of the 8 groups of 32-bit registers, that is, outputting the 256-bit hash value obtained by encryption.

8. The method for enhancing the speed of SHA256 algorithm operation as recited in claim 1, wherein: The message preprocessing of the initial data includes the following steps, The indefinite-length initial data is divided into blocks, and a padding bit value is added to each data block until the data length satisfies the condition that the remainder after 512 is taken as the modulus is 448, and the excess data is put into the next data block; The length information of the processed data blocks is added to form a plurality of 16 groups of 32-bit message blocks.

9. A system for enhancing the speed of operation of the SHA256 algorithm, characterized in that: The message preprocessing module, the message expansion module and the cyclic compression module, The message preprocessing module is used for grouping the initial data and forming message blocks; and performing logical operation on the message blocks in turn to generate a 256-bit hash value through the cyclic compression module; The message expansion module and the cyclic compression module are connected with the message preprocessing module at the same time, wherein each module includes a data input unit and a data output unit, and the message preprocessing module includes a data processing unit, and the message expansion module and the cyclic compression module both include a logical operation unit; wherein, The message preprocessing module further includes a counting control unit for counting and judging the number of cyclic compression times of any message block and controlling the data flow direction according to the judgment result; When the counting control unit determines that the cyclic compression of any message block is performed for the first sixteen times, the message preprocessing module transmits the corresponding data in the message block to the cyclic compression module for cyclic compression, and outputs the cyclic compression result through the cyclic compression module; ​ When the count control unit determines that the seventeenth to sixty-fourth round compression processing is performed on the message block, the message preprocessing module transmits the message block to the message expansion module for message expansion, and then transmits the message expansion result to the round compression module for round compression and outputs the round compression result; When the count control unit determines that the sixteenth round compression processing is performed on the message block, the message preprocessing module also transmits the message block to the message expansion module for message expansion to perform the seventeenth round compression to generate the seventeenth group of data, and then performs the complete sixty-fourth round compression operation on the previous data to generate the 256-bit hash value.

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