DC detection circuit, audio amplifier and electronic equipment

Abstract

The present invention provides a DC detection circuit, an audio amplifier, and an electronic device. The DC detection circuit includes a processing unit and a detection unit. The processing unit is configured to receive a first pulse-width modulated signal and a second pulse-width modulated signal, perform level shifting and logical operations on the first and second pulse-width modulated signals, and output a third signal. The detection unit is configured to receive the third signal and detect whether the duty cycle of the third signal is greater than a first preset threshold value, thereby determining whether the DC voltage in the signal output from the audio amplifier to the speaker exceeds a second preset threshold value. Because the third signal is not affected by parameters other than the duty cycles of the first and second pulse-width modulated signals, such as the temperature of the audio amplifier's environment and the modulation mode, the DC voltage output by the audio amplifier can be more accurately detected, thereby preventing overheating or damage to the speaker.

Description

Technical Field

[0001] The present invention relates to the technical field of audio signal processing, and in particular to a direct current detection circuit, an audio amplifier and an electronic device. Background Art

[0002] Speakers are electroacoustic transducers that convert electrical signals into acoustic signals, making them widely used in various electronic devices such as smartphones, tablets, and smart TVs. Speakers are typically driven by pulse-width modulated signals output by audio amplifiers. However, because speakers are very sensitive to DC voltage, a malfunctioning audio amplifier that outputs DC voltage to the speaker can cause overheating or damage. Summary of the Invention

[0003] The present invention provides a direct current detection circuit, an audio amplifier and an electronic device for detecting the direct current voltage outputted by the audio amplifier to a loudspeaker, so as to prevent the loudspeaker from being overheated or damaged.

[0004] In a first aspect, the present invention provides a DC detection circuit, applied to an audio amplifier, wherein two output terminals of the audio amplifier respectively output a first pulse width modulated signal and a second pulse width modulated signal to drive a speaker via the first pulse width modulated signal and the second pulse width modulated signal. The DC detection circuit includes a processing unit and a detection unit; the processing unit is configured to receive the first pulse width modulated signal and the second pulse width modulated signal, perform level shifting and logical operations on the first pulse width modulated signal and the second pulse width modulated signal, and then output a third signal; the detection unit is configured to receive the third signal and detect whether a duty cycle of the third signal is greater than a first preset threshold value to determine whether a DC voltage in a signal output from the audio amplifier to the speaker exceeds a second preset threshold value; wherein a duty cycle of the third signal being greater than the first preset threshold value indicates that a duty cycle difference between the first pulse width modulated signal and the second pulse width modulated signal is greater than a third preset threshold value, and a duty cycle difference being greater than the third preset threshold value indicates that a DC voltage in a signal output from the audio amplifier exceeds a second preset threshold value.

[0005] In some optional examples, the processing unit includes a level transfer module and a logic module; the level transfer module is used to receive the first pulse width modulated signal and the second pulse width modulated signal, and transfer the levels of the first pulse width modulated signal and the second pulse width modulated signal from a first level value to a second level value, and the second level value is less than the first level value; the logic module is used to perform logical operations on the first pulse width modulated signal and the second pulse width modulated signal after level transfer to obtain the third signal.

[0006] In some optional examples, the logic module includes a NAND gate; or, the logic module includes an XOR gate.

[0007] In some optional examples, the detection unit includes a first switching transistor, a second switching transistor, a first current source, a second current source, a capacitor, and a comparator; the control end of the first switching transistor and the control end of the second switching transistor are connected to the output end of the processing unit for receiving the third signal; the first end of the first switching transistor is connected to one end of the first current source, the other end of the first current source is connected to a power supply end, the first end of the second switching transistor is connected to one end of the second current source, the other end of the second current source is grounded, the second end of the first switching transistor and the second end of the second switching transistor are connected to the first end of the capacitor, and the second end of the capacitor is connected to the ground end; one input end of the comparator is connected to the first end of the capacitor, and the other input end of the comparator receives a reference voltage; when the third signal is at a first level, the first switching transistor is turned on and the second switching transistor is turned off, so that the capacitor is charged; when the third signal is at a second level, the first switching transistor is turned off and the second switching transistor is turned on, so that the capacitor is discharged; the comparator is used to detect an actual voltage of the capacitor, compare the actual voltage with the reference voltage, and output a comparison result, so as to determine whether the duty cycle of the third signal is greater than a first preset threshold based on the comparison result.

[0008] In some optional examples, the first switch tube is an NMOS transistor, the second switch tube is a PMOS transistor, the first level is a low level, and the second level is a high level; or, the first switch tube is a PMOS transistor, the second switch tube is an NMOS transistor, the first level is a high level, and the second level is a low level.

[0009] In some optional examples, the output end of the detection unit is connected to the audio amplifier, and the detection unit is used to feed back the detection result to the audio amplifier, so that the audio amplifier determines whether to stop working according to the detection result.

[0010] In a second aspect, the present invention provides a DC detection method, which is applied to an audio amplifier, wherein two output terminals of the audio amplifier respectively output a first pulse width modulated signal and a second pulse width modulated signal, so as to drive a speaker to operate through the first pulse width modulated signal and the second pulse width modulated signal. The DC detection method includes: performing level shifting and logical operations on the first pulse width modulated signal and the second pulse width modulated signal to obtain a third signal; detecting whether a duty cycle of the third signal is greater than a first preset threshold to determine whether a DC voltage in a signal output by the audio amplifier exceeds a second preset threshold; wherein the duty cycle of the third signal being greater than the first preset threshold indicates that a difference in duty cycles between the first pulse width modulated signal and the second pulse width modulated signal is greater than a third preset threshold, and the difference in duty cycles being greater than the third preset threshold indicates that a DC voltage in a signal output by the audio amplifier exceeds the second preset threshold.

[0011] In a third aspect, the present invention provides an audio amplifier comprising the DC detection circuit as described in any one of the above items.

[0012] In some optional examples, the audio amplifier includes a PWM modulated amplifier, and the amplifier includes a power driver stage.

[0013] In a fourth aspect, the present invention provides an electronic device comprising the audio amplifier as described above.

[0014] The DC detection circuit, audio amplifier, and electronic device provided by the present invention generate a third signal by performing level shifting and logical operations on a first pulse-width modulated signal and a second pulse-width modulated signal. A duty cycle of the third signal greater than a first preset threshold indicates that the difference between the duty cycles of the first and second pulse-width modulated signals is greater than the third preset threshold. This duty cycle difference greater than the third preset threshold indicates that the DC voltage in the signal output by the audio amplifier exceeds the second preset threshold. Therefore, by detecting whether the duty cycle of the third signal is greater than the first preset threshold, it is possible to determine whether the DC voltage in the signal output by the audio amplifier exceeds the second preset threshold. Because the third signal is unaffected by parameters other than the duty cycles of the first and second pulse-width modulated signals, such as the ambient temperature and modulation mode of the audio amplifier, the problem of the first and second pulse-width modulated signals not accurately reflecting the DC voltage reaching the speaker due to the dead time of the output stage of the Class D audio amplifier is avoided. Consequently, the DC voltage in the signal output by the audio amplifier can be more accurately detected, preventing overheating or damage to the speaker. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0016] Figure 1 This is a structural block diagram of an audio amplifier disclosed in an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of the specific structure of an audio amplifier disclosed in an embodiment of the present invention;

[0018] Figure 3 A timing diagram of a pulse width modulation signal disclosed in an embodiment of the present invention;

[0019] Figure 4 A schematic diagram of the connection relationship between a DC detection circuit and an audio amplifier provided in an embodiment of the present invention;

[0020] Figure 5 A schematic structural diagram of a DC detection circuit disclosed in an embodiment of the present invention;

[0021] Figure 6 A timing diagram of a third signal disclosed in an embodiment of the present invention;

[0022] Figure 7 A timing diagram of another third signal disclosed in an embodiment of the present invention;

[0023] Figure 8 A timing diagram of another third signal disclosed in an embodiment of the present invention;

[0024] Figure 9 A schematic structural diagram of another DC detection circuit disclosed in an embodiment of the present invention;

[0025] Figure 10 This is a flow chart of a DC detection method disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] like Figure 1 As shown, Figure 1 This is a structural block diagram of an audio amplifier disclosed in an embodiment of the present invention. The audio amplifier is a class D amplifier and includes a signal modulation module 10 , a driving module 20 , a power amplification module 30 and a low-pass filtering module 40 .

[0028] The signal modulation module 10 is primarily used to convert the analog audio signal into a digital pulse width modulation (PWM) signal. Typically, the signal modulation module 10 is implemented using a comparator, with the audio signal serving as one input and a triangular wave signal with a frequency n (n>1) times the audio signal. The comparator compares the audio signal with the triangular wave signal. If the amplitude of the audio signal is higher than the amplitude of the triangular wave signal at a given moment, the comparator outputs a high level; otherwise, it outputs a low level. The duration of the high and low levels is determined by the time difference between the two. Consequently, a continuous audio signal is modulated into a continuous PWM signal.

[0029] The driver module 20 works closely with the power amplifier module 30. Typically, the power amplifier module 30 is composed of high-power MOS transistors. The driver module 20 controls the on / off state of the MOS transistors in the power amplifier module 30 based on the pulse-width modulated signal, thereby enabling the power amplifier module 30 to output a signal that matches the pulse-width modulated signal generated in the aforementioned steps while achieving power amplification. Because the signal output by the power amplifier module 30 contains both an audio signal and a carrier signal, a low-pass filter 40 is required in the audio amplifier to filter out the carrier signal in order to restore the desired audio signal.

[0030] like Figure 2 As shown, Figure 2 This is a schematic diagram of the specific structure of an audio amplifier disclosed in an embodiment of the present invention. The audio amplifier includes two output terminals and drives a speaker 50 to work through two pulse width modulation signals output by the two output terminals, such as a first pulse width modulation signal PWMN and a second pulse width modulation signal PWMP.

[0031] like Figure 3 As shown, Figure 3 This is a timing diagram of a pulse width modulation signal disclosed in an embodiment of the present invention. Under normal circumstances, the duty cycles of the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP are the same and both are less than 100%, such as 30%, 40%, 50%, or 60%. However, if a fault occurs within the audio amplifier, the duty cycles of the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP may differ. In this case, there is a certain difference in the duty cycles of the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP. The larger the difference, the greater the amplitude of the DC voltage output by the audio amplifier to the speaker. Excessively large DC voltage amplitude can cause overheating or damage to the speaker.

[0032] Based on this, an embodiment of the present invention discloses a DC detection circuit for detecting whether the duty cycle difference between a first pulse-width modulation signal and a second pulse-width modulation signal output by an audio amplifier is greater than a preset threshold, so as to issue a fault warning or control the audio amplifier to stop working according to the detection result to avoid overheating or damage to the speaker.

[0033] As an optional implementation of the contents disclosed in the present invention, an embodiment of the present invention provides a DC detection circuit, which is applied to an audio amplifier and is used to detect whether the duty cycle difference between a first pulse width modulation signal and a second pulse width modulation signal output by the audio amplifier is greater than a preset threshold.

[0034] like Figure 4 As shown, Figure 4 This is a schematic diagram of the connection relationship between a DC detection circuit and an audio amplifier provided in an embodiment of the present invention. The two output terminals of the audio amplifier respectively output a first pulse width modulation signal PWMN and a second pulse width modulation signal PWMP to drive the speaker 50 to operate through the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP. It can be understood that Figure 4 Only an audio amplifier is used as an example for description. The structure of the audio amplifier in the embodiment of the present invention is not limited to Figure 4 shown.

[0035] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a DC detection circuit disclosed in an embodiment of the present invention. The DC detection circuit includes a processing unit 51 and a detection unit 52. The two input terminals of the processing unit 51 are respectively connected to the two output terminals of the audio amplifier, and the input terminal of the detection unit 52 is connected to the output terminal of the processing unit 51.

[0036] The processing unit 51 is configured to receive a first pulse-width modulated signal PWMN and a second pulse-width modulated signal PWMP, perform level shifting and logic operations on the first pulse-width modulated signal PWMN and the second pulse-width modulated signal PWMP, and output a third signal V3. The detection unit 52 is configured to receive the third signal V3 and detect whether the duty cycle of the third signal is greater than a first preset threshold value, thereby determining whether the DC voltage of the signal output by the audio amplifier exceeds a second preset threshold value. A duty cycle of the third signal greater than the first preset threshold value indicates that the difference in duty cycle between the first pulse-width modulated signal and the second pulse-width modulated signal is greater than a third preset threshold value, and a duty cycle difference greater than the third preset threshold value indicates that the DC voltage of the signal output by the audio amplifier exceeds the second preset threshold value.

[0037] In some embodiments of the present invention, the processing unit includes a level shifting module and a logic module. The level shifting module is configured to receive a first pulse-width modulated signal and a second pulse-width modulated signal, and shift the levels of the first pulse-width modulated signal PWMN and the second pulse-width modulated signal PWMP from a first level value to a second level value, where the second level value is less than the first level value. For example, the high level of the first pulse-width modulated signal and the second pulse-width modulated signal is shifted from 30V to 5V or 1.8V, wherein the low level of the first pulse-width modulated signal and the second pulse-width modulated signal remains unchanged at 0V. The logic module is configured to perform a logic operation on the level-shifted first pulse-width modulated signal and the second pulse-width modulated signal to obtain a third signal.

[0038] In some embodiments of the present invention, the logic module includes a NAND gate, and in other embodiments, the logic module includes an XOR gate. However, the present invention is not limited to this. In other embodiments, the logic module may also include other logic gates or combinations of logic gates, which will not be repeated here.

[0039] In the case where the logic module is a NAND gate, a timing diagram of the third signal is as follows: Figure 6 As shown, in the case where the logic module is an XOR gate, another timing diagram of the third signal is as follows Figure 7 As shown, after the logic operation is performed on the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP, the output third signal V3 has a certain duty cycle. When the duty cycle difference between the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP remains unchanged, the duty cycle of the third signal V3 also remains unchanged.

[0040] However, when the duty cycle difference between the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP increases, the duty cycle of the third signal V3 also increases. Figure 8 As shown, Figure 8 This is a timing diagram of another third signal disclosed in an embodiment of the present invention. When the duty cycle of the second pulse width modulation signal PWMP increases, the difference in duty cycle between the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP also increases. When the logic module is a NAND gate, the duty cycle of the third signal V3 also increases.

[0041] Based on this, in embodiments of the present invention, by simply determining whether the duty cycle of the third signal V3 is greater than a first preset threshold, it can be determined that the first preset threshold indicates that the difference between the duty cycles of the first pulse-width modulation signal PWMN and the second pulse-width modulation signal PWMP is greater than the third preset threshold, thereby determining whether the DC voltage in the signal output from the audio amplifier to the speaker exceeds the second preset threshold. Because the third signal V3 is not affected by parameters other than the duty cycles of the first and second pulse-width modulation signals PWMN and PWMP, such as the ambient temperature and modulation mode of the audio amplifier, the problem of the first and second pulse-width modulation signals not accurately reflecting the DC voltage reaching the speaker due to the dead time of the output stage of the Class D audio amplifier is avoided. Therefore, the DC voltage output by the audio amplifier can be more accurately detected, preventing overheating or damage to the speaker. The dead time is provided to prevent the PMOS transistor and NMOS transistor of the output stage from being turned on simultaneously.

[0042] In some embodiments of the present invention, the detection unit 52 controls the charging and discharging of the capacitor through the third signal V3 to detect the duty cycle of the third signal V3. Of course, the present invention is not limited to this. In other embodiments, the duty cycle of the third signal V3 can also be detected by a timer or a counter, which will not be repeated here.

[0043] like Figure 9 As shown, Figure 9 Schematic diagram of another DC detection circuit disclosed in an embodiment of the present invention. The detection unit 52 includes a first switch tube K1, a second switch tube K2, a first current source I1, a second current source I2, a capacitor C and a comparator AP.

[0044] The control terminal of the first switch K1 and the control terminal of the second switch K2 are connected to the output terminal of the processing unit 51 for receiving the third signal V3. The first terminal of the first switch K1 is connected to one terminal of the first current source I1, the other terminal of the first current source I1 is connected to the power supply terminal VDD. The first terminal of the second switch K2 is connected to one terminal of the second current source I2, the other terminal of the second current source I2 is grounded. The second terminal of the first switch K1 and the second terminal of the second switch K2 are connected to the first terminal of the capacitor C, and the second terminal of the capacitor C is connected to the ground terminal GND. One input terminal of the comparator AP is connected to the first terminal of the capacitor C, and the other input terminal of the comparator AP receives the reference voltage Vref. It will be understood that the "connection" in the embodiments of the present invention can be a direct connection or an indirect connection achieved through other electronic components, which will not be further described here.

[0045] When the third signal V3 is at a first level, the first switch K1 is turned on and the second switch K2 is turned off. The first current source I1, the first switch K1, and the capacitor C form a charging path, thereby charging the capacitor C. When the third signal V3 is at a second level, the first switch K1 is turned off and the second switch K2 is turned on. The second switch K2, the second current source I2, and the capacitor C form a discharging path, thereby discharging the capacitor C. The comparator AP is configured to detect an actual voltage V1 of the capacitor C, compare the actual voltage V1 with a reference voltage Vref, and output a comparison result Vout. Based on the comparison result Vout, the comparator AP determines whether the duty cycle of the third signal V3 is greater than a first preset threshold.

[0046] In some embodiments of the present invention, the first switch transistor K1 may be an NMOS transistor, the second switch transistor K2 may be a PMOS transistor, the first level may be a low-level signal, and the second level may be a high-level signal. Of course, the present invention is not limited to this embodiment. In other embodiments, the first switch transistor K1 may be a PMOS transistor, the second switch transistor K2 may be an NMOS transistor, the first level may be a high-level signal, and the second level may be a low-level signal. Of course, the first switch transistor K1 and the second switch transistor K2 may also be other switches, such as the first switch transistor K1 and the second switch transistor K2 being complementary switches, etc., which will not be further described here.

[0047] The first current source I1 and the second current source I2 can provide stable charge and discharge currents to the capacitor C, so that the charge and discharge quantity of the capacitor C is only affected by the duty cycle of the third signal V3, thereby ensuring the accuracy of the duty cycle detection of the third signal V3.

[0048] Assuming that the duration of the first level is T1 and the duration of the second level is T2, the duty cycle D of the third signal V3 is T1 / (T1+T2), and the charging duration of the capacitor C in each charge and discharge cycle is T1 and T2. When the duty cycles of the first pulse-width modulation signal PWMN and the second pulse-width modulation signal PWMP are the same, that is, when the difference between the duty cycles of the first pulse-width modulation signal PWMN and the second pulse-width modulation signal PWMP is zero, the duty cycle of the third signal V3 remains unchanged, so that the actual voltage V1 of the capacitor C is less than the capacitor voltage corresponding to the first preset threshold value, and the reference voltage Vref is greater than or equal to the capacitor voltage corresponding to the first preset threshold value, so that the comparison result of the comparator AP remains unchanged, such as the comparison result Vout remains at a high level. However, when the difference between the duty cycles of the first pulse-width modulation signal PWMN and the second pulse-width modulation signal PWMP increases, the duty cycle of the third signal V3 also increases, so that the actual voltage V1 of the capacitor C also increases. If the actual voltage V1 of the capacitor C is greater than the reference voltage Vref, the comparison result of the comparator AP will be reversed, such as the comparison result Vout flipping to a low level.

[0049] Based on this, it can be determined based on the comparison result of the comparator AP whether the duty cycle of the third signal V3 is greater than the first preset threshold, and further, based on whether the duty cycle of the third signal V3 is greater than the first preset threshold, it can be determined whether the duty cycle difference between the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP is greater than the third preset threshold. Furthermore, based on whether the duty cycle difference is greater than the third preset threshold, it can be determined whether the DC voltage in the signal output by the audio amplifier to the speaker exceeds the second preset threshold. If the DC voltage exceeds the second preset threshold, the speaker may overheat or be damaged.

[0050] Assuming that the power supply voltage of the audio amplifier is PVDD, the duty cycle difference between the first pulse width modulation signal PWMN and the second pulse width modulation signal PWMP is △D, then the DC voltage V DC =PVDD*△D. Among them, the charge of capacitor C is (PVDD*△D*T) / k. When the DC voltage is equal to the second preset threshold value V2, the discharge of capacitor C is (V2*k*T) / k. According to the charge and discharge balance, (PVDD*△D*T) / k=(V2*k*T) / k. Therefore, V DC = V2. Where T represents time, and k is a coefficient that characterizes the resistance of the circuit in which the capacitor C is located.

[0051] In the embodiment of the present invention, the duty cycle of the third signal V3 is detected by controlling the charge and discharge of the capacitor C via the third signal V3, rather than detecting the duty cycle of the first pulse-width modulation signal PWMN and / or the second pulse-width modulation signal PWMP by controlling the charge and discharge of the capacitor C. This prevents the detection result from being affected by parameters such as the voltage value of the first pulse-width modulation signal PWMN and / or the second pulse-width modulation signal PWMP, the ambient temperature of the audio amplifier, and the modulation mode. This not only improves detection accuracy but also reduces the ripple of the capacitor C, thereby enabling the use of a capacitor C with very small capacitance, thereby reducing the area and cost of the DC detection circuit.

[0052] In some embodiments of the present invention, the output of the comparator AP can be connected to a processor. Upon detecting a change in the output signal of the comparator AP, the processor can control an alarm to issue a fault warning, prompting a staff member to control the audio amplifier to stop operating. Alternatively, the processor can directly control the audio amplifier to stop operating. Of course, the present invention is not limited to this. In other embodiments, the output of the comparator AP can also be directly connected to the audio amplifier to feed the output signal of the comparator AP back to the audio amplifier, so that the audio amplifier determines whether to stop operating based on the output signal.

[0053] As an optional implementation of the present disclosure, an embodiment of the present invention provides a DC detection method, which is applied to an audio amplifier to detect whether the pulse width modulation signal output by the audio amplifier is converted into a DC voltage signal. Figure 4 The two output terminals of the audio amplifier respectively output a first pulse width modulation signal and a second pulse width modulation signal, so as to drive the speaker to work through the first pulse width modulation signal and the second pulse width modulation signal. Figure 10 As shown, Figure 10 This is a flow chart of a DC detection method disclosed in an embodiment of the present invention. The DC detection method includes:

[0054] S110: performing level shift and logic operation on the first pulse width modulation signal and the second pulse width modulation signal to obtain a third signal;

[0055] S111: Detect whether the duty cycle of the third signal is greater than a first preset threshold, so as to determine whether the DC voltage of the signal output by the audio amplifier exceeds a second preset threshold.

[0056] Among them, the duty cycle of the third signal being greater than the first preset threshold indicates that the duty cycle difference between the first pulse width modulation signal and the second pulse width modulation signal is greater than the third preset threshold, and the duty cycle difference being greater than the third preset threshold indicates that the DC voltage in the signal output by the audio amplifier exceeds the second preset threshold.

[0057] refer to Figure 5 After receiving the first pulse-width modulated signal PWMN and the second pulse-width modulated signal PWMP, the processing unit 51 performs level shifting and logic operations on the first and second pulse-width modulated signals PWMN and PWMP to obtain and output a third signal V3. The detection unit 52 receives the third signal V3 and detects whether the duty cycle of the third signal V3 is greater than a first preset threshold. Based on whether the duty cycle of the third signal V3 is greater than the first preset threshold, the processing unit 51 determines whether the difference in duty cycles between the first and second pulse-width modulated signals PWMN and PWMP is greater than a third preset threshold. Based on whether the difference in duty cycles is greater than the third preset threshold, the processing unit 51 determines whether the DC voltage of the signal output from the audio amplifier to the speaker exceeds a second preset threshold, thereby preventing overheating or damage to the speaker.

[0058] refer to Figure 9 After the processing unit 51 outputs the third signal V3, if the third signal V3 is at the first level, the first switch tube K1 is turned on and the second switch tube K2 is turned off. The first switch tube K1 and the capacitor C form a charging path to charge the capacitor C. If the third signal V3 is at the second level, the first switch tube K1 is turned off and the second switch tube K2 is turned on. The second switch tube K2 and the capacitor C form a discharging path to discharge the capacitor C.

[0059] When the third signal V3 is at a first level, the first switch K1 is turned on and the second switch K2 is turned off. The first current source I1, the first switch K1, and the capacitor C form a charging path, thereby charging the capacitor C. When the third signal V3 is at a second level, the first switch K1 is turned off and the second switch K2 is turned on. The second switch K2, the second current source I2, and the capacitor C form a discharging path, thereby discharging the capacitor C. The comparator AP is configured to detect an actual voltage V1 of the capacitor C, compare the actual voltage V1 with a reference voltage Vref, and output a comparison result Vout. Based on the comparison result Vout, the comparator AP determines whether the duty cycle of the third signal V3 is greater than a first preset threshold.

[0060] As an optional implementation of the present disclosure, an embodiment of the present invention provides an audio amplifier, comprising a DC detection circuit as provided in any of the above embodiments. The audio amplifier comprises a Class D amplifier. Optionally, the audio amplifier comprises a PWM modulated amplifier, and the amplifier includes a power driver stage.

[0061] As an optional implementation of the disclosed content of the present invention, an embodiment of the present invention provides an electronic device, including the above audio amplifier.

[0062] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the scope of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be subject to the appended claims.

Claims

1. A DC detection circuit, characterized in that: Applied to an audio amplifier, wherein two output terminals of the audio amplifier respectively output a first pulse width modulation signal and a second pulse width modulation signal, so as to drive a speaker to operate through the first pulse width modulation signal and the second pulse width modulation signal, and the DC detection circuit includes a processing unit and a detection unit; The processing unit is configured to receive the first pulse width modulation signal and the second pulse width modulation signal, perform level shift and logic operation on the first pulse width modulation signal and the second pulse width modulation signal, and then output a third signal; The detection unit is configured to receive the third signal and detect whether a duty cycle of the third signal is greater than a first preset threshold value, so as to determine whether a DC voltage in the signal output by the audio amplifier exceeds a second preset threshold value; wherein the duty cycle of the third signal being greater than the first preset threshold value indicates that a difference in duty cycles between the first pulse-width modulation signal and the second pulse-width modulation signal is greater than a third preset threshold value, and the difference in duty cycles being greater than the third preset threshold value indicates that the DC voltage in the signal output by the audio amplifier exceeds the second preset threshold value; The processing unit includes a level transfer module and a logic module; the level transfer module is used to receive the first pulse width modulated signal and the second pulse width modulated signal, and transfer the levels of the first pulse width modulated signal and the second pulse width modulated signal from a first level value to a second level value, where the second level value is less than the first level value; the logic module is used to perform a logical operation on the first pulse width modulated signal and the second pulse width modulated signal after the level transfer to obtain the third signal.

2. The DC detection circuit according to claim 1, characterized in that: The logic module includes a NAND gate; or, the logic module includes an XOR gate.

3. The DC detection circuit according to claim 1, wherein: The detection unit includes a first switch tube, a second switch tube, a first current source, a second current source, a capacitor and a comparator; The control end of the first switching transistor and the control end of the second switching transistor are connected to the output end of the processing unit for receiving the third signal; a first end of the first switching transistor is connected to one end of the first current source, the other end of the first current source is connected to the power supply end, a first end of the second switching transistor is connected to one end of the second current source, the other end of the second current source is grounded, a second end of the first switching transistor and a second end of the second switching transistor are connected to the first end of the capacitor, and the second end of the capacitor is connected to the ground end; one input end of the comparator is connected to the first end of the capacitor, and the other input end of the comparator receives a reference voltage; When the third signal is at a first level, the first switch tube is turned on and the second switch tube is turned off, so that the capacitor is charged; when the third signal is at a second level, the first switch tube is turned off and the second switch tube is turned on, so that the capacitor is discharged; The comparator is used to detect the actual voltage of the capacitor, compare the actual voltage with the reference voltage and output a comparison result, so as to determine whether the duty cycle of the third signal is greater than a first preset threshold according to the comparison result.

4. The DC detection circuit according to claim 3, characterized in that: The first switch tube is an NMOS transistor, the second switch tube is a PMOS transistor, the first level is a low level, and the second level is a high level; or, The first switch tube is a PMOS transistor, the second switch tube is an NMOS transistor, the first level is a high level, and the second level is a low level.

5. The DC detection circuit according to claim 1, characterized in that: The output end of the detection unit is connected to the audio amplifier. The detection unit is used to feed back the detection result to the audio amplifier, so that the audio amplifier determines whether to stop working according to the detection result.

6. A DC detection method, characterized in that: Applied to the DC detection circuit according to any one of claims 1 to 5, the DC detection method comprises: performing level shift and logic operation on the first pulse width modulation signal and the second pulse width modulation signal respectively outputted from the two output terminals of the audio amplifier to obtain a third signal; detecting whether a duty cycle of the third signal is greater than a first preset threshold value, so as to determine whether a DC voltage in the signal output by the audio amplifier exceeds a second preset threshold value; The duty cycle of the third signal being greater than the first preset threshold indicates that the duty cycle difference between the first pulse width modulation signal and the second pulse width modulation signal is greater than a third preset threshold, and the duty cycle difference being greater than the third preset threshold indicates that the DC voltage in the signal output by the audio amplifier exceeds a second preset threshold.

7. An audio amplifier, characterized in that: The DC detection circuit comprises the DC detection circuit according to any one of claims 1 to 5.

8. The audio amplifier according to claim 7, wherein: The audio amplifier comprises a PWM modulated amplifier, and the amplifier includes a power driver stage.

9. An electronic device, characterized in that: The audio amplifier according to claim 7 or 8 is included.

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