High-speed serial bus transmission circuit

Abstract

The utility model discloses a high-speed serial bus transmission circuit, which comprises a main control circuit, and the main control circuit comprises an FPGA (field programmable gate array), a CLKIO (clock line input / output), a DATAIO (data address input / output) and an LTC2879XMS8E chip. An acquisition node circuit, wherein the acquisition node circuit comprises an FPGA (Field Programmable Gate Array), a CLKIO, a DATAIO and an LTC2879XMS8E chip; and a level conversion circuit, wherein the level conversion circuit comprises a resistor and an LTC2879XMS8E chip. According to the utility model, the circuit structure design is optimized, through the arrangement of the master control circuit, the acquisition node circuit and the level conversion circuit, the communication between one master control and a plurality of acquisition nodes is realized, the acquisition nodes are distinguished by different addresses, the communication efficiency is high, the external common-mode noise can be completely counteracted, and the reliability is high. Signals are transmitted in a differential mode, the anti-interference capacity of communication is improved, the structural design that the two sets of shielding twisted pairs are combined is adopted, the two wires are close to each other and equal in signal amplitude, the amplitudes of coupling electromagnetic fields between the two wires and the ground wire are also equal, the signal polarities of the two wires and the ground wire are opposite, and according to the right-hand spiral rule, the signal polarities of the two wires are different. The magnetic lines of force are mutually offset, and the anti-electromagnetic interference capability is strong.

Description

Technical Field

[0001] The utility model relates to the technical field of high-speed serial circuits, in particular to a high-speed serial bus transmission circuit. Background Art

[0002] The working principle of the acoustic logging instrument is to stimulate an acoustic pressure pulse through a piezoelectric ceramic transmitting transducer and radiate it into the formation. When the acoustic wave encounters obstacles or other interfaces during its propagation in the formation, it will be reflected. The returned acoustic wave signal is collected by an array receiver connected to the acquisition node circuit, and then transmitted to the main control unit for data compression and transmission to the next level. Due to the harsh working environment of the instrument and the need for stable and rapid transmission of a large amount of acoustic wave acquisition data between multiple acquisition node circuits and the main control unit, a high-speed serial bus transmission circuit is required. The transmission circuit in the existing technology has the following disadvantages during use:

[0003] UART communication can only connect to one device at a time, has a low communication rate, and is easily affected by electromagnetic interference and noise, so it cannot meet the communication needs of the system.

[0004] The drawbacks of USB communication are that the host-side protocol stack is too large and complex, making it difficult to miniaturize. A minimal USB host driver requires thousands of lines of code to implement, and the communication distance is too short to meet the communication needs of the system. Utility Model Content

[0005] Therefore, the purpose of the present invention is to provide a high-speed serial bus transmission circuit, optimize the circuit structure design, and realize communication between a master control circuit, an acquisition node circuit and a level conversion circuit through the setting of the master control circuit, the acquisition node circuit and the level conversion circuit. The acquisition nodes are distinguished by different addresses, the communication efficiency is high, and the external common-mode noise can be completely offset. The signal is transmitted in a differential form, which is conducive to improving the anti-interference ability of the communication. The structural design of the combination of two groups of shielded twisted pair cables is that the two wires are very close and the signal amplitudes are equal. The amplitudes of the coupled electromagnetic fields between the two wires and the ground wire are also equal. At the same time, their signal polarities are opposite. According to the right-hand screw rule, their magnetic lines of force offset each other, and the anti-electromagnetic interference ability is strong.

[0006] To solve the above technical problems, according to one aspect of the present invention, the present invention provides the following technical solution: a high-speed serial bus transmission circuit, comprising:

[0007] Main control circuit, the main control circuit includes FPGA, CLK_IO, DATA_IO, LTC2879XMS8E chip;

[0008] An acquisition node circuit, comprising an FPGA, a CLK_IO, a DATA_IO, and an LTC2879XMS8E chip;

[0009] A level conversion circuit, comprising a resistor and an LTC2879XMS8E chip;

[0010] The signal converted by the main control circuit is connected to the acquisition node circuit via a set of high-speed serial buses.

[0011] As a preferred solution of the high-speed serial bus transmission circuit described in the utility model, the CLK_IO of the main control circuit FPGA outputs a clock signal with a frequency of 8Mbps, and the DATA_IO outputs a data signal, and the edges of the clock signal and the data signal are strictly aligned.

[0012] As a preferred solution of the high-speed serial bus transmission circuit described in the utility model, in the main control circuit, the single-ended clock signal is converted into differential clock signals CLK_A and CLK_B by the chip LT2879XMS8E, and the single-ended data signal is converted into differential data signals DATA_A and DATA_B by the chip LT2879XMS8E.

[0013] As a preferred solution of the high-speed serial bus transmission circuit described in the utility model, in the acquisition circuit, two LT2879XMS8E chips are used to convert the differential clock signal and data signal into single-ended signals and input them to CLK_IO and DATA_IO of the acquisition node FPGA.

[0014] As a preferred solution of a high-speed serial bus transmission circuit described in the utility model, in the level conversion circuit, resistors R1 and R6 are pull-up resistors, resistors R3 and R4 are pull-down resistors, resistor R2 is an IO port current limiting resistor, resistor R5 is a terminal matching resistor, and chip U1 is a level conversion chip LTC2879XMS8E.

[0015] As a preferred solution of the high-speed serial bus transmission circuit described in the utility model, it also includes two groups of shielded twisted pairs, one group of twisted pairs is used to transmit differential clock signals, and the other group of twisted pairs is used to transmit differential data signals.

[0016] Compared with the prior art, the advantages of the present invention are:

[0017] The circuit structure design is optimized. By setting up the main control circuit, acquisition node circuit and level conversion circuit, communication between one main control and multiple acquisition nodes is realized. The acquisition nodes are distinguished by different addresses, the communication efficiency is high, and the external common mode noise can be completely offset. The signal is transmitted in a differential form, which is conducive to improving the anti-interference ability of communication. The structural design of the combination of two groups of shielded twisted pair cables has two wires very close to each other and the signal amplitude is equal. The amplitude of the coupled electromagnetic field between these two wires and the ground wire is also equal. At the same time, their signal polarities are opposite. According to the right-hand screw rule, their magnetic lines of force offset each other, and the anti-electromagnetic interference ability is strong.

[0018] In actual use, a high-speed serial bus consists of two shielded twisted-pair cables, one for transmitting differential clock signals and the other for transmitting differential data signals. Using shielded twisted-pair cables as the transmission medium for a high-speed serial bus can reduce EMI. Because the two wires are close together and have equal signal amplitudes, the amplitudes of the coupled electromagnetic fields between the two wires and the ground wire are also equal. At the same time, their signal polarities are opposite. According to the right-hand screw rule, their magnetic field lines cancel each other out. The tighter the two wires are coupled, the more magnetic field lines cancel each other out, and the less electromagnetic energy is released to the outside world. Interference noise is generally loaded onto both signal lines simultaneously and with equal value. If the receiving end is only concerned with the difference between the two signals, then external common-mode noise can be completely canceled out. Therefore, transmitting signals differentially improves the communication's anti-interference capability. At one end of the high-speed transmission bus, we convert the transmitted TTL logic level into a low-voltage differential signal, and at the other end, we convert the differential signal into a single-ended signal for reception.

[0019] The CLK_IO of the main control circuit FPGA outputs a clock signal with a frequency of 8Mbps, and the DATA_IO outputs a data signal. The clock signal and the data signal are strictly edge-aligned. The single-ended clock signal is converted into differential clock signals CLK_A and CLK_B by the chip LT2879XMS8E. The single-ended data signal is converted into differential data signals DATA_A and DATA_B by the chip LT2879XMS8E. The converted differential clock signal and differential data signal are connected to the collection node circuit through a set of high-speed serial buses. In the collection node circuit, two LT2879XMS8E chips are used to convert the differential clock signal and data signal into single-ended signals and input them to the CLK_IO and DATA_IO of the collection node FPGA respectively. At this point, signal transmission from the master control unit to the acquisition node circuit is complete. The same applies to signal transmission from the acquisition node to the master control unit. To enable a single master control unit to communicate with multiple acquisition nodes, we simultaneously connected multiple acquisition nodes to the same high-speed serial bus. Each acquisition node is distinguished by a different address. The distance between the master control unit and the first acquisition node is 1.5m, and the distance between adjacent acquisition nodes is 0.3m. Because the input impedance of level conversion chips is generally high (for example, the LT2879XMS8E has an input impedance of 112kΩ and can connect up to 96 nodes), the signal will experience a sudden change in instantaneous impedance at the end of the bus (in the case of the LT2879XMS8E, the impedance changes from 120Ω to 112kΩ), causing signal reflections and affecting signal quality. To prevent signal reflections and improve signal quality, we selected appropriate terminal resistors based on actual conditions, and experimental results have been satisfactory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings and detailed embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without inventive labor. Among them:

[0021] Figure 1 This is a transmission diagram of the main control circuit and the acquisition node circuit of the utility model;

[0022] Figure 2 This is a diagram showing the relationship between the clock and data phases of the present utility model;

[0023] Figure 3 This is the level conversion circuit diagram of the utility model;

[0024] Figure 4 This is a schematic diagram of multi-node transmission of the utility model;

[0025] Figure 5Schematic diagram of differential signal transmission effect. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. People skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific implementation methods disclosed below.

[0028] Next, the present invention is described in detail with reference to schematic diagrams. For ease of illustration, cross-sectional views of device structures may be partially enlarged and not to scale when describing the embodiments of the present invention. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0030] The utility model provides a high-speed serial bus transmission circuit with an optimized circuit structure design. By arranging a main control circuit, an acquisition node circuit and a level conversion circuit, communication between a main control and a plurality of acquisition nodes is realized. The acquisition nodes are distinguished by different addresses, the communication efficiency is high, and external common-mode noise can be completely offset. Signals are transmitted in a differential form, which is beneficial to improving the anti-interference ability of communication. The structural design of the combination of two groups of shielded twisted pair wires is that the two wires are very close and the signal amplitudes are equal. The amplitudes of the coupled electromagnetic fields between the two wires and the ground wire are also equal. At the same time, their signal polarities are opposite. According to the right-hand screw rule, their magnetic lines of force offset each other, and the anti-electromagnetic interference ability is strong.

[0031] Figure 1-Figure 5 The figure shows the overall structure of a high-speed serial bus transmission circuit embodiment of the present invention. Figure 1-5 , the main structure of this embodiment includes:

[0032] A main control circuit includes an FPGA, CLK_IO, DATA_IO, and an LTC2879XMS8E chip. The CLK_IO of the FPGA in the main control circuit outputs a clock signal with a frequency of 8Mbps, and the DATA_IO outputs a data signal. The clock signal and the data signal are strictly edge-aligned. In the main control circuit, the single-ended clock signal is converted into differential clock signals CLK_A and CLK_B by the LT2879XMS8E chip, and the single-ended data signal is converted into differential data signals DATA_A and DATA_B by the LT2879XMS8E chip.

[0033] An acquisition node circuit, comprising an FPGA, a CLK_IO, a DATA_IO, and an LTC2879XMS8E chip. In the acquisition circuit, two LT2879XMS8E chips are used to convert differential clock and data signals into single-ended signals and input them to the CLK_IO and DATA_IO of the acquisition node FPGA.

[0034] A level conversion circuit includes resistors and an LTC2879XMS8E chip. In the level conversion circuit, resistors R1 and R6 are pull-up resistors, resistors R3 and R4 are pull-down resistors, resistor R2 is an IO port current limiting resistor, resistor R5 is a terminal matching resistor, and chip U1 is a level conversion chip LTC2879XMS8E.

[0035] The signal converted by the main control circuit is connected to the acquisition node circuit via a set of high-speed serial buses;

[0036] In actual use, a high-speed serial bus consists of two sets of shielded twisted-pair cables, one of which transmits a differential clock signal, and the other transmits a differential data signal. Using a shielded twisted-pair cable as the transmission medium for a high-speed serial bus can reduce EMI. Because the two wires are close together and have equal signal amplitudes, the amplitude of the coupled electromagnetic field between the two wires and the ground wire is also equal. At the same time, their signal polarities are opposite. According to the right-hand screw rule, their magnetic lines of force cancel each other out. The tighter the coupling between the two wires, the more magnetic lines of force cancel each other out, and the less electromagnetic energy is released to the outside world. Interference noise is generally loaded onto both signal lines at the same time. If the receiving end is only concerned with the difference between the two signals, then external common-mode noise can be completely canceled out. Therefore, transmitting signals in differential form helps improve the communication's anti-interference capability. At one end of the high-speed transmission bus, we convert the transmitted TTL logic level into a low-voltage differential signal, and at the other end of the high-speed transmission bus, we convert the differential signal into a single-ended signal for reception.

[0037] The CLK_IO of the main control circuit FPGA outputs a clock signal with a frequency of 8Mbps, and the DATA_IO outputs a data signal. The clock signal and the data signal are strictly edge-aligned. The single-ended clock signal is converted into differential clock signals CLK_A and CLK_B by the chip LT2879XMS8E. The single-ended data signal is converted into differential data signals DATA_A and DATA_B by the chip LT2879XMS8E. The converted differential clock signal and differential data signal are connected to the collection node circuit through a set of high-speed serial buses. In the collection node circuit, two LT2879XMS8E chips are used to convert the differential clock signal and data signal into single-ended signals and input them to the CLK_IO and DATA_IO of the collection node FPGA respectively. At this point, signal transmission from the master control unit to the acquisition node circuit is complete. The same applies to signal transmission from the acquisition node to the master control unit. To enable a single master control unit to communicate with multiple acquisition nodes, we simultaneously connected multiple acquisition nodes to the same high-speed serial bus. Each acquisition node is distinguished by a different address. The distance between the master control unit and the first acquisition node is 1.5m, and the distance between adjacent acquisition nodes is 0.3m. Because the input impedance of level conversion chips is generally high (for example, the LT2879XMS8E has an input impedance of 112kΩ and can connect up to 96 nodes), the signal will experience a sudden change in instantaneous impedance at the end of the bus (in the case of the LT2879XMS8E, the impedance changes from 120Ω to 112kΩ), causing signal reflections and affecting signal quality. To prevent signal reflections and improve signal quality, we selected appropriate terminal resistors based on actual conditions, and experimental results have been satisfactory.

[0038] While the present invention has been described above with reference to specific embodiments, various modifications may be made and equivalent components may be substituted without departing from the scope of the present invention. In particular, as long as no structural conflicts exist, the various features of the embodiments disclosed herein may be combined with one another in any manner, and the omission of an exhaustive description of these combinations in this specification is solely for the sake of space and resource conservation. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A high-speed serial bus transmission circuit, characterized in that: include: Main control circuit, the main control circuit includes FPGA, CLK_IO, DATA_IO, LTC2879XMS8E chip; An acquisition node circuit, comprising an FPGA, a CLK_IO, a DATA_IO, and an LTC2879XMS8E chip; A level conversion circuit, comprising a resistor and an LTC2879XMS8E chip; The signal converted by the main control circuit is connected to the acquisition node circuit via a set of high-speed serial buses.

2. The high-speed serial bus transmission circuit according to claim 1, wherein: The CLK_IO of the main control circuit FPGA outputs a clock signal with a frequency of 8Mbps, and the DATA_IO outputs a data signal. The edges of the clock signal and the data signal are strictly aligned.

3. The high-speed serial bus transmission circuit according to claim 2, characterized in that: In the main control circuit, the single-ended clock signal is converted into differential clock signals CLK_A and CLK_B by the chip LT2879XMS8E, and the single-ended data signal is converted into differential data signals DATA_A and DATA_B by the chip LT2879XMS8E.

4. The high-speed serial bus transmission circuit according to claim 3, wherein: In the acquisition node circuit, two LT2879XMS8E chips are used to convert the differential clock signal and data signal into single-ended signals and input them into CLK_IO and DATA_IO of the acquisition node FPGA.

5. The high-speed serial bus transmission circuit according to claim 4, characterized in that: In the level conversion circuit, resistors R1 and R6 are pull-up resistors, resistors R3 and R4 are pull-down resistors, resistor R2 is the IO port current limiting resistor, resistor R5 is the terminal matching resistor, and chip U1 is the level conversion chip LTC2879XMS8E.

6. The high-speed serial bus transmission circuit according to claim 5, characterized in that: It also includes two groups of shielded twisted-pair cables, one of which is used to transmit differential clock signals, and the other is used to transmit differential data signals.

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