Isolation conversion circuit

Abstract

The utility model relates to an isolation conversion circuit which comprises a voltage conversion chip U45, an isolation chip U42 and a level conversion chip U41. The input end of the voltage conversion chip U45 is connected with + 5V voltage, and the output end of the voltage conversion chip U45 is electrically connected with the first power supply input end of the isolation chip U42 so as to transmit the converted + 3.3 V voltage to the isolation chip U42; the isolation chip U42 is suitable for being electrically connected with the CPU chip U15, the isolation chip U42 is in bidirectional electrical connection with the level conversion chip U41, and the level conversion chip U41 is suitable for being in bidirectional electrical connection with RS-232 equipment so as to transmit converted signals; the input end of the voltage conversion chip U45 is electrically connected with a filter capacitor C191, and the output end of the voltage conversion chip U45 is electrically connected with a filter capacitor C86 and a filter capacitor C192; the first power input end of the isolation chip U42 is electrically connected with a filter capacitor C185.

Description

Technical Field

[0001] This application relates to the field of signal conversion technology, and in particular to an isolation conversion circuit. Background Technology

[0002] With the rapid development of information technology, the demand for higher accuracy in analog-to-digital conversion is increasing. For example, the main function of the MAX232 level converter chip is to convert between TTL and RS-232 levels. (Refer to...) Figure 4 As shown, in the existing circuit structure, the MAX232 level conversion chip is directly electrically connected to the CPU chip. This causes noise from the circuit on the left side of the MAX232 level conversion chip (the side connected to the CPU chip) to easily crosstalk to the communication signal on the right side, resulting in data transmission errors, affecting the normal communication between the CPU chip and external devices, and reducing circuit stability and lifespan. Summary of the Invention

[0003] In view of this, this application proposes an isolation switching circuit.

[0004] According to one aspect of this application, an isolation conversion circuit is provided, characterized in that it includes: a voltage conversion chip U45, an isolation chip U42, and a level conversion chip U41;

[0005] The input terminal of the voltage conversion chip U45 is connected to a +5V voltage, and the output terminal of the voltage conversion chip U45 is electrically connected to the first power input terminal of the isolation chip U42 to deliver the converted +3.3V voltage to the isolation chip U42;

[0006] The isolation chip U42 is suitable for bidirectional electrical connection with the CPU chip U15. The isolation chip U42 is also bidirectionally electrically connected with the level conversion chip U41. The level conversion chip U41 is suitable for bidirectional electrical connection with RS-232 devices to transmit the converted signal.

[0007] The input terminal of the voltage conversion chip U45 is electrically connected to a filter capacitor C191, and the output terminal of the voltage conversion chip U45 is electrically connected to filter capacitors C86 and C192.

[0008] The first power input terminal of the isolation chip U42 is electrically connected to a filter capacitor C185.

[0009] In one possible implementation, the voltage conversion chip U45 is designated as TPS75733KTT.

[0010] In one possible implementation, the isolation chip U42 is designated as ADuM1201.

[0011] In one possible implementation, the second power input terminal of the isolation chip U42 is connected to a 5V voltage through a filter capacitor C186.

[0012] In one possible implementation, the level conversion chip U41 is model MAX232.

[0013] In one possible implementation, the T1I terminal of the level conversion chip U41 is electrically connected to the VOB terminal of the isolation chip U42; the R1OUT terminal of the level conversion chip U41 is electrically connected to the VIA terminal of the isolation chip U42.

[0014] In one possible implementation, the V+ terminal of the level conversion chip U41 is connected to a +5V voltage via capacitor C181.

[0015] Beneficial effects: The voltage conversion chip U45 is suitable for converting a 5V input voltage to a 3.3V output voltage, providing a stable operating power supply for the isolation chip U42. The isolation chip U42 is suitable for reducing interference between systems, achieving electrical isolation between the front-end signal source and the subsequent level conversion chip U41, ensuring stable signal transmission to the level conversion chip U41. When outputting a signal, the level conversion chip U41 converts the level signal from the isolation chip U42 into an RS-232 level signal and outputs it from the corresponding output pin to the external RS-232 communication device. When receiving a signal, the level conversion chip U41 converts the level signal input from the external RS-232 device into a TTL / CMOS level, transmits it back to the isolation chip U42, and then transmits it back to the front-end circuit through the isolation chip U42. This application combines electrical isolation and level conversion functions, enhancing anti-interference capability, reducing data transmission error rate, and improving circuit stability and lifespan. It also protects the conversion circuit from high-voltage surges, thereby improving the stability of signal conversion.

[0016] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0018] Figure 1 A partial circuit diagram of the isolation switching circuit according to an embodiment of this application is shown;

[0019] Figure 2 A partial circuit diagram of the isolation switching circuit according to an embodiment of this application is shown;

[0020] Figure 3 A circuit diagram of the CPU chip U15 according to an embodiment of this application is shown;

[0021] Figure 4 The circuit diagram of the MAX232 level conversion chip in the prior art is shown. Detailed Implementation

[0022] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0023] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model or simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0026] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0027] Figure 1 A partial circuit diagram of the isolation switching circuit according to an embodiment of this application is shown; Figure 2 A partial circuit diagram of the isolation switching circuit according to an embodiment of this application is shown; Figure 3 A circuit diagram of the CPU chip U15 according to an embodiment of this application is shown. Figure 1As shown, this isolation conversion circuit includes: a voltage conversion chip U45, an isolation chip U42, and a level conversion chip U41; the input terminal of the voltage conversion chip U45 is connected to a +5V voltage, and the output terminal of the voltage conversion chip U45 is electrically connected to the first power input terminal of the isolation chip U42 to deliver the converted +3.3V voltage to the isolation chip U42; the isolation chip U42 is suitable for bidirectional electrical connection with the CPU chip U15, and the isolation chip U42 is bidirectionally electrically connected to the level conversion chip U41; the level conversion chip U41 is suitable for bidirectional electrical connection with an RS-232 device to transmit the converted signal; a filter capacitor C191 is electrically connected to the input terminal of the voltage conversion chip U45, and filter capacitors C86 and C192 are electrically connected to the output terminal of the voltage conversion chip U45; a filter capacitor C185 is electrically connected to the first power input terminal of the isolation chip U42.

[0028] It should be noted that the voltage conversion chip U45 converts a 5V input voltage to a 3.3V output voltage, providing a stable power supply for the isolation chip U42. The isolation chip U42 reduces interference between systems and achieves electrical isolation between the front-end signal source and the subsequent level conversion chip U41. This ensures stable signal transmission to the level conversion chip U41, which converts the level signal from the isolation chip U42 into an RS-232 level signal and outputs it from the corresponding output pin to an external RS-232 communication device. When receiving a signal, the level conversion chip U41 converts the level signal input from the external RS-232 device into a TTL / CMOS level and transmits it back to the isolation chip U42, which then transmits it back to the front-end circuit. This application combines electrical isolation and level conversion functions, enhancing anti-interference capabilities and protecting the conversion circuit from high-voltage surges.

[0029] In one possible implementation, the voltage converter chip U45 is model TPS75733KTT. The power input terminal (pin 2) of the voltage converter chip U45 is connected to a +5V voltage via capacitor C191; the EN terminal (pin 1) of the voltage converter chip U45 is grounded; the GND terminal (pin 3) of the voltage converter chip U45 is grounded; and the VO terminal (pin 4) of the voltage converter chip U45 outputs the converted +3.3V voltage. One terminal of both filter capacitors C86 and C192 is electrically connected to the VO terminal (pin 4) of the voltage converter chip U45, and the other terminals of both filter capacitors C86 and C192 are grounded.

[0030] In one possible implementation, the isolation chip U42 is model ADuM1201. The second power input terminal (pin 8) of the isolation chip U42 is connected to a +5V voltage via a filter capacitor C186, and the first power input terminal (pin 1) is connected to a +3.3V voltage via a filter capacitor C185. The VIB terminal (pin 3) of the isolation chip U42 is used to electrically connect to the CPU chip U15 to receive unconverted signals, and the VOA terminal (pin 2) of the isolation chip U42 is used to electrically connect to the CPU chip U15 to output converted signals to the CPU chip U15. The GND terminals (pins 4 and 5) of the isolation chip U42 are grounded. The VOB terminal (pin 6) of the isolation chip U42 is electrically connected to the T1IN terminal (pin 11) of the level conversion chip U41; and the VIA terminal (pin 7) of the isolation chip U42 is electrically connected to the R1IOUT terminal (pin 12) of the level conversion chip U41.

[0031] In one possible implementation, the level shifter chip U41 is model MAX232. The C1- terminal (pin 3) of the level shifter chip U41 is electrically connected to the C1+ terminal (pin 1) of the level shifter chip U41 via capacitor C182; the C2- terminal (pin 5) of the level shifter chip U41 is electrically connected to the C2+ terminal (pin 4) of the level shifter chip U41 via capacitor C184; the T1IN terminal (pin 11) of the level shifter chip U41 is electrically connected to the VOB terminal (pin 6) of the isolation chip U42; and the R1IOUT terminal (pin 12) of the level shifter chip U41 is electrically connected to the isolation chip U42. The VIA terminal (pin 7) of the level converter chip U41 is electrically connected; the VCC terminal (pin 16) of the level converter chip U41 is connected to +5V voltage through capacitor C180; the V+ terminal (pin 2) of the level converter chip U41 is connected to +5V voltage through capacitor C181; the V- terminal (pin 6) of the level converter chip U41 is grounded through capacitor C183; the TIOUT terminal (pin 14) and the R1IN terminal (pin 13) of the level converter chip U41 are suitable for electrical connection with external RS-232 communication equipment.

[0032] like Figure 3 As shown, the CPU chip U15 is model TMS320F28335; the SCITXDA terminal (pin 141) of the CPU chip U15 is electrically connected to the VOA terminal (pin 2) of the isolation chip U42, and the SCITXDA terminal (pin 2) of the CPU chip U15 is electrically connected to the VIB terminal (pin 3) of the isolation chip U42.

[0033] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An isolated conversion circuit, characterized by, include: Voltage conversion chip U45, isolation chip U42, level conversion chip U41; The input terminal of the voltage conversion chip U45 is connected to a +5V voltage, and the output terminal of the voltage conversion chip U45 is electrically connected to the first power input terminal of the isolation chip U42 to deliver the converted +3.3V voltage to the isolation chip U42. The isolation chip U42 is suitable for bidirectional electrical connection with the CPU chip U15, the isolation chip U42 is bidirectionally electrically connected with the level conversion chip U41, and the level conversion chip U41 is suitable for bidirectional electrical connection with RS-232 devices to transmit the converted signal; The input terminal of the voltage conversion chip U45 is electrically connected to a filter capacitor C191, and the output terminal of the voltage conversion chip U45 is electrically connected to a filter capacitor C86 and a filter capacitor C192. The first power input terminal of the isolation chip U42 is electrically connected to a filter capacitor C185.

2. The isolated conversion circuit of claim 1, wherein, The voltage conversion chip U45 is model TPS75733KTT.

3. The isolated conversion circuit of claim 1, wherein, The isolation chip U42 is model ADuM1201.

4. The isolated conversion circuit of claim 3, wherein, The second power input terminal of the isolation chip U42 is connected to a +5V voltage through a filter capacitor C186.

5. The isolated conversion circuit of claim 3, wherein, The level conversion chip U41 is model MAX232.

6. The isolated conversion circuit of claim 5, wherein, The T1I terminal of the level conversion chip U41 is electrically connected to the VOB terminal of the isolation chip U42; the R1OUT terminal of the level conversion chip U41 is electrically connected to the VIA terminal of the isolation chip U42.

7. The isolated conversion circuit of claim 6, wherein, The V+ terminal of the level conversion chip U41 is connected to a +5V voltage through capacitor C181; the VCC terminal of the level conversion chip U41 is connected to a +5V voltage through capacitor C180.

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