A high-power anti-reverse power control and detection circuit and method

Abstract

The present application relates to a kind of high-power anti-reverse power distribution control and detection circuit and method, belong to power distribution control and detection circuit technical field, solve how to prevent instruction misexecution and not execute, guarantee the high reliability and high security of power distribution output Problem.Circuit includes: isolation drive circuit is controlled on and off to MOSFET switching transistor by transistor control signal and detects on-off state;Level conversion circuit converts control signal into transistor control signal, and state signal is converted to level and provided to FPGA;FPGA is communicated with host computer in CAN communication mode to provide transistor state signal to it and receive control signal;Power supply circuit provides power supply voltage to isolation drive circuit, level conversion circuit and FPGA, receives disconnect control signal in 485 communication mode to zero power supply voltage.Working full-process state detection provides sufficient criterion for power distribution execution situation.When CAN communication fails, RS485 communication is used to cut off power distribution output, improve the safety of system.

Description

Technical Field

[0001] This invention relates to the field of power distribution control and detection circuit technology, and in particular to a high-power anti-reverse power distribution control and detection circuit and method. Background Technology

[0002] Modern power distribution systems often rely on traditional mechanical relays or monitoring equipment for their switches. This relay-based system struggles to achieve real-time switch status monitoring, resulting in weak real-time monitoring capabilities. Power distribution faults typically require manual inspection or reactive responses, failing to capture transient faults or enable high-frequency monitoring. Furthermore, relays rely on mechanical contacts for switching operations; frequent switching leads to contact wear, oxidation, or adhesion, reducing their lifespan. The switching life of a typical mechanical relay is around 100,000 cycles, far lower than the millions or even higher lifespan of solid-state power distribution switches based on MOSFETs.

[0003] Modern power distribution systems rely more on customized hardware or complex wiring, resulting in high costs, long deployment cycles, and large space requirements. They cannot achieve compatibility and productization between different load systems. Therefore, there is an urgent need for a universal, modular, highly reliable, highly secure, and fully detectable power distribution circuit. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a high-power anti-reverse power distribution control and detection circuit to solve the problems of how to execute power distribution output commands and detect power distribution output status, prevent command mis-execution and non-execution, and ensure high reliability and high safety of power distribution output.

[0005] On one hand, embodiments of the present invention provide a high-power anti-reverse power distribution control and detection circuit, comprising: an isolation drive circuit, used to control the on / off state of a MOSFET switching transistor in the power distribution circuit to be detected by means of a transistor control signal and to detect the on / off state of the MOSFET switching transistor to obtain a transistor status signal; a level conversion circuit, used to convert a control signal provided by an FPGA into the transistor control signal, and to level-convert the transistor status signal and provide it to the FPGA; the FPGA, used to communicate with a host computer via CAN communication to provide the level-converted transistor status signal to the host computer and to receive the control signal from the host computer; and a power supply circuit, used to provide power supply voltage to the isolation drive circuit, the level conversion circuit and the FPGA, wherein the power supply voltage of the isolation drive circuit, the level conversion circuit and the FPGA is set to zero based on the received off signal of the MOSFET switching transistor.

[0006] The beneficial effects of the above technical solutions are as follows: (1) The present invention adopts a reliability design method based on "serial and parallel" execution to achieve high system reliability. (2) The present invention adopts full-process status detection technology to provide sufficient criteria for power distribution execution. (3) The present invention adopts CAN and RS485 communication methods. When CAN communication fails, RS485 communication can be used to cut off the power distribution output, thereby improving the system's security.

[0007] Based on further improvements to the above circuit, the power distribution circuit to be tested includes a first branch and a second branch. The isolation drive circuit includes a first isolation drive circuit, a second isolation drive circuit, a third isolation drive circuit, and a fourth isolation drive circuit. The first branch includes a first ideal diode, a second ideal diode, a first MOSFET switching transistor, and a second MOSFET switching transistor connected in series. The second branch includes a third ideal diode, a fourth ideal diode, a third MOSFET switching transistor, and a fourth MOSFET switching transistor connected in series. The first isolation drive circuit, the second isolation drive circuit, the third isolation drive circuit, and the fourth isolation drive circuit are respectively used to control the first MOSFET switching transistor, the second MOSFET switching transistor, the third MOSFET switching transistor, and the fourth MOSFET switching transistor.

[0008] Based on further improvements to the above circuit, each isolation drive circuit is used to isolate the operating power supply voltage of the isolation drive circuit from the MOSFET-side power supply. Each isolation drive circuit includes a detection input terminal, a detection output terminal, a control input terminal, and a control output terminal. The detection input terminal is used to detect the state signal of the MOSFET switching transistor at the source of the MOSFET switching transistor via the detection input terminal. The detection output terminal is used to output the state voltage and provide the state voltage to the level conversion circuit. The control input terminal is used to receive the transistor control signal. The control output terminal is used to provide the transistor control signal to the gate of the MOSFET switching transistor.

[0009] Based on further improvements to the above circuit, the isolation drive circuit also includes an isolation drive chip, diode D18 or D20, first resistor R621 or R650, second resistor R632 or R652, third resistor R636 or R657, fourth resistor R637 or R658, first capacitor C302 or C327, second capacitor C298 or C325, and third capacitor C296 or C312. The anode of diode D18 or D20 is connected to the detection input terminal JC1 or JC2, and the cathode of diode D18 or D20 is connected to the source of the MOSFET switching transistor. The detection output terminal FBK1 or FBK2 is connected to the input terminal of the level conversion circuit. One end of the first capacitor is grounded, and the other end of the first capacitor is connected to the control... The input terminal is IN1 or IN2; one end of the first resistor and the second resistor are respectively connected to the first control output terminal N_OUT1 or N_OUT2 and the second control output terminal P_OUT1 or P_OUT2, and the other end of the first resistor and the second resistor are connected to the gate of the MOSFET switching transistor; one end of the third resistor and the fourth resistor are connected to the isolation ground ISOGND and the drain of the MOSFET switching transistor, and the other end of the third resistor is connected to one end of the second capacitor, and the other end of the second capacitor and the other end of the fourth resistor are connected to the gate of the MOSFET switching transistor; one end of the third capacitor is grounded, and the other end of the third capacitor is connected to the power supply voltage and the power supply pin of the isolation drive module.

[0010] Based on further improvements to the above circuit, each of the first ideal diode and the second ideal diode is a combination of a control diode and a MOSFET control transistor, wherein the anode of the control diode is connected to the source of the MOSFET control transistor; the cathode of the control diode is connected to the drain of the MOSFET control transistor, and the gate of the MOSFET control transistor is controlled by a control chip to control the conduction sequence of the first ideal diode and the second ideal diode.

[0011] Based on further improvements to the above circuit, the control chip includes a first control chip U52 and a second control chip U54, wherein the input pin of the first control chip is connected to the anode of the first ideal diode; the gate pin of the first control chip is connected to the gate of the MOSFET control transistor in the first ideal diode; the output pin of the first control chip is connected to the cathode of the first ideal diode and the input pin of the second control chip; the gate pin of the second control chip is connected to the gate of the MOSFET control transistor in the second ideal diode; and the output pin of the second control chip is connected to the cathode of the second ideal diode, wherein a fourth capacitor is connected between the power supply voltage output pin and the ground output pin of the first control chip, the power supply voltage output pin of the first control chip is connected to the anode of the first ideal diode via a fifth resistor; the fifth capacitor is connected between the power supply voltage output pin and the ground output pin of the second control chip, and the power supply voltage output pin of the second control chip is connected to the cathode of the second ideal diode via a sixth resistor.

[0012] Based on further improvements to the above circuit, the power supply circuit includes a power input pin SVIN, a power output pin VOUT, a working mode selection pin MODE, an internal regulator output pin INTVCC, an output enable pin RUN, and a power output status pin PGOOD. The power input pin SVIN includes a first power input pin SVIN1, a second power input pin SVIN2, and a third power input pin SVIN3, all used to receive power from the power supply circuit. The power output status pin PGOOD includes a first pin PGOOD1, a second pin PGOOD2, and a third pin PGOOD3. The first pin PGOOD1, the second pin PGOOD2, and the third pin PGOOD3 are connected via two resistors to the working mode selection pin MODE1 and the internal regulator output pins INTVCC1, MODE2 and INTVCC2, and MODE3 and the internal regulator output pins respectively. INTVCC3; The output enable pin RUN includes a first output enable pin RUN1, a second output enable pin RUN2, and a third output enable pin RUN3. The first output enable pin RUN1 is connected to the Pow_OFF output signal pin of the FPGA based on 485 communication. The second output enable pin RUN2 is connected to the connection point of two resistors between the operating mode selection pin MODE1 and the internal regulator output pin INTVCC1. The third output enable pin RUN3 is connected to the connection point of two resistors between the operating mode selection pin MODE2 and the internal regulator output pin INTVCC2. The power output pin VOUT includes a first output pin VOUT1, a second output pin VOUT2, and a third output pin VOUT3. The first power supply voltage is output via the first output pin VOUT1, the second power supply voltage is output via the second output pin VOUT2, and the third power supply voltage is output via the third output pin VOUT3.

[0013] Based on further improvements to the above circuit, a first power supply voltage is provided to the FPGA via the first output pin VOUT1; a second power supply voltage is provided to the output level conversion circuit via the second output pin VOUT2; and a third power supply voltage is provided to the isolation drive circuit via the third output pin VOUT3, wherein the first power supply voltage, the second power supply voltage, and the third power supply voltage are different.

[0014] Based on further improvements to the above circuit, the FPGA sets or zeros the control input terminal of the isolation drive circuit according to the control signal received from the host computer.

[0015] On the other hand, embodiments of the present invention provide a high-power anti-reverse power distribution control and detection method, comprising: using a transistor control signal through an isolation drive circuit to control the on / off state of a MOSFET switching transistor in a power distribution circuit to be detected and detecting the on / off state of the MOSFET switching transistor to obtain a transistor status signal; converting a control signal provided by an FPGA into the transistor control signal through a level conversion circuit, and level-converting the transistor status signal and providing it to the FPGA; communicating with a host computer via CAN communication through the FPGA to provide the level-converted transistor status signal to the host computer and receive the control signal from the host computer; and providing power supply voltage to the isolation drive circuit, the level conversion circuit, and the FPGA through a power supply circuit, wherein the power supply voltage of the isolation drive circuit, the level conversion circuit, and the FPGA is set to zero based on the received off signal of the MOSFET switching transistor.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0017] 1. Through circuit design, each power distribution branch can withstand a 56V reverse peak voltage and each power distribution branch has a rated current of 45A. The rated current value of each power distribution branch can be increased by parallel connection according to different loads, so as to realize the generalization and productization of power distribution control modules.

[0018] 2. The present invention proposes a high-power anti-reverse power distribution control and detection circuit, with each branch having a rated voltage of 28V and a rated current of 5A. Different numbers of branches can be connected in parallel according to the actual load requirements of different power distribution systems. For example, if a rated current of 10A is required, the circuit of the present invention can be connected in parallel to improve the adaptability and versatility for different power distribution system requirements.

[0019] 3. When each power distribution branch has different input loads but the same load, by activating only one power distribution branch, the status of each branch can be correctly detected, achieving status detectability. Through circuit design and component selection, reverse current flow from other branches to this branch can be prevented.

[0020] 4. For CMOS circuit structures, latch-up can be effectively prevented simply by designing the chip power supply method, thus effectively reducing the types and number of components.

[0021] 5. This invention uses CAN and RS485 communication methods. When CAN communication fails, RS485 communication can be used to cut off the power distribution output, thereby improving the system's safety.

[0022] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0023] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0024] Figure 1 This is a schematic diagram of the single-circuit power distribution branch structure of the present invention;

[0025] Figure 2 This is a diagram showing the internal structure of the isolation drive module of the present invention;

[0026] Figure 3 This is a circuit diagram of the power distribution switch control and status detection of the present invention;

[0027] Figure 4 This is a connection diagram between the power distribution control and detection section and the FPGA main controller of the present invention;

[0028] Figure 5 This is a circuit diagram showing the sequential conduction of the two ideal diodes of this invention;

[0029] Figure 6 This is a circuit diagram of the power supply circuit based on CAN communication of the present invention;

[0030] Figure 7 This is a flowchart of a high-power reverse power distribution control and detection method according to an embodiment of the present invention. Detailed Implementation

[0031] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0032] refer to Figure 4 A specific embodiment of the present invention discloses a high-power anti-reverse power distribution control and detection circuit, comprising: an isolation drive circuit, a level conversion circuit, an FPGA, and a power supply circuit.

[0033] An isolation drive circuit is used to control the on / off state of the MOSFET switching transistor in the power distribution circuit to be tested by means of a transistor control signal, and to detect the on / off state of the MOSFET switching transistor to obtain a transistor status signal.

[0034] refer to Figure 1 The power distribution circuit under test includes a first branch (i.e., bus 1) and a second branch (i.e., bus 2). The isolation drive circuit includes a first isolation drive circuit, a second isolation drive circuit, a third isolation drive circuit, and a fourth isolation drive circuit. The first branch includes a first ideal diode, a second ideal diode, a first MOSFET switching transistor, and a second MOSFET switching transistor connected in series. The second branch includes a third ideal diode, a fourth ideal diode, a third MOSFET switching transistor, and a fourth MOSFET switching transistor connected in series. The first, second, third, and fourth isolation drive circuits are used to control the first, second, third, and fourth MOSFET switching transistors, respectively.

[0035] refer to Figure 2 and Figure 3 Each isolation drive circuit isolates its operating power supply voltage from the MOSFET-side power supply. Each isolation drive circuit includes a detection input, a detection output, a control input, and a control output. The detection input detects the state signal of the MOSFET switching transistor at its source. The detection output outputs a state voltage and provides it to a level shifting circuit. The control input receives a transistor control signal. The control output provides the transistor control signal to the gate of the MOSFET switching transistor.

[0036] refer to Figure 3 The first and third isolation drive circuits are obtained through the isolation drive chip MD0510-DI and peripheral circuits. The isolation drive circuit includes the isolation drive chip MD0510-DI, diode D18 or D20, first resistor R621 or R650, second resistor R632 or R652, third resistor R636 or R657, fourth resistor R637 or R658, first capacitor C302 or C327, second capacitor C298 or C325, and third capacitor C296 or C312.

[0037] The anode of diode D18 is connected to the detection input terminal JC1, and the cathode of diode D18 is connected to the source of the MOSFET switching transistor. The detection output terminal FBK1 is connected to the input terminal of the level conversion circuit. One end of the first capacitor C302 is grounded, and the other end of the first capacitor C302 is connected to the control input terminal IN1. One end of the first resistor R621 and the second resistor R632 are connected to the first control output terminal N_OUT1 and the second control output terminal P_OUT1, respectively, and the other ends of the first resistor R621 and the second resistor R632 are connected to the gate of the first MOSFET switching transistor. One end of the third resistor R636 and the fourth resistor R637 are connected to the isolation ground ISOGND and the drain of the first MOSFET switching transistor, and the other end of the third resistor R636 is connected to one end of the second capacitor C298. The other ends of the second capacitor C298 and the fourth resistor R637 are connected to the gate of the first MOSFET switching transistor. One end of the third capacitor C296 is grounded, and the other end of the third capacitor C296 is connected to the power supply voltage 5V and the power supply pin VCC1 of the isolation drive module.

[0038] The anode of diode D20 is connected to the detection input terminal JC2, and the cathode of diode D20 is connected to the source of the MOSFET switching transistor. The detection output terminal FBK2 is connected to the input terminal of the level conversion circuit. One end of the first capacitor C327 is grounded, and the other end of the first capacitor C327 is connected to the control input terminal IN2. One end of the first resistor R650 and the second resistor R652 are connected to the first control output terminal N_OUT2 and the second control output terminal P_OUT2, respectively, and the other ends of the first resistor R650 and the second resistor R652 are connected to the gate of the third MOSFET switching transistor. One end of the third resistor R657 and the fourth resistor R658 are connected to the isolation ground ISOGND and the drain of the third MOSFET switching transistor, and the other end of the third resistor R657 is connected to one end of the second capacitor C325. The other ends of the second capacitor C325 and the fourth resistor R658 are connected to the gate of the third MOSFET switching transistor. One end of the third capacitor C312 is grounded, and the other end of the third capacitor C312 is connected to the power supply voltage 5V and the power supply pin VCC2 of the isolation drive module.

[0039] Similarly, another isolated driver chip, MD0510-DI, can be used to control the second and fourth MOSFET switching transistors. The specific connection circuit is similar to that of the first and third MOSFET switching transistors.

[0040] refer to Figure 4The level conversion circuit is used to convert the control signals (0~3.3V) provided by the FPGA into transistor control signals (0~5V), and to convert the detected transistor status signals (0~5V) into status signals (0~3.3V) provided to the FPGA.

[0041] refer to Figure 4 The FPGA is used to communicate with the host computer via CAN communication to provide the host computer with level-converted transistor status signals and to receive control signals from the host computer. Specifically, the FPGA sets or resets the control input terminal of the isolation drive circuit according to the control signal received from the host computer.

[0042] refer to Figure 4 The power supply circuit provides power to the isolation drive circuit, level shifting circuit, and FPGA. The output enable pin of the power supply circuit receives an enable control signal from the Pow_OFF pin of the FPGA main control chip via RS485 communication. Based on the received MOSFET switching transistor's turn-off signal, the power supply voltage of the isolation drive circuit, level shifting circuit, and FPGA is set to zero. When the output enable pin is high, the power supply circuit operates normally; when the output enable pin is low, the power supply circuit enters the off state, i.e., is set to zero. Therefore, RS485 communication serves as an alternative to CAN communication, allowing power output to be cut off when CAN communication fails.

[0043] refer to Figure 6 The power supply circuit includes the power input pin SVIN, the power output pin VOUT, the operating mode selection pin MODE, the internal regulator output pin INTVCC, the output enable pin RUN, and the power output status pin PGOOD.

[0044] The power input pins SVIN include the first power input pin SVIN1, the second power input pin SVIN2, and the third power input pin SVIN3, all of which are used to receive the 12V power supply from the power supply circuit.

[0045] The power output status indicator PGOOD includes three pins: PGOOD1, PGOOD2, and PGOOD3. PGOOD1 is connected to the operating mode selection pin MODE1 and the internal regulator output pin INTVCC1 via resistors R664 and R665. PGOOD2 is connected to the operating mode selection pin MODE2 and the internal regulator output pin INTVCC2 via resistors R667 and R670. PGOOD3 is connected to the operating mode selection pin MODE3 and the internal regulator output pin INTVCC3 via resistors R680 and R681.

[0046] The output enable pin RUN includes a first output enable pin RUN1, a second output enable pin RUN2, and a third output enable pin RUN3. The first output enable pin RUN1 is connected to the output signal pin Pow_OFF of the FPGA based on 485 communication; the second output enable pin RUN2 is connected to the junction of two resistors between the operating mode selection pin MODE1 and the internal regulator output pin INTVCC1; the third output enable pin RUN3 is connected to the junction of two resistors between the operating mode selection pin MODE2 and the internal regulator output pin INTVCC2.

[0047] The power output pin VOUT includes a first output pin VOUT1, a second output pin VOUT2, and a third output pin VOUT3. The first power supply voltage is output through the first output pin VOUT1, the second power supply voltage is output through the second output pin VOUT2, and the third power supply voltage is output through the third output pin VOUT3.

[0048] Specifically, a first power supply voltage is provided to the FPGA via the first output pin VOUT1; a second power supply voltage is provided to the output level conversion circuit via the second output pin VOUT2; and a third power supply voltage is provided to the isolation drive circuit via the third output pin VOUT3. The first, second, and third power supply voltages are different. Specifically, the first power supply voltage is 1.5V, the second power supply voltage is 3.3V, and the third power supply voltage is 5V.

[0049] Compared with the prior art, the high-power anti-reverse power distribution control and detection circuit provided in this embodiment has the following technical effects: (1) The present invention adopts a reliability design method based on "series-parallel" execution to achieve high system reliability. (2) The present invention adopts full-process status detection technology to provide sufficient criteria for power distribution execution. (3) The present invention adopts CAN and RS485 communication methods. When CAN communication fails, RS485 communication can be used to cut off the power distribution output, thereby improving the system's safety.

[0050] refer to Figure 5 Each of the first and second ideal diodes is a combination of a control diode and a MOSFET control transistor. For example, the first ideal diode is a combination of a first control diode and a first MOSFET control transistor. The second ideal diode is a combination of a second control diode and a second MOSFET control transistor.

[0051] The anode of the control diode is connected to the source of the MOSFET control transistor; the cathode of the control diode is connected to the drain of the MOSFET control transistor, wherein the gate of the MOSFET control transistor is controlled by a control chip to control the conduction sequence of the first ideal diode and the second ideal diode. For example, the anode of the first control diode is connected to the source of the first MOSFET control transistor, and the cathode of the first control diode is connected to the drain of the first MOSFET control transistor; the anode of the second control diode is connected to the source of the second MOSFET control transistor, and the cathode of the second control diode is connected to the drain of the second MOSFET control transistor; the anode of the third control diode is connected to the source of the third MOSFET control transistor, and the cathode of the third control diode is connected to the drain of the third MOSFET control transistor; and the anode of the fourth control diode is connected to the source of the fourth MOSFET control transistor; the cathode of the fourth control diode is connected to the drain of the fourth MOSFET control transistor.

[0052] refer to Figure 5The control chip includes a first control chip U52 and a second control chip U54. The input pin of the first control chip U52 is connected to the anode of a first ideal diode; the gate pin of the first control chip U52 is connected to the gate of the first MOSFET control transistor in the first ideal diode; the output pin of the first control chip U52 is connected to the cathode of the first ideal diode and the input pin of the second control chip; the gate pin of the second control chip U54 is connected to the gate of the second MOSFET control transistor in the second ideal diode; and the output pin of the second control chip U54 is connected to the cathode of the second ideal diode. A fourth capacitor C236 is connected between the power supply voltage output pin VDD and the ground output pin GND of the first control chip; the power supply voltage output pin of the first control chip is connected to the anode of the first ideal diode via a fifth resistor R345; a fifth capacitor C242 is connected between the power supply voltage output pin VDD and the ground output pin GND of the second control chip; and the power supply voltage output pin VDD of the second control chip is connected to the cathode of the second ideal diode via a sixth resistor R396.

[0053] refer to Figure 7 Another specific embodiment of the present invention discloses a high-power anti-reverse power distribution control and detection method, comprising: in step S701, using a transistor control signal through an isolation drive circuit to control the on / off state of the MOSFET switching transistor in the power distribution circuit to be detected and to obtain a transistor status signal; in step S702, using a level conversion circuit to convert the control signal provided by the FPGA into a transistor control signal, and level-converting the detected transistor status signal and providing it to the FPGA; in step S703, using the FPGA to communicate with a host computer via CAN communication to provide the level-converted transistor status signal to the host computer and to receive control signals from the host computer; and in step S704, using a power supply circuit to provide power voltage to the isolation drive circuit, the level conversion circuit, and the FPGA. The power supply circuit communicates with the FPGA via RS485 communication. Specifically, the output enable pin of the power supply circuit receives an enable control signal from the Pow_OFF pin of the FPGA main control chip via RS485 communication. Based on the received MOSFET switching transistor off signal, the power supply voltage of the isolation drive circuit, the level conversion circuit, and the FPGA is set to zero.

[0054] The technical solution of this invention is as follows: when the output voltage of the distribution branch is higher than the bus voltage, it can prevent large current backflow and correctly detect the status of the distribution switch; when two distribution branches are connected to the same load output and there is a voltage difference between the bus supply voltages of the two distribution branches, it can prevent current backflow to the other branch and correctly detect the status of each distribution switch; the reliability of the distribution branch is improved by using two ideal diode control chips in series, and the power supply of the second ideal diode control chip is taken from the output of the first ideal diode control chip, which can effectively prevent latch-up.

[0055] The advantages of this invention compared to the prior art are:

[0056] (1) Through circuit design, each power distribution branch can withstand a 56V reverse peak voltage and the rated current of each power distribution branch is 45A. The rated current value of each power distribution branch can be increased by parallel connection according to different loads, so as to realize the generalization and productization of power distribution control module.

[0057] (2) When the power supply input of each distribution branch is different but the load is the same, the status of each distribution branch can be correctly detected when only one distribution branch is turned on, thus achieving status detectability. By designing the circuit and selecting the components, it is possible to prevent the current from other branches from flowing back into this branch.

[0058] (3) For CMOS circuit structure, latch-up can be effectively prevented by designing the chip power supply method, and the types and number of components can be effectively reduced.

[0059] (4) The present invention uses CAN and RS485 communication methods. When CAN communication fails, RS485 communication can be used to cut off the power distribution output, thereby improving the system's security.

[0060] In the following text, refer to Figures 1 to 6 The high-power reverse power distribution control and detection circuit according to embodiments of the present invention will be described in detail by way of specific examples.

[0061] like Figure 1As shown, the power distribution execution section comprises two branches, each containing two ideal diodes and two power distribution switches connected in series. The power distribution switch MOSFETs are controlled by isolation drive modules. Each MOSFET's drive signal originates from a different isolation drive module, preventing power distribution control failure if one module fails. When a power distribution switch on one branch fails (i.e., a fault occurs at one level), the power output can be controlled via the other branch. When another power distribution switch on both branches fails, the circuit breaker design is implemented to prevent malfunctions in downstream equipment. When one ideal diode on one branch fails, the other ideal diode provides anti-reverse current protection. The selected MOSFET model is C100N45S5, with a rated current of 45A and a withstand voltage of 100V. When the power supply voltage is 28V and the circuit output voltage is 56V, each MOSFET needs to withstand a 42V reverse peak voltage. Therefore, the power distribution switch MOSFETs are selected with a withstand voltage of 100V to meet the Class I derating requirements.

[0062] like Figure 2 As shown, the MD0510-DI isolation driver module is a unique module consisting of three parts: an isolation power supply, a signal isolation unit, and a MOSFET driver module. The isolation power supply isolates the chip's 5V operating power supply from the MOSFET-side power supply. The control and status terminals can respectively control the on / off state of the MOSFET and detect its status. The MOSFET driver module is used to output the control voltage for the MOSFET. The MD0510-DI isolation driver module can control the on / off state and detect the status of two MOSFET devices.

[0063] like Figure 3 As shown, the IN pin of the MD0510-DI isolation driver module (model C100N45S5) is used to control the on / off state of the MOSFET switch, and its FBK pin is used to detect the MOSFET's on / off state. After power-on, the IN pin of the isolation driver module is low by default, the N_OUT pin outputs 10~13V, capacitors C298 and C325 are discharging, the MOSFET driver terminal is low, the MOSFET is off, the JC pin and FBK pin of the isolation driver module are both high. When the IN pin inputs a high level, the P_OUT pin outputs 10~13V, capacitors C298 and C325 are charging, the MOSFET driver terminal is high, the MOSFET is on, the JC pin and FBK pin of the isolation driver module are both low.

[0064] When the input voltages of the two branch busbars are inconsistent, and both distribution switches on the high-voltage side branch are on while the other branch distribution switch is off, the isolation drive module can accurately reflect the on / off state of the MOSFETs by actually testing the voltage across them. This enables full detection of the power distribution status, eliminating any undetectable or unmeasurable power distribution states and providing sufficient criteria for judging the power distribution execution. When there is an abnormal reverse peak voltage in the power distribution output, the MD0510-DI isolation drive module can correctly detect the MOSFET's on / off state. The detected state is always the actual on state of the MOSFETs, unaffected by reverse peak voltage interference.

[0065] like Figure 4 As shown, the control terminal (IN pin) and status terminal (FBK pin) of the isolation drive module MD0510-DI are converted to 3.3V via a level converter B54ACS164245SA and then connected to the FPGA main control chip. The FPGA main control chip controls the MOSFET switching on and off via CAN communication and provides real-time feedback of the MOSFET switching status at a frequency of 250ms to achieve real-time detection of the entire power distribution control status. The principle of MOSFET switching status control and detection is shown in Table 1.

[0066] Table 1. Correspondence between MOSFET switching control and state detection

[0067]

[0068] like Figure 5 As shown, the IN pin of the lower 4357 control chip U54 is connected to the OUT pin of the upper 4357 control chip U52. When an external 28V power supply is input through the Ur1 pin, the upper MOSFET device M3 turns on first. After M3 turns on, it supplies power to the lower 4357 control chip U54. The output voltage of the 4357 control chip U54 then drives the lower MOSFET device M7 to turn on. This connection method allows the 4357 control chips to be powered on sequentially, and the MOSFET devices to be turned on sequentially, effectively preventing CMOS circuit latch-up.

[0069] This invention includes two FPGA main control chips: one FPGA main control chip for implementing dual-channel CAN communication, and the other FPGA main control chip for implementing dual-channel RS-485 communication. CAN communication is mainly used for power distribution switch control and status detection, while RS-485 communication is mainly used for uploading information such as power distribution branch current and supply voltage. Figure 6As shown, the FPGA main control chip based on CAN communication is powered by the HCE4644MB power module. The HCE4644MB power module has a 12V input and four outputs. The RUN pin is the control output enable pin. When the first 1.5V output is triggered, the PGOOD pin outputs a high level, triggering the second 3.3V output. Similarly, when the second output is triggered, the third 5V output is triggered. Figure 6 The connection method allows for sequential output of 1.5V, 3.3V, and 5V. The first 1.5V output enable pin (RUN) is connected to the Pow_OFF output signal of the FPGA main control chip based on 485 communication. The Pow_OFF output signal is high by default.

[0070] The FPGA main control chip and the MD0510-DI isolation driver module, which are based on CAN communication, are both powered by voltages from... Figure 6 The output voltage of the HCE4644MB power module is controlled by a 485 command. When the FPGA main control chip based on CAN communication malfunctions and cannot control the power distribution branch, the Pow_OFF output signal can be set to 0. At this time, the HCE4644MB power module output voltage is 0V, and the FPGA main control chip and isolation driver module based on CAN communication are powered off. Figure 3 As shown, the control terminal (IN pin) of the isolation drive module is pulled low to ground, the power distribution switch is turned off, realizing the product's protection design and timely disconnecting the external power supply from the downstream circuit.

[0071] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0072] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-power reverse power distribution control and detection circuit, characterized in that, include: An isolation drive circuit is used to control the on / off state of the MOSFET switching transistor of the power distribution circuit to be tested through a transistor control signal and to detect the on / off state of the MOSFET switching transistor to obtain a transistor state signal. A level conversion circuit is used to convert the control signals provided by the FPGA into control signals for the transistors, and to perform level conversion on the transistor status signals and provide them to the FPGA. The FPGA is used to communicate with the host computer via CAN communication to provide the level-converted transistor status signal to the host computer and to receive the control signal from the host computer. as well as A power supply circuit is provided to supply power voltage to the isolation drive circuit, the level conversion circuit, and the FPGA, wherein the power supply voltage of the isolation drive circuit, the level conversion circuit, and the FPGA is set to zero based on the received turn-off signal of the MOSFET switching transistor. The power distribution circuit to be tested includes a first branch, which includes a first ideal diode, a second ideal diode, a first MOSFET switching transistor, and a second MOSFET switching transistor connected in series in sequence. Each of the first ideal diode and the second ideal diode is a combination of a control diode and a MOSFET control transistor, wherein the anode of the control diode is connected to the source of the MOSFET control transistor; the cathode of the control diode is connected to the drain of the MOSFET control transistor, wherein the gate of the MOSFET control transistor is controlled by a control chip to control the conduction sequence of the first ideal diode and the second ideal diode; The control chip includes a first control chip U52 and a second control chip U54. The input pin of the first control chip is connected to the anode of the first ideal diode; the gate pin of the first control chip is connected to the gate of the MOSFET control transistor in the first ideal diode; the output pin of the first control chip is connected to the cathode of the first ideal diode and the input pin of the second control chip; the gate pin of the second control chip is connected to the gate of the MOSFET control transistor in the second ideal diode; and the output pin of the second control chip is connected to the cathode of the second ideal diode. A fourth capacitor is connected between the power supply voltage output pin and the ground output pin of the first control chip. The power supply voltage output pin of the first control chip is connected to the anode of the first ideal diode via a fifth resistor. A fifth capacitor is connected between the power supply voltage output pin and the ground output pin of the second control chip. The power supply voltage output pin of the second control chip is connected to the cathode of the second ideal diode via a sixth resistor.

2. The high-power reverse power distribution control and detection circuit according to claim 1, characterized in that, The power distribution circuit to be tested includes a second branch, and the isolation drive circuit includes a first isolation drive circuit, a second isolation drive circuit, a third isolation drive circuit, and a fourth isolation drive circuit, wherein, The second branch includes a third ideal diode, a fourth ideal diode, a third MOSFET switching transistor, and a fourth MOSFET switching transistor connected in sequence, wherein the first isolation driving circuit, the second isolation driving circuit, the third isolation driving circuit, and the fourth isolation driving circuit are respectively used to control the first MOSFET switching transistor, the second MOSFET switching transistor, the third MOSFET switching transistor, and the fourth MOSFET switching transistor.

3. The high-power reverse power distribution control and detection circuit according to claim 2, characterized in that, Each isolation drive circuit is used to isolate the operating power supply voltage of the isolation drive circuit from the power supply on the MOSFET side. Each isolation drive circuit includes a detection input terminal, a detection output terminal, a control input terminal, and a control output terminal. The detection input terminal is used to detect the state signal of the MOSFET switching transistor at the source of the MOSFET switching transistor via the detection input terminal; The detection output terminal is used to output the state voltage corresponding to the state signal of the MOSFET switching transistor and provide the state voltage to the level conversion circuit. The control input terminal is used to receive the transistor control signal; and The control output terminal is used to provide the transistor control signal to the gate of the MOSFET switching transistor.

4. The high-power reverse power distribution control and detection circuit according to claim 3, characterized in that, The isolation drive circuit also includes an isolation drive chip, a diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and a third capacitor, wherein... The anode of the diode is connected to the detection input terminal, and the cathode of the diode is connected to the source of the MOSFET switching transistor; The detection output terminal is connected to the input terminal of the level conversion circuit; One end of the first capacitor is grounded, and the other end of the first capacitor is connected to the control input terminal; One end of the first resistor and one end of the second resistor are respectively connected to the first control output terminal and the second control output terminal, and the other end of the first resistor and the second resistor are connected to the gate of the MOSFET switching transistor. One end of the third resistor and one end of the fourth resistor are connected to the isolation ground ISOGND and the drain of the MOSFET switching transistor, the other end of the third resistor is connected to one end of the second capacitor, and the other end of the second capacitor and the other end of the fourth resistor are connected to the gate of the MOSFET switching transistor. as well as One end of the third capacitor is grounded, and the other end of the third capacitor is connected to the power supply voltage and the power supply pin of the isolation drive circuit.

5. The high-power reverse power distribution control and detection circuit according to claim 1, characterized in that, The power supply circuit includes a power input pin SVIN, a power output pin VOUT, a working mode selection pin MODE, an internal regulator output pin INTVCC, an output enable pin RUN, and a power output status pin PGOOD. The power input pin SVIN includes a first power input pin SVIN1, a second power input pin SVIN2, and a third power input pin SVIN3, all of which are used to receive power from the power supply circuit. The power output normality pin PGOOD includes a first pin PGOOD1, a second pin PGOOD2, and a third pin PGOOD3. The first pin PGOOD1, the second pin PGOOD2, and the third pin PGOOD3 are connected to the working mode selection pin MODE1 and the internal regulator output pin INTVCC1, the working mode selection pin MODE2 and the internal regulator output pin INTVCC2, and the working mode selection pin MODE3 and the internal regulator output pin INTVCC3, respectively, via two resistors. The output enable pin RUN includes a first output enable pin RUN1, a second output enable pin RUN2, and a third output enable pin RUN3. The first output enable pin RUN1 is connected to the Pow_OFF output signal pin of the FPGA based on 485 communication. The second output enable pin RUN2 is connected to the connection point of two resistors between the operating mode selection pin MODE1 and the internal regulator output pin INTVCC1. The third output enable pin RUN3 is connected to the connection point of two resistors between the operating mode selection pin MODE2 and the internal regulator output pin INTVCC2. The power output pin VOUT includes a first output pin VOUT1, a second output pin VOUT2, and a third output pin VOUT3, wherein the first power supply voltage is output through the first output pin VOUT1, the second power supply voltage is output through the second output pin VOUT2, and the third power supply voltage is output through the third output pin VOUT3.

6. The high-power reverse power distribution control and detection circuit according to claim 5, characterized in that, A first power supply voltage is provided to the FPGA via the first output pin VOUT1; A second power supply voltage is provided to the level conversion circuit via the second output pin VOUT2; as well as A third power supply voltage is provided to the isolated drive circuit via the third output pin VOUT3, wherein the first power supply voltage, the second power supply voltage and the third power supply voltage are different.

7. The high-power reverse power distribution control and detection circuit according to claim 6, characterized in that, The FPGA sets or zeros the control input terminal of the isolation drive circuit according to the control signal received from the host computer.

8. A high-power reverse power distribution control and detection method, characterized in that, include: The isolation drive circuit uses transistor control signals to control the on / off state of the MOSFET switching transistor in the power distribution circuit under test, and detects the on / off state of the MOSFET switching transistor to obtain the transistor state signal. The control signals provided by the FPGA are converted into control signals of the transistors through a level conversion circuit, and the transistor status signals are level-converted and provided to the FPGA. The FPGA communicates with the host computer via CAN communication to provide the level-converted transistor status signal to the host computer and receive the control signal from the host computer. as well as A power supply circuit provides power voltage to the isolation drive circuit, the level shifting circuit, and the FPGA, wherein the power supply voltage of the isolation drive circuit, the level shifting circuit, and the FPGA is set to zero based on the received off signal of the MOSFET switching transistor. The power distribution circuit to be tested includes a first branch, which includes a first ideal diode, a second ideal diode, a first MOSFET switching transistor, and a second MOSFET switching transistor connected in series in sequence. Each of the first ideal diode and the second ideal diode is a combination of a control diode and a MOSFET control transistor, wherein the anode of the control diode is connected to the source of the MOSFET control transistor; the cathode of the control diode is connected to the drain of the MOSFET control transistor, wherein the gate of the MOSFET control transistor is controlled by a control chip to control the conduction sequence of the first ideal diode and the second ideal diode; The control chip includes a first control chip U52 and a second control chip U54. The input pin of the first control chip is connected to the anode of the first ideal diode; the gate pin of the first control chip is connected to the gate of the MOSFET control transistor in the first ideal diode; the output pin of the first control chip is connected to the cathode of the first ideal diode and the input pin of the second control chip; the gate pin of the second control chip is connected to the gate of the MOSFET control transistor in the second ideal diode; and the output pin of the second control chip is connected to the cathode of the second ideal diode. A fourth capacitor is connected between the power supply voltage output pin and the ground output pin of the first control chip. The power supply voltage output pin of the first control chip is connected to the anode of the first ideal diode via a fifth resistor. A fifth capacitor is connected between the power supply voltage output pin and the ground output pin of the second control chip. The power supply voltage output pin of the second control chip is connected to the cathode of the second ideal diode via a sixth resistor.

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