Low-level maintaining circuit used for level switching circuit in IO port floating state
By using a low-level maintenance circuit composed of PMOS and NMOS transistors in the level conversion circuit, the problem of maintaining the level in the floating state of the IO port is solved, achieving a low-cost and stable low-level maintenance effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- DIOO MICROCIRCUITS CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-01
AI Technical Summary
Existing technologies struggle to effectively maintain a low level when the I/O port of a level conversion circuit is floating. Furthermore, existing methods require large resistors or currents, resulting in high hardware costs and unstable resistance values that vary with PVT.
A low-level sustaining circuit composed of PMOS transistors M2, M3, and M4 is used to replicate the leakage current through an NMOS current mirror and draw it away from the I/O port. Combined with the size design and process consistency of PMOS transistors M2 and M5, the I/O port is kept at a low level in the floating state.
It achieves a simple and low-cost way to maintain the low level of the I/O port in a floating state. The circuit architecture is simple, adaptable to PVT changes, and reduces leakage current requirements.
Smart Images
Figure CN121966547A_ABST
Abstract
Description
Low-level maintenance circuit for I / O ports in floating state for level conversion circuits Technical Field
[0001] This invention relates to a low-level sustaining circuit, and more particularly to a low-level sustaining circuit for an I / O port in a floating state for a level conversion circuit, belonging to the field of semiconductor integrated circuit technology. Background Technology
[0002] Level conversion chips / devices are widely used in many fields such as chips, consumer electronics, communications, industrial control and the Internet of Things. Their core advantage lies in their ability to efficiently adapt to signal conversion needs between different voltage domains, solving key problems in system interconnection.
[0003] Figure 5 shows a schematic diagram of a prior art level conversion circuit. When the level conversion chip is not communicating, the I / O port typically needs to be in a floating state. The level of the floating I / O port affects the actual user experience. In practical applications, the I / O port usually needs to maintain a low level in the floating state. Figure 3 shows a common I / O port floating state setting: the NMOS gate is connected to a low level, the PMOS gate is connected to a high level, and the pull-up resistor is not connected to the circuit. In this case, the DC state of the floating I / O port depends entirely on the voltage division of the resistors when the NMOS and PMOS are off.
[0004] Common solutions include connecting a large resistor to ground or a fixed current source to the I / O port. However, these methods have significant problems. For example, to maintain low leakage current in the floating state, a large resistor with an excessively large area is required. Furthermore, the resistance values of PMOS and NMOS in the floating state change significantly with PVT, and a linearly changing resistor is unlikely to meet the requirements of maintaining both low leakage current and effective pull-down under PVT conditions. Using a fixed current extraction method also has similar problems. Since the resistance values of PMOS and NMOS in the floating state change significantly with PVT, the value of the extraction current needs to meet the requirements under the worst-case scenario, resulting in a large current being extracted in the floating state. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a low-level maintenance circuit for the floating state of the IO port in a level conversion circuit, so as to maintain the low level of the IO port in the floating state with a low hardware cost.
[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a low-level maintenance circuit for the floating state of the IO port of a level conversion circuit, comprising a PMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, wherein the source of the PMOS transistor M2 is connected to the power supply VCCA, the gate of the PMOS transistor M2 is connected to the signal VGATE, the drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M3 and the gate of the NMOS transistor M4, the drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M6 and the IO port IO_PAD, and the source of the NMOS transistor M3 and the source of the NMOS transistor M4 are grounded.
[0007] Furthermore, the signal VGATE is provided by the gate drive circuit.
[0008] Furthermore, the gate drive circuit includes a PMOS transistor M1, a resistor R1, and a capacitor C1. The source of the PMOS transistor M1 is connected to the power supply VCCA. The gate of the PMOS transistor M1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. The drain of the PMOS transistor M1 is connected to one end of the capacitor C1 and generates a signal VGATE. The other end of the capacitor C1 is grounded.
[0009] Furthermore, the gate of the PMOS transistor M5 is connected to the control signal OS_P, and the source of the PMOS transistor M5 is connected to the power supply VCCA.
[0010] Furthermore, the gate of the NMOS transistor M6 is connected to the control signal OS_N, and the source of the NMOS transistor M6 is grounded.
[0011] Furthermore, the size of the PMOS transistor M2 is larger than that of the PMOS transistor M5, so that the leakage current of the PMOS transistor M2 in the off state is greater than that of the PMOS transistor M5.
[0012] Furthermore, the PMOS transistors M2 and M5 are on a single bare die unit DIE, and the PMOS transistors M2 and M5 are consistent with the process deviation.
[0013] Furthermore, the NMOS transistors M3 and M4 form an NMOS current mirror, and the current ratio flowing through the NMOS transistors M3 and M4 is 1:1.
[0014] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a low-level maintenance circuit for the floating state of the IO port in a level conversion circuit. The circuit architecture is simple and achieves the maintenance of the low level in the floating state of the IO port with low hardware cost. Attached Figure Description
[0015] Figure 1 is a schematic diagram of a low-level maintenance circuit for an I / O port in a floating state for a level conversion circuit according to the present invention.
[0016] Figure 2 is a schematic diagram of the state of signal VGATE when it is powered on according to an embodiment of the present invention.
[0017] Figure 3 is a schematic diagram of the existing I / O port floating state setting scheme.
[0018] Figure 4 is a schematic diagram of a one-shot acceleration circuit for a prior art level conversion chip.
[0019] Figure 5 is a schematic diagram of a prior art level conversion circuit. Detailed Implementation
[0020] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0021] Figure 4 shows a schematic diagram of a one-shot acceleration circuit for a level conversion chip in the prior art. When the chip is in the floating state, the voltage of the control signal OS_P is VCCB, and the voltage of the control signal OS_N is 0.
[0022] As shown in Figure 1, a low-level maintenance circuit for the floating state of the IO port in a level conversion circuit according to the present invention includes a PMOS transistor M2, an NMOS transistor M3, and an NMOS transistor M4. The source of the PMOS transistor M2 is connected to the power supply VCCA, the gate of the PMOS transistor M2 is connected to the signal VGATE, the drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M3, and the gate of the NMOS transistor M4, the drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M6, and the IO port IO_PAD, and the source of the NMOS transistor M3 and the source of the NMOS transistor M4 are grounded.
[0023] The signal VGATE is provided by the gate drive circuit.
[0024] The gate drive circuit includes a PMOS transistor M1, a resistor R1, and a capacitor C1. The source of the PMOS transistor M1 is connected to the power supply VCCA. The gate of the PMOS transistor M1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. The drain of the PMOS transistor M1 is connected to one end of the capacitor C1 and generates a signal VGATE. The other end of the capacitor C1 is grounded.
[0025] The gate of PMOS transistor M5 is connected to the control signal OS_P, and the source of PMOS transistor M5 is connected to the power supply VCCA. The gate of NMOS transistor M6 is connected to the control signal OS_N, and the source of NMOS transistor M6 is grounded.
[0026] The size of PMOS transistor M2 is larger than that of PMOS transistor M5, so that the leakage current of PMOS transistor M2 is greater than that of PMOS transistor M5 in the off state.
[0027] PMOS transistors M2 and M5 are on a single bare die cell DIE, and the PMOS transistors M2 and M5 are consistent with the process deviation.
[0028] NMOS transistors M3 and M4 form an NMOS current mirror, and the current ratio flowing through NMOS transistors M3 and M4 is 1:1.
[0029] The working principle of the low-level maintenance circuit for the floating state of the IO port in this invention is as follows: PMOS transistor M2 is a PMOS transistor of the same type as PMOS transistor M5, and the size of PMOS transistor M2 is larger than that of PMOS transistor M5. This ensures that the leakage current of PMOS transistor M2 is greater than that of PMOS transistor M5 in the off state. Since PMOS transistors M2 and M5 are on the same bare die cell (DIE), their leakage currents are naturally consistent with the process variations. The current flowing through PMOS transistor M2 is replicated by an NMOS current mirror composed of NMOS transistors M3 and M4 and drawn away from the IO port IO_PAD. Because the leakage current of PMOS transistor M2 is greater than that of PMOS transistor M5, the IO port IO_PAD is kept at a low level in the floating state.
[0030] As shown in Figure 2, upon power-up, the power supply VCCA gradually increases. When VCCA rises above the threshold voltage of PMOS transistor M1, M1 is turned on, and VCCA begins charging capacitor C1, causing the signal VGATE to rise until it equals VCCA. At this time, signal VGATE is high, and PMOS transistor M2 is off. Simultaneously, since the voltage of control signal OS_P is VCCB (i.e., control signal OS_P is high), PMOS transistor M5 is also off. In this off-state state, both PMOS transistors M2 and M5 experience leakage current, and the leakage current of M2 is greater than that of M5, thus ensuring that the IO port IO_PAD remains low in the floating state.
[0031] This invention provides a circuit for maintaining a low level in the floating state of an I / O port for a level conversion circuit. The circuit architecture is simple and achieves the maintenance of a low level in the floating state of the I / O port with low hardware cost.
[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. A circuit for maintaining a low level in the floating state of an I / O port in a level conversion circuit, characterized in that: It includes PMOS transistor M2, NMOS transistor M3, and NMOS transistor M4. The source of PMOS transistor M2 is connected to the power supply VCCA, the gate of PMOS transistor M2 is connected to the signal VGATE, the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the gate of NMOS transistor M3, and the gate of NMOS transistor M4, the drain of NMOS transistor M4 is connected to the drain of PMOS transistor M5, the drain of NMOS transistor M6, and the IO port IO_PAD, and the source of NMOS transistor M3 and the source of NMOS transistor M4 are grounded.
2. The low-level maintenance circuit for the floating state of an I / O port in a level conversion circuit according to claim 1, characterized in that: The signal VGATE is provided by the gate drive circuit.
3. A low-level maintenance circuit for an I / O port in a floating state as described in claim 2, characterized in that: The gate drive circuit includes a PMOS transistor M1, a resistor R1, and a capacitor C1. The source of the PMOS transistor M1 is connected to the power supply VCCA. The gate of the PMOS transistor M1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. The drain of the PMOS transistor M1 is connected to one end of the capacitor C1 and generates a signal VGATE. The other end of the capacitor C1 is grounded.
4. A low-level maintenance circuit for an I / O port in a floating state as described in claim 1, characterized in that: The gate of the PMOS transistor M5 is connected to the control signal OS_P, and the source of the PMOS transistor M5 is connected to the power supply VCCA.
5. A low-level maintenance circuit for an I / O port in a floating state as described in claim 1, characterized in that: The gate of the NMOS transistor M6 is connected to the control signal OS_N, and the source of the NMOS transistor M6 is grounded.
6. A low-level maintenance circuit for an I / O port in a floating state as described in claim 1, characterized in that: The size of PMOS transistor M2 is larger than that of PMOS transistor M5, so that the leakage current of PMOS transistor M2 is greater than that of PMOS transistor M5 in the off state.
7. A low-level maintenance circuit for an I / O port in a floating state as described in claim 6, characterized in that: The PMOS transistors M2 and M5 are on a single bare die unit DIE, and the PMOS transistors M2 and M5 are consistent with the process deviation.
8. A low-level maintenance circuit for an I / O port in a floating state as described in claim 1, characterized in that: The NMOS transistors M3 and M4 form an NMOS current mirror, and the current ratio flowing through the NMOS transistors M3 and M4 is 1:1.