A dual voltage magnetic random access memory word line drive circuit suitable for a wide temperature range

Abstract

This invention discloses a word line driving circuit for a dual-voltage magnetic random access memory (MRAM) suitable for a wide temperature range, including a control circuit, a word line decoding circuit, a word line level conversion circuit, and a word line voltage selection circuit. The circuit employs dual power supplies; the control circuit and word line decoding circuit operate in the low-voltage domain, while the word line level conversion circuit and word line voltage selection circuit operate in the high-voltage domain. Different voltages are output as word line voltages according to the required read / write operation. During a read operation, the low voltage is selected as the word line voltage, while during a write operation, the high voltage is selected. This invention uses dual-voltage domain transistors, effectively ensuring the entire circuit operates under dual power supplies. The transmission gate in the word line voltage selection circuit must also use high-voltage control to prevent the transmission gate from failing to close during read / write operations. This invention effectively guarantees MRAM write yield over a wide temperature range and is suitable for MRAM memory arrays with wide temperature range requirements.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and particularly relates to a word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range. Background Technology

[0002] As a crucial component of computer architecture, memory significantly impacts a computer's speed, integration, and power consumption. Low-power memory greatly contributes to reducing overall computer system power consumption. To balance high speed and large capacity, common computer storage often employs a hierarchical structure. High-density, high-capacity hard drives are used to store infrequently used programs and data, while high-speed main memory or cache is used for information exchange with the central processing unit (CPU). This hierarchical structure allows the computer's storage system to combine high speed and large capacity. With the continuous shrinking of semiconductor process feature sizes, the leakage current of CMOS transistors increases with the reduction in process size. Common SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) face increasingly serious leakage problems. An effective solution to this problem is to use non-volatile memory to replace SRAM and DRAM in constructing cache and main memory. This method allows the storage system to operate in a sleep state without losing data, thereby eliminating the static power consumption caused by leakage current. To reduce leakage problems, various non-volatile memories have been researched, mainly including phase-change random access memory (PCMRAM), magnetic random access memory, resistive random access memory (RRAM), etc. MRAM has proven its potential as a general-purpose memory. It boasts speeds and low latency similar to SRAM and DRAM. Due to its smaller cell area and higher density, MRAM can be seen as a future replacement for SRAM. Its non-volatility allows it to retain data even when power is off, eliminating leakage issues. Furthermore, compared to flash memory, MRAM offers numerous advantages such as higher read / write speeds, lower power consumption, longer write cycles, higher integration density, and scalability, making it suitable for applications like in-memory computing and neuromorphic computing. Another important feature of MRAM is its CMOS-compatible manufacturing process, enabling large-scale deployment. In emerging application areas such as the Internet of Things (IoT) and big data, the use of non-volatile memory is essential to save storage power as sensor terminals need to collect massive amounts of data. Moreover, as IoT devices evolve towards mobile devices, embedded MRAM (eMRAM) is receiving increasing attention in IoT applications. MRAM also presents higher reliability requirements for storage circuits operating over a wide temperature range in many fields.

[0003] Common MTJs (Metal-Transfer Junctions) use electric current to write information. An MTJ consists of two ferromagnetic layers of different thicknesses and a non-magnetic insulating layer. The two ferromagnetic layers are the free layer and the fixed layer, respectively. When the magnetization direction of the fixed layer is parallel to the magnetization direction of the free layer, the MTJ is in a parallel state and exhibits a low resistance (R0). P ), representing the data "0"; when the magnetization direction of the fixed layer of the MTJ is opposite to that of the free layer, the MTJ is in an antiparallel state, and the MTJ exhibits a high resistance (R). AP (), representing data "1", can have its state rewritten by a bidirectional write current higher than the critical current of the MTJ, allowing it to store different data. The key module architecture of the MRAM macrocell is shown in the attached figure. Figure 2 As shown. Similar to traditional memory design architectures, MRAM mainly consists of modules such as a memory array, decoding column select, driver circuit, sensitive amplifier, timing control module, and input / output circuit. MRAM primarily relies on magnetic tunnel junctions (MTJs) to store data. A common MRAM memory cell structure consists of an MTJ and access transistors. Each memory cell stores one bit of data, where the access transistors isolate selected cells from unselected cells. The two ends of the memory cell are connected to the bit line (BL) and the source line (SL), respectively. By adjusting the word line voltage, the memory cell can be selected and the current transmitted to the memory cell can be controlled. Because many fields require MRAM to operate over a wide temperature range, circuit devices including MTJs and CMOS are affected by temperature. Furthermore, with the continuous reduction in device size, the reliability and performance of memory are greatly challenged, placing higher reliability demands on memory circuits with wide temperature ranges. Since MRAM write operations require a large write current, a high write voltage or word line voltage is needed to ensure MRAM write yield, while MRAM read operations require a smaller read current. Write and read operations require significantly different voltages for the word lines, and a single word line power supply is insufficient to meet the read and write requirements of MRAM over a wide temperature range. Summary of the Invention

[0004] The purpose of this invention is to provide a word line drive circuit for dual-voltage magnetic random access memory (MRAM) suitable for a wide temperature range, so as to solve the technical problem that a single word line power supply cannot meet the write requirements of MRAM under a wide temperature range.

[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0006] A word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range includes the following circuits: a control circuit, a word line decoding circuit, a word line level conversion circuit, and a word line voltage selection circuit.

[0007] The control circuit generates a read enable signal ReadEN based on the input read / write control signal WEB, and generates a write enable signal WriteEN based on the input chip select signal CEB. It outputs a decoding enable signal EN to the word line decoder circuit. When the chip select signal is low, the word line decoder is enabled to decode the input word line address and generate the read / write enable signal when the memory performs read / write operations.

[0008] The word line decoding circuit is responsible for decoding the input word line address, and the output decoding result is used as the word line drive signal RWL during the read operation.

[0009] The word line level conversion circuit functions to convert the low-voltage word line drive signal RWL generated by the word line decoding circuit into a high-voltage word line drive signal WWL during a write operation.

[0010] The word line voltage selection circuit selects either a low-voltage word line drive signal RWL or a high-voltage word line drive signal WWL as the word line voltage based on the read enable signal ReadEN and the write enable signal WriteEN generated by the control circuit. The function of the word line voltage selection circuit is to select the lower voltage as the word line voltage during read operations and the higher voltage as the word line voltage during write operations.

[0011] Furthermore, the control circuit and word line decoding circuit operate in the low voltage domain, while the word line level conversion circuit and word line voltage selection circuit operate in the high voltage domain, employing dual-voltage domain transistors. Both the control circuit and word line decoding circuit use low-voltage transistors and operate at low voltage. The dual-voltage circuit matching problem refers to the need for a level converter circuit to perform voltage conversion when signals are transmitted between the high and low voltage domains, converting low-voltage signals to high voltage or vice versa.

[0012] Furthermore, read and write operations use different power supply voltage signals as word line voltages. A low voltage signal is used as the word line voltage during read operations, while a high voltage signal is used as the word line voltage during write operations.

[0013] Furthermore, the control circuit includes two inverters, two NOR gates, one OR gate, and one AND gate; the first inverter INV1 has its input connected to the read / write control signal WEB and its output signal WE; the second inverter INV2... Its input is connected to the chip select signal CEB, and its output is connected to the signal CE; the first NOR gate NOR1, here the NOR gate is a dual-input single-output gate, the input terminals are the first input terminal and the second input terminal respectively, its first input terminal is connected to the chip select signal CEB, its second input terminal is connected to the control signal WEB, and its output is the write enable signal WriteEN; the second NOR gate NOR2, its first input terminal is connected to the chip select signal CEB, its second input terminal is connected to the signal WE, and its output is the read enable signal ReadEN; the first OR gate OR, here the OR gate is a dual-input single-output gate, its input terminals are the first input terminal and the second input terminal respectively, its first input terminal is connected to the signal WriteEN, its second input terminal is connected to the signal ReadEN, and its output is the signal ENB; the first AND gate AND, here the AND gate is a dual-input single-output gate, its input terminals are the first input terminal and the second input terminal respectively, its first input terminal is connected to the signal ENB, its second input terminal is connected to the signal CE, and its output is the decode enable signal EN.

[0014] Furthermore, the word line decoding circuit completes the word line address decoding and outputs 2 based on the input N-bit word line address. N Bit address; the word line decoding circuit adopts a multi-level decoding structure, consisting of a 2-4 decoder, a 3-8 decoder, NOR gates, and AND gates.

[0015] Furthermore, the word line level conversion circuit consists of 2 N The system consists of several level converters. The input of the first level converter LS[0] is connected to the decoded output signal RWL[0], and the output signal is WWL[0]. The input of the second level converter LS[1] is connected to the decoded output signal RWL[1], and the output signal is WWL[1]. And so on, the input of the nth level converter LS[n] is connected to the decoded output signal RWL[n], and the output signal is WWL[n], until the 2nd level converter LS[n]. N Level converter LS[2] N The input terminal of ] is connected to the decoded output signal RWL[2] N ], output signal WWL[2 N ];

[0016] Each level shifter includes: a first inverter INV, whose input is connected to IN, output is connected to node INB, power supply is connected to power supply VDDL, and ground is connected to ground VSS; a first NMOS transistor MN1, whose gate is connected to IN, source is connected to ground VSS, and drain is connected to node N1; a second NMOS transistor MN2, whose gate is connected to node INB, source is connected to ground VSS, and drain is connected to node N2; a third NMOS transistor MN3, whose gate is connected to node N1, source is connected to ground VSS, and drain is connected to output OUT; a first PMOS transistor MP1, whose gate is connected to node N2, source is connected to power supply VDDH, and drain is connected to node N1; a second PMOS transistor MP2, whose gate is connected to node N1, source is connected to power supply VDDH, and drain is connected to node N2; and a third PMOS transistor MP3, whose gate is connected to node N1, source is connected to power supply VDDH, and drain is connected to output OUT.

[0017] Furthermore, the word line voltage selection circuit includes 2 N Each of the following gating circuits contains four input terminals and one output terminal: the first input terminal of the first gating circuit MUX[0] is connected to signal WWL[0], the second input terminal is connected to signal RWL[0], and the output is WL[0]. The first input terminal of the second gating circuit MUX[1] is connected to signal WWL[1], the second input terminal is connected to signal RWL[1], and the output is WL[1]. This continues until the 2Nth gating circuit MUX[2] is connected to signal WWL[n], the second input terminal is connected to signal RWL[n], and the output is WL[n]. N The first input terminal of ] is connected to the signal WWL[2] N The second input terminal is connected to signal RWL[2]. N Output WL[2] N The WriteEN enable signal is connected to the third input terminal of the first gating circuit MUX[0] to the second... N MUX [2] N The third input terminal of the first strobe circuit MUX[0]; the read enable signal ReadEN is connected to the fourth input terminal of the first strobe circuit MUX[0] to the second input terminal. N MUX [2] N The fourth input terminal of ].

[0018] Furthermore, the gating circuit includes two level shifters and two transmission gates. Each level shifter has one input and two outputs. The first level shifter, LS1, has its input connected to the signal WriteEN, its first output connected to the signal OUTB1, and its second output connected to the signal OUT1. The second level shifter, LS2, has its input connected to the signal ReadEN, its first output connected to the signal OUTB2, and its second output connected to the signal OUT2. The two level shifters convert the read / write enable signal into two complementary signals to control the transmission gates. Each transmission gate consists of an NMOS and a PMOS transistor. It includes two control terminals, an input terminal and an output terminal; the two control terminals of the first transmission gate TG1 are connected to the outputs OUTB1 and OUT1 of the first level converter, respectively, the input terminal is connected to the signal WWL[0], and the output terminal is connected to the signal WL[O]; the two control terminals of the second transmission gate TG2 are connected to the outputs OUTB2 and OUT2 of the second level converter, respectively, the input terminal is connected to the signal RWL[0], and the output terminal is connected to the signal WL[O]; since a higher word line voltage is used when writing to the memory cell, the two transmission gates must also use high voltage domain transistors.

[0019] Furthermore, the level shifter in the gating circuit includes: a first inverter INV, whose input is connected to IN, output is connected to INB, power supply is connected to power supply VDDL, and ground is connected to ground VSS; a first NMOS transistor MN1, whose gate is connected to IN, source is connected to ground VSS, and drain is connected to the first node N1; a second NMOS transistor MN2, whose gate is connected to INB, source is connected to ground VSS, and drain is connected to the second node N2; a third NMOS transistor MN3, whose gate is connected to the first node N1, source is connected to ground VSS, and drain outputs OUT; and a fourth NMOS transistor MN4, whose gate is connected to IN. The second node N2 has its source connected to ground VSS and its drain connected to output OUTB; the first PMOS transistor MP1 has its gate connected to the second node N2, its source connected to power supply VDDH, and its drain connected to the first node N1; the second PMOS transistor MP2 has its gate connected to the first node N1, its source connected to power supply VDDH, and its drain connected to the second node N2; the third PMOS transistor MP3 has its gate connected to the first node N1, its source connected to power supply VDDH, and its drain connected to output OUT; the fourth PMOS transistor MP4 has its gate connected to the second node N2, its source connected to power supply VDDH, and its drain connected to output OUTB.

[0020] The word line driving circuit of the present invention, applicable to a wide temperature range dual-voltage magnetic random access memory, has the following advantages:

[0021] (1) The present invention adopts a dual power supply voltage design. For write operations, a higher voltage is used as the word line voltage, which can reduce write latency and improve write yield; for read operations, a lower voltage is used as the word line voltage, which can reduce read damage and reduce read power consumption.

[0022] (2) In the control circuit of the present invention, the word line decoding circuit operates in the low voltage domain, and the level conversion circuit and the word line voltage selection circuit operate in the high voltage domain. The level converter is used to realize the voltage conversion of the two voltage domain signals. The transistors of the two voltage domains are used to effectively reduce the area energy consumption.

[0023] (3) The word line voltage selection circuit of the present invention converts the read / write enable signal into a high voltage signal to control the transmission gate, which can prevent the transmission gate from being unable to close due to the high voltage of the word line or write word line signal during read / write operations, and ensure that the correct voltage can be selected as the word line voltage during read / write operations. Attached Figure Description

[0024] Figure 1 A key module architecture diagram of an MRAM macrocell in the prior art is provided for the background art.

[0025] Figure 2 A word line drive circuit diagram for a dual-voltage magnetic random access memory suitable for a wide temperature range is provided as an embodiment of the present invention;

[0026] Figure 3 This is a control circuit structure diagram provided in an embodiment of the present invention;

[0027] Figure 4 This is a structural diagram of the word line decoding circuit provided in an embodiment of the present invention;

[0028] Figure 5 This is a structural diagram of the word line level conversion circuit provided in an embodiment of the present invention;

[0029] Figure 6 This is a structural diagram of the word line voltage selection circuit group provided in an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the working waveform of the word line voltage driving circuit provided in an embodiment of the present invention;

[0031] Figure 8 This invention provides the write yield of MRAM at -55℃ with VDDH values ​​of 2V, 2.1V, and 2.2V for SS, TT, and FF process angles, respectively.

[0032] Figure 9 This invention provides the write yield of MRAM at 25°C under SS, TT, and FF process angles with VDDH values ​​of 2V, 2.1V, and 2.2V, respectively.

[0033] Figure 10 This refers to the write yield of MRAM at 125°C under SS, TT, and FF process angles with VDDH values ​​of 2V, 2.1V, and 2.2V, respectively. Detailed Implementation

[0034] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an explanation of a word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range.

[0035] The word line drive circuit structure of the dual-voltage magnetic random access memory (DRAM) applicable to a wide temperature range, as described in this invention, is as follows: Figure 2 As shown, the circuit includes the following components: a control circuit, a word line decoding circuit, a word line level conversion circuit, and a word line voltage selection circuit. This circuit is responsible for decoding the high-order address bits and driving the word lines according to the control signal. During read operations, it provides a lower word line voltage RWL as the word line voltage, and during write operations, it provides a higher word line voltage WWL. In this embodiment, the total number of word lines WL is 2. N , where N is 8.

[0036] Control circuit structure as follows Figure 3 As shown, it includes two inverters, two NOR gates, one OR gate, and one AND gate. CEB is the chip select enable signal. When CEB is low, the word line decoding circuit enable signal EN is high, and the word line decoding circuit starts working, decoding the N-bit word line address into 2. N Bit output. WEB is the read / write control signal. When WEB is low, the output read enable signal ReadEN is high; when WEB is high, the output write enable signal WriteEN is high.

[0037] Word line decoding circuit, such as Figure 4 As shown, the word-line decoding circuit selects the corresponding memory unit based on the input binary address information. If the word-line decoding circuit adopts a single-stage decoding method, a decoder with an N-bit address input requires a total of 2... N The presence of N-input AND gates significantly increases the area and delay of the word line decoding circuit, thus a multi-stage decoding structure is often used. For an 8-bit word line address input, the row address X[7:0] is divided into two decoding paths. Address X[7:5] is processed by a 3-to-8 decoder and a three-input NOR gate to generate 8 block row selection signals. Address X[4:0] is processed by a 5-to-32 decoder composed of a 2-to-4 decoder and a 3-to-8 decoder to generate intra-block row selection signals. Finally, 256 word line signals (RWL[255:0]) are generated through 256 AND gates.

[0038] The structure of the word line level conversion circuit is as follows: Figure 5 As shown, by 2 NComposed of two level converters, responsible for the word line decoding circuit 2 N The output signal is converted from 1.2V VDDL to 2.1V VDDH. The level shifter is a cross-coupled structure, mainly composed of 3 PMOS, 3 NMOS, and one inverter. The inverter is driven by VDDL, and the other 6 MOS transistors are all high-voltage transistors. The main principle of this level shifter is as follows: when the input IN, which serves as the gate voltage of MN1, is 1.2V, MN1 is turned on, while INB is 0V and MN2 is turned off. Therefore, the voltage at node A is lower. The cross-coupled structure formed by MP1 and MP2 continuously amplifies the voltages at nodes N1 and N2. Through positive feedback, the voltage at node N1 eventually becomes low, and the inverter composed of MP3 and MN3 outputs a 2.1V signal.

[0039] The structure of the word line voltage selection circuit is as follows: Figure 6 As shown, including 2 N Each gating circuit consists of two transmission gates and two level shifters. The level shifters control the transmission gates to turn on or off based on the read / write enable. The two inputs of each gating circuit are the output RWL[2] of the word line decoding circuit. N :0], and the word line level conversion circuit outputs WWL[2 N When the write enable signal WriteEN is high, the level converter LS1 outputs a high voltage at node OUT1 and a low voltage at OUTB1, turns on transmission gate TG2, selects the higher WWL output, and provides VDDH voltage to WL; when the read enable signal ReadEN is high, the level converter LS2 outputs a high voltage at node OUT2 and a low voltage at OUTB2, turns on transmission gate TG2, selects the lower RWL signal output, and provides 1.2V voltage to WL. The level converter in the selection circuit differs from the previous one; it consists of four PMOS transistors, four NMOS transistors, and an inverter. The inverter uses low-voltage domain transistors, operating at VDDL, while the other MOS transistors use high-voltage domain transistors, operating at high voltage VDDH. Its specific principle is the same as the level converter in the word line voltage conversion circuit, but to drive the transmission gate, a complementary signal must be output, so a complementary signal OUTB to the inverter output signal OUT, composed of MP4 and MN4, is added. Although the output voltage of the word line drive is 1.2V during read operations, the corresponding transmission gate control voltage must be 2.1V. This is to prevent the 2.1V voltage on WL from turning on the PMOS in the transmission gate during write operations. Therefore, the control signals ReadEN and WriteEN of the transmission gate must be converted to 2.1V using a level converter.

[0040] Figure 7The diagram illustrates the waveforms of the word line drive circuit, primarily showing the operation of the entire circuit during continuous writing and reading of the memory cells corresponding to two word line addresses X1 and X2. When the chip select enable signal goes low, the read / write enable signals ReadEN and WriteEN are output, and the word line decoding circuit begins decoding. The input word line addresses X1 and X2 are decoded, resulting in outputs RWL[X1] and RWL[X2] as VDDL. These RWL[X1] and RWL[X2] are then boosted by a level converter to WWL[X1] and WWL[X2] with voltages of VDDH. When the read / write control signal WEB is low, the output write enable signal is high, selecting the higher WWL[X1] and WWL[X2] as the word line drive voltage. When the read / write control signal WEB goes high, the read enable signal is high, selecting the lower RWL[X1] and RWL[X2] as the word line drive voltage.

[0041] Figure 8 The figure shows the write yield of MRAM at -55℃ with VDDH values ​​of 2V, 2.1V, and 2.2V, including process corners such as TT, SS, and FF. All results in the figure are average write yields for high-resistivity to low-resistivity transitions (AP2P) and low-resistivity to high-resistivity transitions (P2AP). The figure demonstrates that MRAM exhibits high write yields at various process corners.

[0042] Figure 9 The figure shows the write yield of MRAM at 25°C with VDDH values ​​of 2V, 2.1V, and 2.2V, including process corners such as TT, SS, and FF. All results in the figure are averages of the write yield for transitions from high-resistivity to low-resistivity (AP2P) and from low-resistivity to high-resistivity (P2AP). The figure shows that MRAM maintains high write yield across different process corners, even at the SS process corner. Furthermore, the write yield increases with increasing VDDH, reaching 100% in all cases when VDDH is at its highest value of 2.2V.

[0043] Figure 10 The figure shows the write yield of MRAM at 125℃ with VDDH values ​​of 2V, 2.1V, and 2.2V, including process corners such as TT, SS, and FF. All results in the figure are the average write yields for high-resistivity to low-resistivity (AP2P) and low-resistivity to high-resistivity (P2AP) states. Figure 8 The results show that MRAM has a high write yield at different process corners.

[0044] This invention discloses a word line driving circuit for a dual-voltage magnetic random access memory (MRAM) suitable for a wide temperature range, comprising a control circuit, a word line decoding circuit, a word line level conversion circuit, and a word line voltage selection circuit. Since MRAM write operations require higher current and word line voltages than read operations over a wide temperature range (-55℃ to 125℃), a single word line voltage cannot meet the read and write requirements of MRAM over this wide temperature range. This invention decodes the input word line address and outputs different word line voltages according to the required read and write operations. The circuit employs dual word line voltages and dual voltage domain transistors, utilizing a level converter to achieve voltage conversion. A lower word line voltage is used when performing read operations on memory cells, while a higher word line voltage is used when performing write operations on memory cells, allowing different word line voltages to be used for read and write operations of memory cells. The control circuit, word line decoding circuit, and other circuit components in this invention use low-voltage domain transistors and operate at low voltages. The level shifter and word line voltage selection circuit in this circuit both employ high-voltage domain transistors, operating at high voltages. The use of high-voltage domain transistors in the transmission gates of the word line voltage selection circuit prevents the transmission gates from conducting due to high voltages on the bit lines during write operations. This invention effectively guarantees the write yield of MRAM over a wide temperature range and is suitable for MRAM memory arrays requiring wide temperature range operation.

[0045] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range, characterized in that, Includes the following circuits: control circuit, word line decoding circuit, word line level conversion circuit, and word line voltage selection circuit; The control circuit generates a read enable signal ReadEN based on the input read / write control signal WEB, generates a write enable signal WriteEN based on the input chip select signal CEB, and outputs a decoding enable signal EN to the word line decoding circuit. The word line decoding circuit is responsible for decoding the input word line address, and the output decoding result is used as the word line drive signal RWL during the read operation. The word line level conversion circuit functions to convert the low-voltage word line drive signal RWL generated by the word line decoding circuit into a high-voltage word line drive signal WWL during a write operation. The word line voltage selection circuit selects either a low-voltage word line drive signal RWL or a high-voltage word line drive signal WWL as the word line voltage based on the read enable signal ReadEN and the write enable signal WriteEN generated by the control circuit. The control circuit includes two inverters, two NOR gates, one OR gate, and one AND gate; the first inverter INV1 has its input connected to the read / write control signal WEB and its output signal WE; the second inverter INV2... Its input is connected to the chip select signal CEB, and its output is connected to the signal CE; the first NOR gate NOR1, here the NOR gate is a dual-input single-output gate, the input terminals are the first input terminal and the second input terminal respectively, its first input terminal is connected to the chip select signal CEB, its second input terminal is connected to the control signal WEB, and its output is the write enable signal WriteEN; the second NOR gate NOR2, its first input terminal is connected to the chip select signal CEB, its second input terminal is connected to the signal WE, and its output is the read enable signal ReadEN; the first OR gate OR, here the OR gate is a dual-input single-output gate, its input terminals are the first input terminal and the second input terminal respectively, its first input terminal is connected to the signal WriteEN, its second input terminal is connected to the signal ReadEN, and its output is the signal ENB; the first AND gate AND, here the AND gate is a dual-input single-output gate, its input terminals are the first input terminal and the second input terminal respectively, its first input terminal is connected to the signal ENB, its second input terminal is connected to the signal CE, and its output is the decode enable signal EN.

2. The word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 1, characterized in that, The control circuit and word line decoding circuit operate in the low voltage domain, while the word line level conversion circuit and word line voltage selection circuit operate in the high voltage domain, employing dual-voltage domain transistors.

3. The word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 1, characterized in that, Read and write operations use different power supply voltage signals as word line voltages. A low voltage signal is used as the word line voltage during read operations, and a high voltage signal is used as the word line voltage during write operations.

4. The word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 1, characterized in that, The word line decoding circuit decodes the input N-bit word line address and outputs 2. N Bit address; the word line decoding circuit adopts a multi-level decoding structure, consisting of a 2-4 decoder, a 3-8 decoder, NOR gates, and AND gates.

5. The word line drive circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 1, characterized in that, The word line level conversion circuit consists of 2 N The system consists of several level converters. The input of the first level converter LS[0] is connected to the decoded output signal RWL[0], and the output signal is WWL[0]. The input of the second level converter LS[1] is connected to the decoded output signal RWL[1], and the output signal is WWL[1]. And so on, the input of the nth level converter LS[n] is connected to the decoded output signal RWL[n], and the output signal is WWL[n], until the 2nd level converter LS[n]. N Level converter LS[2] N The input terminal of ] is connected to the decoded output signal RWL[2] N ], output signal WWL[2 N ]; Each level shifter includes: a first inverter INV, whose input is connected to IN, output is connected to node INB, power supply is connected to power supply VDDL, and ground is connected to ground VSS; a first NMOS transistor MN1, whose gate is connected to IN, source is connected to ground VSS, and drain is connected to node N1; a second NMOS transistor MN2, whose gate is connected to node INB, source is connected to ground VSS, and drain is connected to node N2; a third NMOS transistor MN3, whose gate is connected to node N1, source is connected to ground VSS, and drain is connected to output OUT; a first PMOS transistor MP1, whose gate is connected to node N2, source is connected to power supply VDDH, and drain is connected to node N1; a second PMOS transistor MP2, whose gate is connected to node N1, source is connected to power supply VDDH, and drain is connected to node N2; and a third PMOS transistor MP3, whose gate is connected to node N1, source is connected to power supply VDDH, and drain is connected to output OUT.

6. The word line driving circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 1, characterized in that, The word line voltage selection circuit includes 2 N Each of the following gating circuits contains four input terminals and one output terminal: the first input terminal of the first gating circuit MUX[0] is connected to signal WWL[0], the second input terminal is connected to signal RWL[0], and the output is WL[0]. The first input terminal of the second gating circuit MUX[1] is connected to signal WWL[1], the second input terminal is connected to signal RWL[1], and the output is WL[1]. This continues until the 2Nth gating circuit MUX[2] is connected to signal WWL[n], the second input terminal is connected to signal RWL[n], and the output is WL[n]. N The first input terminal of ] is connected to the signal WWL[2] N The second input terminal is connected to signal RWL[2]. N Output WL[2] N The WriteEN signal is connected to the third input of the first gating circuit MUX[0] to the second... N MUX [2] N The third input terminal of ]; the read enable signal ReadEN is connected to the fourth input terminal of the first gating circuit MUX[0] to the second N MUX [2] N The fourth input terminal of ].

7. The word line drive circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 6, characterized in that, The gating circuit includes two level converters and two transmission gates; each level converter here has one input terminal and two output terminals. The input terminal of the first level converter LS1 is connected to the signal WriteEN, the first output terminal is connected to the signal OUTB1, and the second output terminal is connected to the signal OUT1. The second level converter LS2 has its input terminal connected to the signal ReadEN, its first output terminal connected to the signal OUTB2, and its second output terminal connected to the signal OUT2. The two level converters convert the read / write enable signals into two complementary signals to control the transmission gates. Each transmission gate consists of an NMOS and a PMOS, including upper and lower control terminals, an input terminal, and an output terminal. The upper and lower control terminals of the first transmission gate TG1 are connected to the outputs OUTB1 and OUT1 of the first level converter, respectively. The input terminal is connected to the signal WWL[0], and the output terminal is connected to the signal WL[O]. The upper and lower control terminals of the second transmission gate TG2 are connected to the outputs OUTB2 and OUT2 of the second level converter, respectively. The input terminal is connected to the signal RWL[0], and the output terminal is connected to the signal WL[O]. Since a higher word line voltage is used when writing to the memory cell, the two transmission gates must also use high-voltage transistors.

8. The word line drive circuit for a dual-voltage magnetic random access memory suitable for a wide temperature range according to claim 7, characterized in that, The level shifter in the gating circuit includes: a first inverter INV, whose input is connected to IN, output is connected to INB, power supply is connected to power supply VDDL, and ground is connected to ground VSS; a first NMOS transistor MN1, whose gate is connected to IN, source is connected to ground VSS, and drain is connected to the first node N1; a second NMOS transistor MN2, whose gate is connected to INB, source is connected to ground VSS, and drain is connected to the second node N2; a third NMOS transistor MN3, whose gate is connected to the first node N1, source is connected to ground VSS, and drain outputs OUT; and a fourth NMOS transistor MN4, whose gate is connected to the first node N1. Two nodes N2, with the source connected to ground VSS and the drain connected to the output OUTB; the first PMOS transistor MP1, with its gate connected to the second node N2, its source connected to the power supply VDDH, and its drain connected to the first node N1; the second PMOS transistor MP2, with its gate connected to the first node N1, its source connected to the power supply VDDH, and its drain connected to the second node N2; the third PMOS transistor MP3, with its gate connected to the first node N1, its source connected to the power supply VDDH, and its drain connected to the output OUT; the fourth PMOS transistor MP4, with its gate connected to the second node N2, its source connected to the power supply VDDH, and its drain connected to the output OUTB.

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